Alex Forencich
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6154506c0a
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axis: Use reset synchronizer module in AXI stream async FIFO
Signed-off-by: Alex Forencich <alex@alexforencich.com>
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2025-02-20 12:44:23 -08:00 |
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Alex Forencich
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689cd34739
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eth: Add additional Ethernet MAC-related timing constraints
Signed-off-by: Alex Forencich <alex@alexforencich.com>
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2025-02-16 22:30:15 -08:00 |
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Alex Forencich
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ffaf05f2d1
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eth: Add RGMII Ethernet MAC module and testbench
Signed-off-by: Alex Forencich <alex@alexforencich.com>
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2025-02-16 22:05:59 -08:00 |
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Alex Forencich
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fab49d1435
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eth: Add RGMII PHY interface module
Signed-off-by: Alex Forencich <alex@alexforencich.com>
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2025-02-16 21:50:42 -08:00 |
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Alex Forencich
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c0583aaff5
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eth: Add GMII Ethernet MAC module and testbench
Signed-off-by: Alex Forencich <alex@alexforencich.com>
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2025-02-16 21:37:12 -08:00 |
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Alex Forencich
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51d6919622
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ptp: Add timing constraints for PTP components
Signed-off-by: Alex Forencich <alex@alexforencich.com>
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2025-02-16 11:29:57 -08:00 |
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Alex Forencich
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69e5ae8545
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axis: Add AXI stream async FIFO module and testbench
Signed-off-by: Alex Forencich <alex@alexforencich.com>
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2025-02-06 00:46:39 -08:00 |
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Alex Forencich
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9cc4cbc670
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sync: Add reset synchronizer module
Signed-off-by: Alex Forencich <alex@alexforencich.com>
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2025-02-03 23:42:47 -08:00 |
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