Alex Forencich
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be80d4e964
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pcie: Tie off AXIL user signals in PCIe AXI lite master module
Signed-off-by: Alex Forencich <alex@alexforencich.com>
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2026-02-21 02:48:18 -08:00 |
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Alex Forencich
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9b55a08465
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pcie: Cast widths in VPD implementation
Signed-off-by: Alex Forencich <alex@alexforencich.com>
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2026-02-20 22:14:01 -08:00 |
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Alex Forencich
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9630afce1d
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pcie: Add VPD capability implementation for UltraScale+
Signed-off-by: Alex Forencich <alex@alexforencich.com>
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2026-02-16 13:37:35 -08:00 |
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Alex Forencich
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ddac834e99
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pcie: Add configuration shim for UltraScale
Signed-off-by: Alex Forencich <alex@alexforencich.com>
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2026-02-05 14:35:01 -08:00 |
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Alex Forencich
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245e71551b
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pcie: Add MSI shim for UltraScale
Signed-off-by: Alex Forencich <alex@alexforencich.com>
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2025-12-23 18:03:56 -08:00 |
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Alex Forencich
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004246608e
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Use logic instead of reg
Signed-off-by: Alex Forencich <alex@alexforencich.com>
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2025-11-07 02:14:19 -08:00 |
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Alex Forencich
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bf584147a1
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pcie: Clean up AXI lite interface width handling in PCIe US AXI lite master
Signed-off-by: Alex Forencich <alex@alexforencich.com>
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2025-08-29 17:59:56 -07:00 |
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Alex Forencich
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b3441f6408
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pcie: Rename enable to en in PCIe US AXI lite master
Signed-off-by: Alex Forencich <alex@alexforencich.com>
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2025-08-29 17:59:33 -07:00 |
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Alex Forencich
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63c961cab4
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pcie: Fix some corner cases in PCIe US AXI lite master
Signed-off-by: Alex Forencich <alex@alexforencich.com>
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2025-08-29 16:50:31 -07:00 |
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Alex Forencich
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b5c9c02b03
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pcie: Add UltraScale PCIe AXI Lite Master module and testbench
Signed-off-by: Alex Forencich <alex@alexforencich.com>
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2025-08-25 22:39:28 -07:00 |
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Alex Forencich
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66b53d98a2
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Reorganize repository
Signed-off-by: Alex Forencich <alex@alexforencich.com>
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2025-05-18 12:25:59 -07:00 |
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