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372 lines
12 KiB
Systemverilog
372 lines
12 KiB
Systemverilog
// SPDX-License-Identifier: CERN-OHL-S-2.0
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/*
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Copyright (c) 2018-2025 FPGA Ninja, LLC
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Authors:
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- Alex Forencich
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*/
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`resetall
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`timescale 1ns / 1ps
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`default_nettype none
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/*
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* AXI4 lite register (read)
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*/
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module taxi_axil_register_rd #
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(
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// AR channel register type
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// 0 to bypass, 1 for simple buffer
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parameter AR_REG_TYPE = 1,
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// R channel register type
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// 0 to bypass, 1 for simple buffer
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parameter R_REG_TYPE = 1
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)
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(
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input wire logic clk,
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input wire logic rst,
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/*
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* AXI4-Lite slave interface
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*/
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taxi_axil_if.rd_slv s_axil_rd,
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/*
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* AXI4-Lite master interface
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*/
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taxi_axil_if.rd_mst m_axil_rd
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);
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// extract parameters
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localparam DATA_W = s_axil_rd.DATA_W;
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localparam ADDR_W = s_axil_rd.ADDR_W;
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localparam STRB_W = s_axil_rd.STRB_W;
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localparam logic ARUSER_EN = s_axil_rd.ARUSER_EN && m_axil_rd.ARUSER_EN;
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localparam ARUSER_W = s_axil_rd.ARUSER_W;
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localparam logic RUSER_EN = s_axil_rd.RUSER_EN && m_axil_rd.RUSER_EN;
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localparam RUSER_W = s_axil_rd.RUSER_W;
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if (m_axil_rd.DATA_W != DATA_W)
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$fatal(0, "Error: Interface DATA_W parameter mismatch (instance %m)");
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if (m_axil_rd.STRB_W != STRB_W)
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$fatal(0, "Error: Interface STRB_W parameter mismatch (instance %m)");
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// AR channel
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if (AR_REG_TYPE > 1) begin
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// skid buffer, no bubble cycles
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// datapath registers
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logic s_axil_arready_reg = 1'b0;
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logic [ADDR_W-1:0] m_axil_araddr_reg = '0;
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logic [2:0] m_axil_arprot_reg = '0;
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logic [ARUSER_W-1:0] m_axil_aruser_reg = '0;
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logic m_axil_arvalid_reg = 1'b0, m_axil_arvalid_next;
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logic [ADDR_W-1:0] temp_m_axil_araddr_reg = '0;
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logic [2:0] temp_m_axil_arprot_reg = '0;
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logic [ARUSER_W-1:0] temp_m_axil_aruser_reg = '0;
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logic temp_m_axil_arvalid_reg = 1'b0, temp_m_axil_arvalid_next;
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// datapath control
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logic store_axil_ar_input_to_output;
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logic store_axil_ar_input_to_temp;
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logic store_axil_ar_temp_to_output;
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assign s_axil_rd.arready = s_axil_arready_reg;
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assign m_axil_rd.araddr = m_axil_araddr_reg;
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assign m_axil_rd.arprot = m_axil_arprot_reg;
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assign m_axil_rd.aruser = ARUSER_EN ? m_axil_aruser_reg : '0;
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assign m_axil_rd.arvalid = m_axil_arvalid_reg;
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// enable ready input next cycle if output is ready or the temp reg will not be filled on the next cycle (output reg empty or no input)
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wire s_axil_arready_early = m_axil_rd.arready || (!temp_m_axil_arvalid_reg && (!m_axil_arvalid_reg || !s_axil_rd.arvalid));
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always_comb begin
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// transfer sink ready state to source
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m_axil_arvalid_next = m_axil_arvalid_reg;
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temp_m_axil_arvalid_next = temp_m_axil_arvalid_reg;
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store_axil_ar_input_to_output = 1'b0;
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store_axil_ar_input_to_temp = 1'b0;
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store_axil_ar_temp_to_output = 1'b0;
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if (s_axil_arready_reg) begin
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// input is ready
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if (m_axil_rd.arready || !m_axil_arvalid_reg) begin
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// output is ready or currently not valid, transfer data to output
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m_axil_arvalid_next = s_axil_rd.arvalid;
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store_axil_ar_input_to_output = 1'b1;
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end else begin
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// output is not ready, store input in temp
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temp_m_axil_arvalid_next = s_axil_rd.arvalid;
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store_axil_ar_input_to_temp = 1'b1;
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end
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end else if (m_axil_rd.arready) begin
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// input is not ready, but output is ready
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m_axil_arvalid_next = temp_m_axil_arvalid_reg;
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temp_m_axil_arvalid_next = 1'b0;
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store_axil_ar_temp_to_output = 1'b1;
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end
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end
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always_ff @(posedge clk) begin
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s_axil_arready_reg <= s_axil_arready_early;
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m_axil_arvalid_reg <= m_axil_arvalid_next;
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temp_m_axil_arvalid_reg <= temp_m_axil_arvalid_next;
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// datapath
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if (store_axil_ar_input_to_output) begin
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m_axil_araddr_reg <= s_axil_rd.araddr;
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m_axil_arprot_reg <= s_axil_rd.arprot;
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m_axil_aruser_reg <= s_axil_rd.aruser;
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end else if (store_axil_ar_temp_to_output) begin
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m_axil_araddr_reg <= temp_m_axil_araddr_reg;
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m_axil_arprot_reg <= temp_m_axil_arprot_reg;
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m_axil_aruser_reg <= temp_m_axil_aruser_reg;
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end
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if (store_axil_ar_input_to_temp) begin
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temp_m_axil_araddr_reg <= s_axil_rd.araddr;
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temp_m_axil_arprot_reg <= s_axil_rd.arprot;
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temp_m_axil_aruser_reg <= s_axil_rd.aruser;
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end
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if (rst) begin
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s_axil_arready_reg <= 1'b0;
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m_axil_arvalid_reg <= 1'b0;
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temp_m_axil_arvalid_reg <= 1'b0;
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end
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end
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end else if (AR_REG_TYPE == 1) begin
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// simple register, inserts bubble cycles
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// datapath registers
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logic s_axil_arready_reg = 1'b0;
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logic [ADDR_W-1:0] m_axil_araddr_reg = '0;
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logic [2:0] m_axil_arprot_reg = '0;
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logic [ARUSER_W-1:0] m_axil_aruser_reg = '0;
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logic m_axil_arvalid_reg = 1'b0, m_axil_arvalid_next;
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// datapath control
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logic store_axil_ar_input_to_output;
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assign s_axil_rd.arready = s_axil_arready_reg;
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assign m_axil_rd.araddr = m_axil_araddr_reg;
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assign m_axil_rd.arprot = m_axil_arprot_reg;
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assign m_axil_rd.aruser = ARUSER_EN ? m_axil_aruser_reg : '0;
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assign m_axil_rd.arvalid = m_axil_arvalid_reg;
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// enable ready input next cycle if output buffer will be empty
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wire s_axil_arready_early = !m_axil_arvalid_next;
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always_comb begin
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// transfer sink ready state to source
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m_axil_arvalid_next = m_axil_arvalid_reg;
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store_axil_ar_input_to_output = 1'b0;
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if (s_axil_arready_reg) begin
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m_axil_arvalid_next = s_axil_rd.arvalid;
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store_axil_ar_input_to_output = 1'b1;
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end else if (m_axil_rd.arready) begin
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m_axil_arvalid_next = 1'b0;
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end
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end
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always_ff @(posedge clk) begin
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s_axil_arready_reg <= s_axil_arready_early;
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m_axil_arvalid_reg <= m_axil_arvalid_next;
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// datapath
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if (store_axil_ar_input_to_output) begin
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m_axil_araddr_reg <= s_axil_rd.araddr;
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m_axil_arprot_reg <= s_axil_rd.arprot;
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m_axil_aruser_reg <= s_axil_rd.aruser;
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end
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if (rst) begin
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s_axil_arready_reg <= 1'b0;
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m_axil_arvalid_reg <= 1'b0;
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end
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end
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end else begin
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// bypass AR channel
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assign m_axil_rd.araddr = s_axil_rd.araddr;
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assign m_axil_rd.arprot = s_axil_rd.arprot;
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assign m_axil_rd.aruser = ARUSER_EN ? s_axil_rd.aruser : '0;
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assign m_axil_rd.arvalid = s_axil_rd.arvalid;
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assign s_axil_rd.arready = m_axil_rd.arready;
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end
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// R channel
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if (R_REG_TYPE > 1) begin
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// skid buffer, no bubble cycles
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// datapath registers
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logic m_axil_rready_reg = 1'b0;
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logic [DATA_W-1:0] s_axil_rdata_reg = '0;
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logic [1:0] s_axil_rresp_reg = 2'b0;
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logic [RUSER_W-1:0] s_axil_ruser_reg = '0;
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logic s_axil_rvalid_reg = 1'b0, s_axil_rvalid_next;
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logic [DATA_W-1:0] temp_s_axil_rdata_reg = '0;
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logic [1:0] temp_s_axil_rresp_reg = 2'b0;
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logic [RUSER_W-1:0] temp_s_axil_ruser_reg = '0;
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logic temp_s_axil_rvalid_reg = 1'b0, temp_s_axil_rvalid_next;
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// datapath control
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logic store_axil_r_input_to_output;
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logic store_axil_r_input_to_temp;
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logic store_axil_r_temp_to_output;
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assign m_axil_rd.rready = m_axil_rready_reg;
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assign s_axil_rd.rdata = s_axil_rdata_reg;
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assign s_axil_rd.rresp = s_axil_rresp_reg;
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assign s_axil_rd.ruser = RUSER_EN ? s_axil_ruser_reg : '0;
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assign s_axil_rd.rvalid = s_axil_rvalid_reg;
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// enable ready input next cycle if output is ready or the temp reg will not be filled on the next cycle (output reg empty or no input)
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wire m_axil_rready_early = s_axil_rd.rready || (!temp_s_axil_rvalid_reg && (!s_axil_rvalid_reg || !m_axil_rd.rvalid));
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always_comb begin
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// transfer sink ready state to source
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s_axil_rvalid_next = s_axil_rvalid_reg;
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temp_s_axil_rvalid_next = temp_s_axil_rvalid_reg;
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store_axil_r_input_to_output = 1'b0;
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store_axil_r_input_to_temp = 1'b0;
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store_axil_r_temp_to_output = 1'b0;
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if (m_axil_rready_reg) begin
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// input is ready
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if (s_axil_rd.rready || !s_axil_rvalid_reg) begin
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// output is ready or currently not valid, transfer data to output
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s_axil_rvalid_next = m_axil_rd.rvalid;
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store_axil_r_input_to_output = 1'b1;
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end else begin
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// output is not ready, store input in temp
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temp_s_axil_rvalid_next = m_axil_rd.rvalid;
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store_axil_r_input_to_temp = 1'b1;
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end
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end else if (s_axil_rd.rready) begin
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// input is not ready, but output is ready
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s_axil_rvalid_next = temp_s_axil_rvalid_reg;
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temp_s_axil_rvalid_next = 1'b0;
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store_axil_r_temp_to_output = 1'b1;
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end
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end
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always_ff @(posedge clk) begin
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m_axil_rready_reg <= m_axil_rready_early;
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s_axil_rvalid_reg <= s_axil_rvalid_next;
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temp_s_axil_rvalid_reg <= temp_s_axil_rvalid_next;
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// datapath
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if (store_axil_r_input_to_output) begin
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s_axil_rdata_reg <= m_axil_rd.rdata;
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s_axil_rresp_reg <= m_axil_rd.rresp;
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s_axil_ruser_reg <= m_axil_rd.ruser;
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end else if (store_axil_r_temp_to_output) begin
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s_axil_rdata_reg <= temp_s_axil_rdata_reg;
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s_axil_rresp_reg <= temp_s_axil_rresp_reg;
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s_axil_ruser_reg <= temp_s_axil_ruser_reg;
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end
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if (store_axil_r_input_to_temp) begin
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temp_s_axil_rdata_reg <= m_axil_rd.rdata;
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temp_s_axil_rresp_reg <= m_axil_rd.rresp;
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temp_s_axil_ruser_reg <= m_axil_rd.ruser;
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end
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if (rst) begin
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m_axil_rready_reg <= 1'b0;
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s_axil_rvalid_reg <= 1'b0;
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temp_s_axil_rvalid_reg <= 1'b0;
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end
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end
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end else if (R_REG_TYPE == 1) begin
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// simple register, inserts bubble cycles
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// datapath registers
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logic m_axil_rready_reg = 1'b0;
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logic [DATA_W-1:0] s_axil_rdata_reg = '0;
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logic [1:0] s_axil_rresp_reg = 2'b0;
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logic [RUSER_W-1:0] s_axil_ruser_reg = '0;
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logic s_axil_rvalid_reg = 1'b0, s_axil_rvalid_next;
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// datapath control
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logic store_axil_r_input_to_output;
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assign m_axil_rd.rready = m_axil_rready_reg;
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assign s_axil_rd.rdata = s_axil_rdata_reg;
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assign s_axil_rd.rresp = s_axil_rresp_reg;
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assign s_axil_rd.ruser = RUSER_EN ? s_axil_ruser_reg : '0;
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assign s_axil_rd.rvalid = s_axil_rvalid_reg;
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// enable ready input next cycle if output buffer will be empty
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wire m_axil_rready_early = !s_axil_rvalid_next;
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always_comb begin
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// transfer sink ready state to source
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s_axil_rvalid_next = s_axil_rvalid_reg;
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store_axil_r_input_to_output = 1'b0;
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if (m_axil_rready_reg) begin
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s_axil_rvalid_next = m_axil_rd.rvalid;
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store_axil_r_input_to_output = 1'b1;
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end else if (s_axil_rd.rready) begin
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s_axil_rvalid_next = 1'b0;
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end
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end
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always_ff @(posedge clk) begin
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m_axil_rready_reg <= m_axil_rready_early;
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s_axil_rvalid_reg <= s_axil_rvalid_next;
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// datapath
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if (store_axil_r_input_to_output) begin
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s_axil_rdata_reg <= m_axil_rd.rdata;
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s_axil_rresp_reg <= m_axil_rd.rresp;
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s_axil_ruser_reg <= m_axil_rd.ruser;
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end
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if (rst) begin
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m_axil_rready_reg <= 1'b0;
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s_axil_rvalid_reg <= 1'b0;
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end
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end
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end else begin
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// bypass R channel
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assign s_axil_rd.rdata = m_axil_rd.rdata;
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assign s_axil_rd.rresp = m_axil_rd.rresp;
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assign s_axil_rd.ruser = RUSER_EN ? m_axil_rd.ruser : '0;
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assign s_axil_rd.rvalid = m_axil_rd.rvalid;
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assign m_axil_rd.rready = s_axil_rd.rready;
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end
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endmodule
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`resetall
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