Alex Forencich 1c686391ab lss: Refactor UART module to split out and share baud rate generation logic ...

Signed-off-by: Alex Forencich <alex@alexforencich.com>

2025-03-11 23:09:19 -07:00

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axi

axi: Normalize unpacked dimension

2025-03-06 16:16:29 -08:00

axis

axis: Implement tstrb in pipeline FIFO

2025-03-06 16:18:20 -08:00

eth

eth: Use unpacked arrays for multidimensional ports

2025-03-07 11:05:58 -08:00

io

io: Add LED shift register driver module

2025-02-25 15:44:57 -08:00

lfsr

lfsr: Add LFSR descrambler module and testbench

2025-02-05 15:29:12 -08:00

lss

lss: Refactor UART module to split out and share baud rate generation logic

2025-03-11 23:09:19 -07:00

prim

prim: Add arbiter module and testbench

2025-02-28 21:04:49 -08:00

ptp

ptp: Add PTP TD rel2tod timestamp reconstruction module and testbench

2025-02-13 22:07:46 -08:00

sync

sync: Add signal synchronizer module

2025-02-03 23:43:18 -08:00

xfcp

xfcp: Rename signals based on upstream/downstsream port role and data direction to simplify connections

2025-03-11 18:33:57 -07:00