Alex Forencich 5966d05740 prim: Add priority encoder and testbench ...

Signed-off-by: Alex Forencich <alex@alexforencich.com>

2025-02-28 21:04:32 -08:00

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axi

axi: Replace reg with logic in AXI lite RAM

2025-02-27 13:44:18 -08:00

axis

axis: Add AXI stream multiplexer module and testbench

2025-02-27 13:28:02 -08:00

eth

eth: Use signal sync module for RGMII MAC speed detection

2025-02-25 17:12:50 -08:00

io

io: Add LED shift register driver module

2025-02-25 15:44:57 -08:00

lfsr

lfsr: Add LFSR descrambler module and testbench

2025-02-05 15:29:12 -08:00

lss

lss: Extract UART data width setting from interface

2025-02-26 14:15:42 -08:00

prim

prim: Add priority encoder and testbench

2025-02-28 21:04:32 -08:00

ptp

ptp: Add PTP TD rel2tod timestamp reconstruction module and testbench

2025-02-13 22:07:46 -08:00

sync

sync: Add signal synchronizer module

2025-02-03 23:43:18 -08:00