Alex Forencich 6054f76a17 eth: Add Ethernet example design for NetFPGA SUME ...

Signed-off-by: Alex Forencich <alex@alexforencich.com>

2025-11-08 19:46:20 -08:00

..

apb

apb: Add APB dual-port RAM module and testbench

2025-09-30 15:25:21 -07:00

axi

Use logic instead of reg

2025-11-07 02:14:19 -08:00

axis

Use logic instead of reg

2025-11-07 02:14:19 -08:00

dma

Use logic instead of reg

2025-11-07 02:14:19 -08:00

eth

eth: Add Ethernet example design for NetFPGA SUME

2025-11-08 19:46:20 -08:00

hip/rtl/us

eth: Add reset logic, QPLL control signals, and additional configuration parameters for US/US+ GTH/GTY transceivers

2025-05-21 21:06:45 -07:00

io/rtl

Clean up always blocks

2025-11-07 01:51:18 -08:00

lfsr

Use logic instead of reg

2025-11-07 02:14:19 -08:00

lss

Use logic instead of reg

2025-11-07 02:14:19 -08:00

math

math: Add MT19937 Mersenne Twister PRNG module and testbench

2025-10-15 22:14:21 -07:00

pcie

Use logic instead of reg

2025-11-07 02:14:19 -08:00

prim

Reorganize repository

2025-05-18 12:25:59 -07:00

ptp

Use logic instead of reg

2025-11-07 02:14:19 -08:00

stats

stats: Clean up casts

2025-09-07 14:58:16 -07:00

sync

Reorganize repository

2025-05-18 12:25:59 -07:00

xfcp

Use logic instead of reg

2025-11-07 02:14:19 -08:00

zircon

Clean up always blocks

2025-11-07 01:51:18 -08:00