Alex Forencich 0044782224 eth: Remove FIFO pipeline registers for statistics FIFOs in distributed RAM ...

Signed-off-by: Alex Forencich <alex@alexforencich.com>

2025-04-17 00:34:22 -07:00

..

axi

axi: Normalize unpacked dimension

2025-03-06 16:16:29 -08:00

axis

axis: Fix parameter accesses in interface arrays

2025-04-09 00:08:16 -07:00

eth

eth: Remove FIFO pipeline registers for statistics FIFOs in distributed RAM

2025-04-17 00:34:22 -07:00

hip/us

hip: Add support for optional phase shifter clock to fractional MMCM module

2025-03-17 21:05:49 -07:00

io

io: Add LED shift register driver module

2025-02-25 15:44:57 -08:00

lfsr

lfsr: Add LFSR descrambler module and testbench

2025-02-05 15:29:12 -08:00

lss

lss: Remove redundant tristate control outputs on I2C modules

2025-03-19 12:41:39 -07:00

prim

prim: Add arbiter module and testbench

2025-02-28 21:04:49 -08:00

ptp

ptp: Add PTP TD rel2tod timestamp reconstruction module and testbench

2025-02-13 22:07:46 -08:00

stats

stats: Exclude strings from statistics counts

2025-04-16 22:41:57 -07:00

sync

sync: Add signal synchronizer module

2025-02-03 23:43:18 -08:00

xfcp

xfcp: Collect statistics strings

2025-04-16 22:42:58 -07:00