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https://github.com/fpganinja/taxi.git
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464 lines
16 KiB
Systemverilog
464 lines
16 KiB
Systemverilog
// SPDX-License-Identifier: CERN-OHL-S-2.0
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/*
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Copyright (c) 2018-2025 FPGA Ninja, LLC
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Authors:
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- Alex Forencich
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*/
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`resetall
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`timescale 1ns / 1ps
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`default_nettype none
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/*
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* XGMII 10GBASE-R decoder
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*/
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module taxi_xgmii_baser_dec #
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(
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parameter DATA_W = 64,
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parameter CTRL_W = (DATA_W/8),
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parameter HDR_W = 2,
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parameter logic GBX_IF_EN = 1'b0
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)
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(
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input wire logic clk,
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input wire logic rst,
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/*
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* 10GBASE-R encoded input
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*/
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input wire logic [DATA_W-1:0] encoded_rx_data,
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input wire logic encoded_rx_data_valid = 1'b1,
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input wire logic [HDR_W-1:0] encoded_rx_hdr,
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input wire logic encoded_rx_hdr_valid = 1'b1,
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/*
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* XGMII interface
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*/
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output wire logic [DATA_W-1:0] xgmii_rxd,
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output wire logic [CTRL_W-1:0] xgmii_rxc,
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output wire logic xgmii_rx_valid,
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/*
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* Status
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*/
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output wire logic rx_bad_block,
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output wire logic rx_sequence_error
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);
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localparam DATA_W_INT = 64;
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localparam CTRL_W_INT = 8;
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localparam SEG_CNT = DATA_W_INT / DATA_W;
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// check configuration
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if (DATA_W != 32 && DATA_W != 64)
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$fatal(0, "Error: Interface width must be 32 or 64");
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if (CTRL_W * 8 != DATA_W)
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$fatal(0, "Error: Interface requires byte (8-bit) granularity");
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if (HDR_W != 2)
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$fatal(0, "Error: HDR_W must be 2");
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localparam [7:0]
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XGMII_IDLE = 8'h07,
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XGMII_LPI = 8'h06,
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XGMII_START = 8'hfb,
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XGMII_TERM = 8'hfd,
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XGMII_ERROR = 8'hfe,
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XGMII_SEQ_OS = 8'h9c,
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XGMII_RES_0 = 8'h1c,
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XGMII_RES_1 = 8'h3c,
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XGMII_RES_2 = 8'h7c,
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XGMII_RES_3 = 8'hbc,
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XGMII_RES_4 = 8'hdc,
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XGMII_RES_5 = 8'hf7,
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XGMII_SIG_OS = 8'h5c;
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localparam [6:0]
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CTRL_IDLE = 7'h00,
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CTRL_LPI = 7'h06,
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CTRL_ERROR = 7'h1e,
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CTRL_RES_0 = 7'h2d,
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CTRL_RES_1 = 7'h33,
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CTRL_RES_2 = 7'h4b,
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CTRL_RES_3 = 7'h55,
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CTRL_RES_4 = 7'h66,
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CTRL_RES_5 = 7'h78;
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localparam [3:0]
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O_SEQ_OS = 4'h0,
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O_SIG_OS = 4'hf;
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localparam [1:0]
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SYNC_DATA = 2'b10,
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SYNC_CTRL = 2'b01;
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localparam [7:0]
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BLOCK_TYPE_CTRL = 8'h1e, // C7 C6 C5 C4 C3 C2 C1 C0 BT
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BLOCK_TYPE_OS_4 = 8'h2d, // D7 D6 D5 O4 C3 C2 C1 C0 BT
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BLOCK_TYPE_START_4 = 8'h33, // D7 D6 D5 C3 C2 C1 C0 BT
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BLOCK_TYPE_OS_START = 8'h66, // D7 D6 D5 O0 D3 D2 D1 BT
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BLOCK_TYPE_OS_04 = 8'h55, // D7 D6 D5 O4 O0 D3 D2 D1 BT
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BLOCK_TYPE_START_0 = 8'h78, // D7 D6 D5 D4 D3 D2 D1 BT
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BLOCK_TYPE_OS_0 = 8'h4b, // C7 C6 C5 C4 O0 D3 D2 D1 BT
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BLOCK_TYPE_TERM_0 = 8'h87, // C7 C6 C5 C4 C3 C2 C1 BT
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BLOCK_TYPE_TERM_1 = 8'h99, // C7 C6 C5 C4 C3 C2 D0 BT
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BLOCK_TYPE_TERM_2 = 8'haa, // C7 C6 C5 C4 C3 D1 D0 BT
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BLOCK_TYPE_TERM_3 = 8'hb4, // C7 C6 C5 C4 D2 D1 D0 BT
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BLOCK_TYPE_TERM_4 = 8'hcc, // C7 C6 C5 D3 D2 D1 D0 BT
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BLOCK_TYPE_TERM_5 = 8'hd2, // C7 C6 D4 D3 D2 D1 D0 BT
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BLOCK_TYPE_TERM_6 = 8'he1, // C7 D5 D4 D3 D2 D1 D0 BT
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BLOCK_TYPE_TERM_7 = 8'hff; // D6 D5 D4 D3 D2 D1 D0 BT
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wire [DATA_W_INT-1:0] encoded_rx_data_int;
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wire encoded_rx_data_valid_int;
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wire [HDR_W-1:0] encoded_rx_hdr_int;
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logic [DATA_W_INT-1:0] decoded_ctrl;
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logic [CTRL_W_INT-1:0] decode_err;
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logic [DATA_W_INT-1:0] xgmii_rxd_reg = '0, xgmii_rxd_next;
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logic [CTRL_W_INT-1:0] xgmii_rxc_reg = '0, xgmii_rxc_next;
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logic [SEG_CNT-1:0] xgmii_rx_valid_reg = '0, xgmii_rx_valid_next;
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logic rx_bad_block_reg = 1'b0, rx_bad_block_next;
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logic rx_sequence_error_reg = 1'b0, rx_sequence_error_next;
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logic frame_reg = 1'b0, frame_next;
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assign xgmii_rxd = xgmii_rxd_reg[DATA_W-1:0];
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assign xgmii_rxc = xgmii_rxc_reg[CTRL_W-1:0];
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assign xgmii_rx_valid = GBX_IF_EN ? xgmii_rx_valid_reg[0] : 1'b1;
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assign rx_bad_block = rx_bad_block_reg;
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assign rx_sequence_error = rx_sequence_error_reg;
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if (DATA_W == 64) begin : repack_in
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assign encoded_rx_data_int = encoded_rx_data;
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assign encoded_rx_data_valid_int = GBX_IF_EN ? encoded_rx_data_valid : 1'b1;
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assign encoded_rx_hdr_int = encoded_rx_hdr;
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end else begin : repack_in
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logic [DATA_W_INT-DATA_W-1:0] encoded_rx_data_reg = '0;
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logic encoded_rx_data_valid_reg = '0;
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logic [HDR_W-1:0] encoded_rx_hdr_reg = '0;
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assign encoded_rx_data_int = {encoded_rx_data, encoded_rx_data_reg};
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assign encoded_rx_data_valid_int = encoded_rx_data_valid_reg && (GBX_IF_EN ? encoded_rx_data_valid : 1'b1);
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assign encoded_rx_hdr_int = encoded_rx_hdr_reg;
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always_ff @(posedge clk) begin
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if (!GBX_IF_EN || encoded_rx_data_valid) begin
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encoded_rx_data_reg <= encoded_rx_data;
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encoded_rx_data_valid_reg <= encoded_rx_hdr_valid;
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if (encoded_rx_hdr_valid) begin
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encoded_rx_hdr_reg <= encoded_rx_hdr;
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end
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end
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if (rst) begin
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encoded_rx_data_valid_reg <= '0;
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end
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end
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end
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always_comb begin
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xgmii_rxd_next = {CTRL_W_INT{XGMII_ERROR}};
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xgmii_rxc_next = '1;
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xgmii_rx_valid_next = '0;
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rx_bad_block_next = 1'b0;
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rx_sequence_error_next = 1'b0;
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frame_next = frame_reg;
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for (integer i = 0; i < CTRL_W_INT; i = i + 1) begin
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case (encoded_rx_data_int[7*i+8 +: 7])
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CTRL_IDLE: begin
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decoded_ctrl[8*i +: 8] = XGMII_IDLE;
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decode_err[i] = 1'b0;
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end
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CTRL_LPI: begin
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decoded_ctrl[8*i +: 8] = XGMII_LPI;
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decode_err[i] = 1'b0;
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end
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CTRL_ERROR: begin
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decoded_ctrl[8*i +: 8] = XGMII_ERROR;
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decode_err[i] = 1'b0;
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end
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CTRL_RES_0: begin
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decoded_ctrl[8*i +: 8] = XGMII_RES_0;
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decode_err[i] = 1'b0;
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end
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CTRL_RES_1: begin
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decoded_ctrl[8*i +: 8] = XGMII_RES_1;
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decode_err[i] = 1'b0;
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end
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CTRL_RES_2: begin
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decoded_ctrl[8*i +: 8] = XGMII_RES_2;
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decode_err[i] = 1'b0;
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end
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CTRL_RES_3: begin
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decoded_ctrl[8*i +: 8] = XGMII_RES_3;
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decode_err[i] = 1'b0;
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end
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CTRL_RES_4: begin
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decoded_ctrl[8*i +: 8] = XGMII_RES_4;
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decode_err[i] = 1'b0;
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end
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CTRL_RES_5: begin
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decoded_ctrl[8*i +: 8] = XGMII_RES_5;
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decode_err[i] = 1'b0;
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end
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default: begin
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decoded_ctrl[8*i +: 8] = XGMII_ERROR;
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decode_err[i] = 1'b1;
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end
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endcase
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end
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if (SEG_CNT > 1) begin
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// repack output
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// disable broken verilator linter (unreachable code by parameter value)
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// verilator lint_off WIDTH
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// verilator lint_off SELRANGE
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xgmii_rxd_next = {{CTRL_W{XGMII_ERROR}}, xgmii_rxd_reg[DATA_W_INT-1:DATA_W]};
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xgmii_rxc_next = {{CTRL_W{1'b1}}, xgmii_rxc_reg[CTRL_W_INT-1:CTRL_W]};
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xgmii_rx_valid_next = {1'b0, xgmii_rx_valid_reg[SEG_CNT-1:1]};
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// verilator lint_on WIDTH
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// verilator lint_on SELRANGE
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end
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if (!encoded_rx_data_valid_int) begin
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// wait for data
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end else if (encoded_rx_hdr_int[0] == 0) begin
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// data block
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xgmii_rxd_next = encoded_rx_data_int;
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xgmii_rxc_next = 8'h00;
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xgmii_rx_valid_next = '1;
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rx_bad_block_next = 1'b0;
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end else begin
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// control block
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// use only four bits of block type for reduced fanin
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xgmii_rx_valid_next = '1;
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case (encoded_rx_data_int[7:4])
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BLOCK_TYPE_CTRL[7:4]: begin
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// C7 C6 C5 C4 C3 C2 C1 C0 BT
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xgmii_rxd_next = decoded_ctrl;
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xgmii_rxc_next = 8'hff;
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rx_bad_block_next = decode_err != 0;
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end
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BLOCK_TYPE_OS_4[7:4]: begin
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// D7 D6 D5 O4 C3 C2 C1 C0 BT
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xgmii_rxd_next[31:0] = decoded_ctrl[31:0];
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xgmii_rxc_next[3:0] = 4'hf;
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xgmii_rxd_next[63:40] = encoded_rx_data_int[63:40];
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xgmii_rxc_next[7:4] = 4'h1;
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if (encoded_rx_data_int[39:36] == O_SEQ_OS) begin
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xgmii_rxd_next[39:32] = XGMII_SEQ_OS;
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rx_bad_block_next = decode_err[3:0] != 0;
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end else begin
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xgmii_rxd_next[39:32] = XGMII_ERROR;
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rx_bad_block_next = 1'b1;
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end
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end
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BLOCK_TYPE_START_4[7:4]: begin
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// D7 D6 D5 C3 C2 C1 C0 BT
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xgmii_rxd_next = {encoded_rx_data_int[63:40], XGMII_START, decoded_ctrl[31:0]};
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xgmii_rxc_next = 8'h1f;
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rx_bad_block_next = decode_err[3:0] != 0;
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rx_sequence_error_next = frame_reg;
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frame_next = 1'b1;
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end
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BLOCK_TYPE_OS_START[7:4]: begin
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// D7 D6 D5 O0 D3 D2 D1 BT
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xgmii_rxd_next[31:8] = encoded_rx_data_int[31:8];
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xgmii_rxc_next[3:0] = 4'h1;
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if (encoded_rx_data_int[35:32] == O_SEQ_OS) begin
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xgmii_rxd_next[7:0] = XGMII_SEQ_OS;
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rx_bad_block_next = 1'b0;
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end else begin
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xgmii_rxd_next[7:0] = XGMII_ERROR;
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rx_bad_block_next = 1'b1;
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end
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xgmii_rxd_next[63:32] = {encoded_rx_data_int[63:40], XGMII_START};
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xgmii_rxc_next[7:4] = 4'h1;
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rx_sequence_error_next = frame_reg;
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frame_next = 1'b1;
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end
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BLOCK_TYPE_OS_04[7:4]: begin
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// D7 D6 D5 O4 O0 D3 D2 D1 BT
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rx_bad_block_next = 1'b0;
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xgmii_rxd_next[31:8] = encoded_rx_data_int[31:8];
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xgmii_rxc_next[3:0] = 4'h1;
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if (encoded_rx_data_int[35:32] == O_SEQ_OS) begin
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xgmii_rxd_next[7:0] = XGMII_SEQ_OS;
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end else begin
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xgmii_rxd_next[7:0] = XGMII_ERROR;
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rx_bad_block_next = 1'b1;
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end
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xgmii_rxd_next[63:40] = encoded_rx_data_int[63:40];
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xgmii_rxc_next[7:4] = 4'h1;
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if (encoded_rx_data_int[39:36] == O_SEQ_OS) begin
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xgmii_rxd_next[39:32] = XGMII_SEQ_OS;
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end else begin
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xgmii_rxd_next[39:32] = XGMII_ERROR;
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rx_bad_block_next = 1'b1;
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end
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end
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BLOCK_TYPE_START_0[7:4]: begin
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// D7 D6 D5 D4 D3 D2 D1 BT
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xgmii_rxd_next = {encoded_rx_data_int[63:8], XGMII_START};
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xgmii_rxc_next = 8'h01;
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rx_bad_block_next = 1'b0;
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rx_sequence_error_next = frame_reg;
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frame_next = 1'b1;
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end
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BLOCK_TYPE_OS_0[7:4]: begin
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// C7 C6 C5 C4 O0 D3 D2 D1 BT
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xgmii_rxd_next[31:8] = encoded_rx_data_int[31:8];
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xgmii_rxc_next[3:0] = 4'h1;
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if (encoded_rx_data_int[35:32] == O_SEQ_OS) begin
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xgmii_rxd_next[7:0] = XGMII_SEQ_OS;
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rx_bad_block_next = decode_err[7:4] != 0;
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end else begin
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xgmii_rxd_next[7:0] = XGMII_ERROR;
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rx_bad_block_next = 1'b1;
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end
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xgmii_rxd_next[63:32] = decoded_ctrl[63:32];
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xgmii_rxc_next[7:4] = 4'hf;
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end
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BLOCK_TYPE_TERM_0[7:4]: begin
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// C7 C6 C5 C4 C3 C2 C1 BT
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xgmii_rxd_next = {decoded_ctrl[63:8], XGMII_TERM};
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xgmii_rxc_next = 8'hff;
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rx_bad_block_next = decode_err[7:1] != 0;
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rx_sequence_error_next = !frame_reg;
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frame_next = 1'b0;
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end
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BLOCK_TYPE_TERM_1[7:4]: begin
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// C7 C6 C5 C4 C3 C2 D0 BT
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xgmii_rxd_next = {decoded_ctrl[63:16], XGMII_TERM, encoded_rx_data_int[15:8]};
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xgmii_rxc_next = 8'hfe;
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rx_bad_block_next = decode_err[7:2] != 0;
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rx_sequence_error_next = !frame_reg;
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frame_next = 1'b0;
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end
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BLOCK_TYPE_TERM_2[7:4]: begin
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// C7 C6 C5 C4 C3 D1 D0 BT
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xgmii_rxd_next = {decoded_ctrl[63:24], XGMII_TERM, encoded_rx_data_int[23:8]};
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xgmii_rxc_next = 8'hfc;
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rx_bad_block_next = decode_err[7:3] != 0;
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rx_sequence_error_next = !frame_reg;
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frame_next = 1'b0;
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end
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BLOCK_TYPE_TERM_3[7:4]: begin
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// C7 C6 C5 C4 D2 D1 D0 BT
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xgmii_rxd_next = {decoded_ctrl[63:32], XGMII_TERM, encoded_rx_data_int[31:8]};
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xgmii_rxc_next = 8'hf8;
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rx_bad_block_next = decode_err[7:4] != 0;
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rx_sequence_error_next = !frame_reg;
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frame_next = 1'b0;
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end
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BLOCK_TYPE_TERM_4[7:4]: begin
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// C7 C6 C5 D3 D2 D1 D0 BT
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xgmii_rxd_next = {decoded_ctrl[63:40], XGMII_TERM, encoded_rx_data_int[39:8]};
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xgmii_rxc_next = 8'hf0;
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rx_bad_block_next = decode_err[7:5] != 0;
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rx_sequence_error_next = !frame_reg;
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frame_next = 1'b0;
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end
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BLOCK_TYPE_TERM_5[7:4]: begin
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// C7 C6 D4 D3 D2 D1 D0 BT
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xgmii_rxd_next = {decoded_ctrl[63:48], XGMII_TERM, encoded_rx_data_int[47:8]};
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xgmii_rxc_next = 8'he0;
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rx_bad_block_next = decode_err[7:6] != 0;
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rx_sequence_error_next = !frame_reg;
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frame_next = 1'b0;
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end
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BLOCK_TYPE_TERM_6[7:4]: begin
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// C7 D5 D4 D3 D2 D1 D0 BT
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xgmii_rxd_next = {decoded_ctrl[63:56], XGMII_TERM, encoded_rx_data_int[55:8]};
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xgmii_rxc_next = 8'hc0;
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rx_bad_block_next = decode_err[7] != 0;
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rx_sequence_error_next = !frame_reg;
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frame_next = 1'b0;
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end
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BLOCK_TYPE_TERM_7[7:4]: begin
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// D6 D5 D4 D3 D2 D1 D0 BT
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xgmii_rxd_next = {XGMII_TERM, encoded_rx_data_int[63:8]};
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xgmii_rxc_next = 8'h80;
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rx_bad_block_next = 1'b0;
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rx_sequence_error_next = !frame_reg;
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frame_next = 1'b0;
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end
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|
default: begin
|
|
// invalid block type
|
|
xgmii_rxd_next = {CTRL_W_INT{XGMII_ERROR}};
|
|
xgmii_rxc_next = '1;
|
|
rx_bad_block_next = 1'b1;
|
|
end
|
|
endcase
|
|
end
|
|
|
|
// check all block type bits to detect bad encodings
|
|
if (!encoded_rx_data_valid_int) begin
|
|
// wait for block
|
|
end else if (encoded_rx_hdr_int == SYNC_DATA) begin
|
|
// data - nothing encoded
|
|
end else if (encoded_rx_hdr_int == SYNC_CTRL) begin
|
|
// control - check for bad block types
|
|
case (encoded_rx_data_int[7:0])
|
|
BLOCK_TYPE_CTRL: begin end
|
|
BLOCK_TYPE_OS_4: begin end
|
|
BLOCK_TYPE_START_4: begin end
|
|
BLOCK_TYPE_OS_START: begin end
|
|
BLOCK_TYPE_OS_04: begin end
|
|
BLOCK_TYPE_START_0: begin end
|
|
BLOCK_TYPE_OS_0: begin end
|
|
BLOCK_TYPE_TERM_0: begin end
|
|
BLOCK_TYPE_TERM_1: begin end
|
|
BLOCK_TYPE_TERM_2: begin end
|
|
BLOCK_TYPE_TERM_3: begin end
|
|
BLOCK_TYPE_TERM_4: begin end
|
|
BLOCK_TYPE_TERM_5: begin end
|
|
BLOCK_TYPE_TERM_6: begin end
|
|
BLOCK_TYPE_TERM_7: begin end
|
|
default: begin
|
|
// invalid block type
|
|
xgmii_rxd_next = {CTRL_W_INT{XGMII_ERROR}};
|
|
xgmii_rxc_next = '1;
|
|
rx_bad_block_next = 1'b1;
|
|
end
|
|
endcase
|
|
end else begin
|
|
// invalid header
|
|
xgmii_rxd_next = {CTRL_W_INT{XGMII_ERROR}};
|
|
xgmii_rxc_next = '1;
|
|
rx_bad_block_next = 1'b1;
|
|
end
|
|
end
|
|
|
|
always_ff @(posedge clk) begin
|
|
xgmii_rxd_reg <= xgmii_rxd_next;
|
|
xgmii_rxc_reg <= xgmii_rxc_next;
|
|
xgmii_rx_valid_reg <= xgmii_rx_valid_next;
|
|
|
|
rx_bad_block_reg <= rx_bad_block_next;
|
|
rx_sequence_error_reg <= rx_sequence_error_next;
|
|
frame_reg <= frame_next;
|
|
|
|
if (rst) begin
|
|
xgmii_rx_valid_reg <= '0;
|
|
frame_reg <= 1'b0;
|
|
end
|
|
end
|
|
|
|
endmodule
|
|
|
|
`resetall
|