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729bf794272450d9ff465cda8a5ee7edededd98a
taxi/src/eth/rtl
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Alex Forencich 729bf79427 eth: Move link speed detection logic from MAC wrapper to PHY interface 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
2025-11-13 21:27:03 -08:00
..
us
eth: Fix widths
2025-11-13 18:07:13 -08:00
taxi_axis_baser_rx_32.sv
eth: Normalize signal and register names in MAC modules
2025-10-05 18:11:27 -07:00
taxi_axis_baser_rx_64.sv
eth: Push CRC computation logic towards input in 64-bit BASE-R RX module
2025-10-05 19:34:27 -07:00
taxi_axis_baser_tx_32.sv
eth: Normalize signal and register names in MAC modules
2025-10-05 18:11:27 -07:00
taxi_axis_baser_tx_64.sv
eth: Normalize signal and register names in MAC modules
2025-10-05 18:11:27 -07:00
taxi_axis_gmii_rx.sv
eth: Normalize signal and register names in MAC modules
2025-10-05 18:11:27 -07:00
taxi_axis_gmii_tx.sv
eth: Normalize signal and register names in MAC modules
2025-10-05 18:11:27 -07:00
taxi_axis_xgmii_rx_32.sv
eth: Push CRC computation logic towards input in 32-bit XGMII RX module
2025-10-05 19:09:59 -07:00
taxi_axis_xgmii_rx_64.sv
eth: Push CRC computation logic towards input in 64-bit XGMII RX module
2025-10-05 19:10:30 -07:00
taxi_axis_xgmii_tx_32.sv
eth: Normalize signal and register names in MAC modules
2025-10-05 18:11:27 -07:00
taxi_axis_xgmii_tx_64.sv
eth: Normalize signal and register names in MAC modules
2025-10-05 18:11:27 -07:00
taxi_eth_mac_1g_fifo.f
Reorganize repository
2025-05-18 12:25:59 -07:00
taxi_eth_mac_1g_fifo.sv
Reorganize repository
2025-05-18 12:25:59 -07:00
taxi_eth_mac_1g_gmii_fifo.f
Reorganize repository
2025-05-18 12:25:59 -07:00
taxi_eth_mac_1g_gmii_fifo.sv
Use logic instead of reg
2025-11-07 02:14:19 -08:00
taxi_eth_mac_1g_gmii.f
Reorganize repository
2025-05-18 12:25:59 -07:00
taxi_eth_mac_1g_gmii.sv
eth: Move link speed detection logic from MAC wrapper to PHY interface
2025-11-13 21:27:03 -08:00
taxi_eth_mac_1g_rgmii_fifo.f
Reorganize repository
2025-05-18 12:25:59 -07:00
taxi_eth_mac_1g_rgmii_fifo.sv
Use logic instead of reg
2025-11-07 02:14:19 -08:00
taxi_eth_mac_1g_rgmii.f
Reorganize repository
2025-05-18 12:25:59 -07:00
taxi_eth_mac_1g_rgmii.sv
eth: Move link speed detection logic from MAC wrapper to PHY interface
2025-11-13 21:27:03 -08:00
taxi_eth_mac_1g.f
eth: Use tie and null_src modules
2025-11-06 09:35:26 -08:00
taxi_eth_mac_1g.sv
eth: Use tie and null_src modules
2025-11-06 09:35:26 -08:00
taxi_eth_mac_10g_fifo.f
Reorganize repository
2025-05-18 12:25:59 -07:00
taxi_eth_mac_10g_fifo.sv
eth: Remove extraneous defaults
2025-06-13 16:45:00 -07:00
taxi_eth_mac_10g.f
eth: Use tie and null_src modules
2025-11-06 09:35:26 -08:00
taxi_eth_mac_10g.sv
eth: Use tie and null_src modules
2025-11-06 09:35:26 -08:00
taxi_eth_mac_mii_fifo.f
Reorganize repository
2025-05-18 12:25:59 -07:00
taxi_eth_mac_mii_fifo.sv
Reorganize repository
2025-05-18 12:25:59 -07:00
taxi_eth_mac_mii.f
Reorganize repository
2025-05-18 12:25:59 -07:00
taxi_eth_mac_mii.sv
Reorganize repository
2025-05-18 12:25:59 -07:00
taxi_eth_mac_phy_10g_fifo.f
Reorganize repository
2025-05-18 12:25:59 -07:00
taxi_eth_mac_phy_10g_fifo.sv
Use logic instead of reg
2025-11-07 02:14:19 -08:00
taxi_eth_mac_phy_10g_rx.f
eth: Add 32-bit support to combined MAC+PCS module
2025-06-17 21:37:34 -07:00
taxi_eth_mac_phy_10g_rx.sv
eth: Add 32-bit support to combined MAC+PCS module
2025-06-17 21:37:34 -07:00
taxi_eth_mac_phy_10g_tx.f
eth: Add 32-bit support to combined MAC+PCS module
2025-06-17 21:37:34 -07:00
taxi_eth_mac_phy_10g_tx.sv
eth: Add 32-bit support to combined MAC+PCS module
2025-06-17 21:37:34 -07:00
taxi_eth_mac_phy_10g.f
eth: Use tie and null_src modules
2025-11-06 09:35:26 -08:00
taxi_eth_mac_phy_10g.sv
eth: Use tie and null_src modules
2025-11-06 09:35:26 -08:00
taxi_eth_mac_stats.f
Reorganize repository
2025-05-18 12:25:59 -07:00
taxi_eth_mac_stats.sv
Reorganize repository
2025-05-18 12:25:59 -07:00
taxi_eth_phy_10g_rx_ber_mon.sv
eth: Fix RX BER monitor when gearbox is enabled
2025-06-15 12:54:01 -07:00
taxi_eth_phy_10g_rx_frame_sync.sv
eth: PHY parameter clean-up, support 32-bit mode in PHY interface modules
2025-06-14 22:54:09 -07:00
taxi_eth_phy_10g_rx_if.f
Reorganize repository
2025-05-18 12:25:59 -07:00
taxi_eth_phy_10g_rx_if.sv
Clean up always blocks
2025-11-07 01:51:18 -08:00
taxi_eth_phy_10g_rx_watchdog.sv
eth: PHY parameter clean-up, support 32-bit mode in PHY interface modules
2025-06-14 22:54:09 -07:00
taxi_eth_phy_10g_rx.f
eth: Support 32 bit mode in BASE-R PHY
2025-06-15 13:00:14 -07:00
taxi_eth_phy_10g_rx.sv
eth: Support 32 bit mode in BASE-R PHY
2025-06-15 13:00:14 -07:00
taxi_eth_phy_10g_tx_if.f
Reorganize repository
2025-05-18 12:25:59 -07:00
taxi_eth_phy_10g_tx_if.sv
Use logic instead of reg
2025-11-07 02:14:19 -08:00
taxi_eth_phy_10g_tx.f
eth: Support 32 bit mode in BASE-R PHY
2025-06-15 13:00:14 -07:00
taxi_eth_phy_10g_tx.sv
eth: Support 32 bit mode in BASE-R PHY
2025-06-15 13:00:14 -07:00
taxi_eth_phy_10g.f
Reorganize repository
2025-05-18 12:25:59 -07:00
taxi_eth_phy_10g.sv
eth: Remove extraneous defaults
2025-06-13 16:45:00 -07:00
taxi_gmii_phy_if.f
Reorganize repository
2025-05-18 12:25:59 -07:00
taxi_gmii_phy_if.sv
eth: Move link speed detection logic from MAC wrapper to PHY interface
2025-11-13 21:27:03 -08:00
taxi_mac_ctrl_rx.sv
Use logic instead of reg
2025-11-07 02:14:19 -08:00
taxi_mac_ctrl_tx.sv
Use logic instead of reg
2025-11-07 02:14:19 -08:00
taxi_mac_pause_ctrl_rx.sv
Reorganize repository
2025-05-18 12:25:59 -07:00
taxi_mac_pause_ctrl_tx.sv
Reorganize repository
2025-05-18 12:25:59 -07:00
taxi_mii_phy_if.f
Reorganize repository
2025-05-18 12:25:59 -07:00
taxi_mii_phy_if.sv
Use logic instead of reg
2025-11-07 02:14:19 -08:00
taxi_rgmii_phy_if.f
Reorganize repository
2025-05-18 12:25:59 -07:00
taxi_rgmii_phy_if.sv
eth: Move link speed detection logic from MAC wrapper to PHY interface
2025-11-13 21:27:03 -08:00
taxi_xgmii_baser_dec.sv
Clean up always blocks
2025-11-07 01:51:18 -08:00
taxi_xgmii_baser_enc.sv
Clean up always blocks
2025-11-07 01:51:18 -08:00