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494 Commits 1 Branch 0 Tags
729bf794272450d9ff465cda8a5ee7edededd98a
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55 Commits

Author SHA1 Message Date
Alex Forencich
729bf79427 eth: Move link speed detection logic from MAC wrapper to PHY interface 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2025-11-13 21:27:03 -08:00
Alex Forencich
a919552914 eth: Fix widths 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2025-11-13 18:07:13 -08:00
Alex Forencich
5e77efbfe3 eth: Add APB register interface to US/US+ transceiver wrappers 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2025-11-13 14:15:20 -08:00
Alex Forencich
2582f86a11 eth: Move reset synchronizer to top-level of GT wrapper 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2025-11-13 00:02:55 -08:00
Alex Forencich
4e256cfe37 eth: Add support for 7-series GTX transceiver to 10G/25G MAC 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2025-11-09 13:39:14 -08:00
Alex Forencich
2d061a76f2 eth: Add support for 7-series GTH transceiver to 10G/25G MAC 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2025-11-08 00:39:50 -08:00
Alex Forencich
32eed71e89 eth: Clean up MAC wrappers 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2025-11-07 12:26:12 -08:00
Alex Forencich
004246608e Use logic instead of reg 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2025-11-07 02:14:19 -08:00
Alex Forencich
5f814e7da8 Clean up always blocks 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2025-11-07 01:51:18 -08:00
Alex Forencich
434f31887e eth: Use tie and null_src modules 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2025-11-06 09:35:26 -08:00
Alex Forencich
7ec62b6b47 eth: Push CRC computation logic towards input in 64-bit BASE-R RX module 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2025-10-05 19:34:27 -07:00
Alex Forencich
f6bfd0d097 eth: Push CRC computation logic towards input in 64-bit XGMII RX module 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2025-10-05 19:10:30 -07:00
Alex Forencich
ae53b5d286 eth: Push CRC computation logic towards input in 32-bit XGMII RX module 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2025-10-05 19:09:59 -07:00
Alex Forencich
adf10be684 eth: Remove unused rxc regs 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2025-10-05 18:12:50 -07:00
Alex Forencich
08879e80b8 eth: Mask off end of packet when lane swapped 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2025-10-05 18:12:20 -07:00
Alex Forencich
59a3d5f511 eth: Normalize signal and register names in MAC modules 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2025-10-05 18:11:27 -07:00
Alex Forencich
2810b72147 eth: Decoding is don't care with termination in lane 0 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2025-10-04 21:59:20 -07:00
Alex Forencich
caeacadb78 eth: Clean up masking, lane 0 never needs to be masked 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2025-10-04 20:06:58 -07:00
Alex Forencich
93ef0f970b eth: Re-nest if statements for termination character handling in 10G RX logic 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2025-10-04 19:01:47 -07:00
Alex Forencich
e395398666 eth: Rework input encoding in BASE-R RX modules 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2025-10-04 18:43:20 -07:00
Alex Forencich
7e08164e8d eth: Add term_first_cycle_reg to reduce fanin 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2025-10-04 17:01:53 -07:00
Alex Forencich
879b65cc70 eth: Normalize CRC register naming in 10G RX modules 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2025-10-04 15:54:49 -07:00
Alex Forencich
d0d6747f88 eth: Merge lane swapping logic into BASE-R encode logic in 64-bit BASE-R TX module 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2025-10-04 11:47:21 -07:00
Alex Forencich
0e2acbf482 eth: Fix 2D array declarations 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2025-10-04 11:02:30 -07:00
Alex Forencich
04df834708 eth: Optimize frame length enforcement logic in BASE-R MACs 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2025-10-03 15:49:51 -07:00
Alex Forencich
8257fdf09e eth: Remove unused encodings 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2025-10-03 13:47:52 -07:00
Alex Forencich
f4e36bd081 eth: Optimize padding logic in BASE-R MACs 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2025-10-02 23:08:11 -07:00
Alex Forencich
7e629d934f Fix TX enable in AXI stream BASE-R TX module 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2025-10-02 20:44:43 -07:00
Alex Forencich
76d4465081 eth: Convert UltraScale wrapper to use unpacked arrays for channels 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2025-10-02 16:10:37 -07:00
Alex Forencich
5b0cae2aac eth: Add 32-bit support to combined MAC+PCS module 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2025-06-17 21:37:34 -07:00
Alex Forencich
7b1ae24d95 eth: Report framing and bad block errors in 32-bit BASE-R RX module 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2025-06-17 21:34:42 -07:00
Alex Forencich
295dc2dd23 eth: Add 32-bit AXI stream BASE-R RX module and testbench 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2025-06-17 20:15:09 -07:00
Alex Forencich
ebb8bf0bd4 eth: Add 32-bit AXI stream BASE-R TX module and testbench 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2025-06-17 20:14:30 -07:00
Alex Forencich
e8cea4c860 eth: Use for loop to reduce duplication 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2025-06-17 11:50:29 -07:00
Alex Forencich
facdc5fe68 eth: Remove extraneous constants 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2025-06-16 16:01:12 -07:00
Alex Forencich
17e48c5f51 eth: Support 32-bit mode in UltraScale wrapper 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2025-06-15 13:16:58 -07:00
Alex Forencich
6407b4c7f0 eth: Support 32-bit sync gearbox in 10G MAC 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2025-06-15 13:11:26 -07:00
Alex Forencich
ab09ceb891 eth: Support 32 bit mode in BASE-R PHY 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2025-06-15 13:00:14 -07:00
Alex Forencich
70c0e3d52a eth: Fix RX BER monitor when gearbox is enabled 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2025-06-15 12:54:01 -07:00
Alex Forencich
2e1619a045 eth: Connect and tie off txsequence 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2025-06-15 01:20:23 -07:00
Alex Forencich
cc8ec558bf eth: PHY parameter clean-up, support 32-bit mode in PHY interface modules 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2025-06-14 22:54:09 -07:00
Alex Forencich
e993a6cfbf eth: Cleanup 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2025-06-13 19:38:06 -07:00
Alex Forencich
65eef8b5e8 eth: Parameter cleanup 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2025-06-13 19:28:21 -07:00
Alex Forencich
f9041cd9d2 eth: Fix multidriven net 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2025-06-13 16:51:07 -07:00
Alex Forencich
3349561810 eth: Remove extraneous defaults 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2025-06-13 16:45:00 -07:00
Alex Forencich
741615f203 eth: Fix parameter name 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2025-06-13 16:40:32 -07:00
Alex Forencich
e846e7f0cd eth: Add gearbox support to 64-bit 10G MAC 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2025-06-13 16:39:55 -07:00
Alex Forencich
d4acf48e0a eth: Fix gearbox interface in 10G PHY 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2025-06-13 16:34:44 -07:00
Alex Forencich
0fd4000f69 eth: Support both split and combined MAC/PCS in UltraScale wrapper 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2025-06-13 14:31:14 -07:00
Alex Forencich
4e66dd0f98 eth: Rename gearbox start signals to sync 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2025-06-12 15:45:07 -07:00