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77 lines
2.2 KiB
Systemverilog
77 lines
2.2 KiB
Systemverilog
// SPDX-License-Identifier: CERN-OHL-S-2.0
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/*
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Copyright (c) 2014-2025 FPGA Ninja, LLC
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Authors:
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- Alex Forencich
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*/
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`resetall
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`timescale 1ns / 1ps
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`default_nettype none
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/*
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* Priority encoder module
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*/
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module taxi_penc #
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(
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parameter WIDTH = 4,
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// LSB priority selection
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parameter logic LSB_HIGH_PRIO = 1'b0
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)
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(
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input wire logic [WIDTH-1:0] input_mask,
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output wire logic output_valid,
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output wire logic [$clog2(WIDTH)-1:0] output_index,
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output wire logic [WIDTH-1:0] output_mask
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);
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// hopefully a temporary workaround
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// verilator lint_off UNOPTFLAT
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localparam CL_WIDTH = $clog2(WIDTH);
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localparam LEVELS = WIDTH > 2 ? CL_WIDTH : 1;
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localparam W = 2**LEVELS;
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// pad input to even power of two
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wire [W-1:0] mask = {{W-WIDTH{1'b0}}, input_mask};
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wire [W/2-1:0] stage_valid[LEVELS];
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wire [W/2-1:0] stage_enc[LEVELS];
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// process input bits; generate valid bit and encoded bit for each pair
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for (genvar n = 0; n < W/2; n = n + 1) begin : loop_in
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assign stage_valid[0][n] = |mask[n*2+1:n*2];
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if (LSB_HIGH_PRIO) begin
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// bit 0 is highest priority
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assign stage_enc[0][n] = !mask[n*2+0];
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end else begin
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// bit 0 is lowest priority
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assign stage_enc[0][n] = mask[n*2+1];
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end
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end
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// compress down to single valid bit and encoded bus
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for (genvar l = 1; l < LEVELS; l = l + 1) begin : loop_levels
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for (genvar n = 0; n < W/(2*2**l); n = n + 1) begin : loop_compress
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assign stage_valid[l][n] = |stage_valid[l-1][n*2+1:n*2];
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if (LSB_HIGH_PRIO) begin
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// bit 0 is highest priority
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assign stage_enc[l][(n+1)*(l+1)-1:n*(l+1)] = stage_valid[l-1][n*2+0] ? {1'b0, stage_enc[l-1][(n*2+1)*l-1:(n*2+0)*l]} : {1'b1, stage_enc[l-1][(n*2+2)*l-1:(n*2+1)*l]};
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end else begin
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// bit 0 is lowest priority
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assign stage_enc[l][(n+1)*(l+1)-1:n*(l+1)] = stage_valid[l-1][n*2+1] ? {1'b1, stage_enc[l-1][(n*2+2)*l-1:(n*2+1)*l]} : {1'b0, stage_enc[l-1][(n*2+1)*l-1:(n*2+0)*l]};
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end
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end
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end
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assign output_valid = stage_valid[LEVELS-1][0];
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assign output_index = CL_WIDTH'(stage_enc[LEVELS-1]);
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assign output_mask = WIDTH'(output_valid) << output_index;
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endmodule
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`resetall
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