Alex Forencich 94dba88560 eth: Add RGMII Ethernet MAC with FIFOs module and testbench ...

Signed-off-by: Alex Forencich <alex@alexforencich.com>

2025-02-16 22:17:42 -08:00

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taxi_axis_baser_rx_64

eth: Enable tuser signals

2025-02-07 22:23:03 -08:00

taxi_axis_baser_tx_64

eth: Invert TX completion output control

2025-02-07 23:24:28 -08:00

taxi_axis_gmii_rx

eth: Enable tuser signals

2025-02-07 22:23:03 -08:00

taxi_axis_gmii_tx

eth: Invert TX completion output control

2025-02-07 23:24:28 -08:00

taxi_axis_xgmii_rx_32

eth: Clean up testbench parameters

2025-02-11 22:35:18 -08:00

taxi_axis_xgmii_rx_64

eth: Clean up testbench parameters

2025-02-11 22:35:18 -08:00

taxi_axis_xgmii_tx_32

eth: Clean up testbench parameters

2025-02-11 22:35:18 -08:00

taxi_axis_xgmii_tx_64

eth: Clean up testbench parameters

2025-02-11 22:35:18 -08:00

taxi_eth_mac_1g

eth: Remove unnecessary PTP_TS_FMT_TOD parameter in 1G MAC module

2025-02-16 18:06:41 -08:00

taxi_eth_mac_1g_fifo

eth: Use correct clock for TX completions in MAC + FIFO testbenches

2025-02-16 18:59:18 -08:00

taxi_eth_mac_1g_gmii

eth: Add GMII Ethernet MAC module and testbench

2025-02-16 21:37:12 -08:00

taxi_eth_mac_1g_gmii_fifo

eth: Add GMII Ethernet MAC with FIFOs module and testbench

2025-02-16 22:17:22 -08:00

taxi_eth_mac_1g_rgmii

eth: Add RGMII Ethernet MAC module and testbench

2025-02-16 22:05:59 -08:00

taxi_eth_mac_1g_rgmii_fifo

eth: Add RGMII Ethernet MAC with FIFOs module and testbench

2025-02-16 22:17:42 -08:00

taxi_eth_mac_10g

eth: Clean up testbench parameters

2025-02-11 22:35:18 -08:00

taxi_eth_mac_10g_fifo

eth: Use correct clock for TX completions in MAC + FIFO testbenches

2025-02-16 18:59:18 -08:00

taxi_eth_mac_mii

eth: Add MII Ethernet MAC module and testbench

2025-02-16 20:46:31 -08:00

taxi_eth_mac_mii_fifo

eth: Add MII Ethernet MAC with FIFOs module and testbench

2025-02-16 22:16:54 -08:00

taxi_eth_mac_phy_10g

eth: Clean up testbench parameters

2025-02-11 22:35:18 -08:00

taxi_eth_mac_phy_10g_fifo

eth: Use correct clock for TX completions in MAC + FIFO testbenches

2025-02-16 18:59:18 -08:00

taxi_eth_phy_10g

eth: Add 10G PHY module and testbench

2025-02-04 17:10:21 -08:00

taxi_mac_ctrl_rx

eth: Add MAC control modules

2025-02-08 19:59:11 -08:00

taxi_mac_ctrl_tx

eth: Add MAC control modules

2025-02-08 19:59:11 -08:00

taxi_mac_pause_ctrl_rx

eth: Add MAC pause control modules

2025-02-05 21:11:14 -08:00

taxi_mac_pause_ctrl_tx

eth: Add MAC pause control modules

2025-02-05 21:11:14 -08:00

taxi_xgmii_baser_dec_64

eth: Add XGMII/BASE-R encode/decode modules and testbenches

2025-02-04 16:14:32 -08:00

taxi_xgmii_baser_enc_64

eth: Add XGMII/BASE-R encode/decode modules and testbenches

2025-02-04 16:14:32 -08:00

baser.py

eth: Add XGMII/BASE-R encode/decode modules and testbenches

2025-02-04 16:14:32 -08:00