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33 lines
937 B
Markdown
33 lines
937 B
Markdown
# Taxi Example Design for fb2CG@KU15P
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## Introduction
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This example design targets the Silicom fb2CG@KU15P FPGA board.
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The design places looped-back MACs on the QSFP28 ports.
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* QSFP28
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* Looped-back 10GBASE-R or 25GBASE-R MACs via GTY transceivers
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## Board details
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* FPGA: xcku15p-ffve1760-2-e
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* 25GBASE-R PHY: Soft PCS with GTY transceivers
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## Licensing
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* Toolchain
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* Vivado Enterprise (requires license)
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* IP
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* No licensed vendor IP or 3rd party IP
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## How to build
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Run `make` in the appropriate `fpga*` subdirectory to build the bitstream. Ensure that the Xilinx Vivado toolchain components are in PATH.
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## How to test
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Run `make program` to program the board with Vivado.
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To test the looped-back MAC, it is recommended to use a network tester like the Viavi T-BERD 5800 that supports basic layer 2 tests with a loopback. Do not connect the looped-back MAC to a network as the reflected packets may cause problems.
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