Move everything around

2026-05-09 16:00:25 -07:00
parent 089df744aa
commit 042d7724ff
28 changed files with 15 additions and 402 deletions
--- a/sim/embedded_wrapper/asm_source/Makefile
+++ b/sim/embedded_wrapper/asm_source/Makefile
--- a/sim/embedded_wrapper/asm_source/jsr_test
+++ b/sim/embedded_wrapper/asm_source/jsr_test
--- a/sim/embedded_wrapper/asm_source/jsr_test.s
+++ b/sim/embedded_wrapper/asm_source/jsr_test.s
--- a/sim/embedded_wrapper/asm_source/lda_test
+++ b/sim/embedded_wrapper/asm_source/lda_test
--- a/sim/embedded_wrapper/asm_source/lda_test.s
+++ b/sim/embedded_wrapper/asm_source/lda_test.s
--- a/sim/embedded_wrapper/asm_source/memory.cfg
+++ b/sim/embedded_wrapper/asm_source/memory.cfg
--- a/sim/embedded_wrapper/asm_source/vectors.s
+++ b/sim/embedded_wrapper/asm_source/vectors.s
--- a/sim/embedded_wrapper/verilog6502_32bit.yaml
+++ b/sim/embedded_wrapper/verilog6502_32bit.yaml
@@ -3,7 +3,7 @@ tests:
    toplevel: "cpu_65c02"
    modules:
      - "verilog6502_32bit_test"
-    sources: "sources.list"
+    sources: "../sources.list"
    waves: True
    defines:
      SIM: "hi"
--- a/sim/embedded_wrapper/verilog6502_32bit_asm.yaml
+++ b/sim/embedded_wrapper/verilog6502_32bit_asm.yaml
@@ -3,7 +3,7 @@ tests:
    toplevel: "cpu_65c02"
    modules:
      - "verilog6502_32bit_asm_test"
-    sources: "sources.list"
+    sources: "../sources.list"
    waves: True
    defines:
      SIM: "hi"
--- a/sim/embedded_wrapper/verilog6502_32bit_asm_test.py
+++ b/sim/embedded_wrapper/verilog6502_32bit_asm_test.py
--- a/sim/embedded_wrapper/verilog6502_32bit_test.py
+++ b/sim/embedded_wrapper/verilog6502_32bit_test.py
--- a/sim/embedded_wrapper/verilog6502_wrapper.yaml
+++ b/sim/embedded_wrapper/verilog6502_wrapper.yaml
@@ -3,7 +3,7 @@ tests:
    toplevel: "verilog6502_wrapper_tb"
    modules:
      - "verilog6502_wrapper_test"
-    sources: "sources.list"
+    sources: "../sources.list"
    waves: True
    defines:
      SIM: "hi"
--- a/sim/embedded_wrapper/verilog6502_wrapper_tb.sv
+++ b/sim/embedded_wrapper/verilog6502_wrapper_tb.sv
@@ -14,7 +14,7 @@ logic i_irq_ext;
 logic i_nmi_ext;


-verilog6502_wrapper u_dut(
+verilog6502_embedded_wrapper u_dut(
    .clk(clk),
    .rst(rst),
    .s_apb(s_apb),
--- a/sim/embedded_wrapper/verilog6502_wrapper_test.py
+++ b/sim/embedded_wrapper/verilog6502_wrapper_test.py
--- a/sim/sources.list
+++ b/sim/sources.list
@@ -1,5 +1,5 @@
 verilator.vlt
-verilog6502_wrapper_tb.sv
+embedded_wrapper/verilog6502_wrapper_tb.sv

 ../src/sources.list