Move everything around
This commit is contained in:
BIN
sim/embedded_wrapper/asm_source/jsr_test
Normal file
BIN
sim/embedded_wrapper/asm_source/jsr_test
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Binary file not shown.
BIN
sim/embedded_wrapper/asm_source/lda_test
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BIN
sim/embedded_wrapper/asm_source/lda_test
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@@ -3,7 +3,7 @@ tests:
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toplevel: "cpu_65c02"
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toplevel: "cpu_65c02"
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modules:
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modules:
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- "verilog6502_32bit_test"
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- "verilog6502_32bit_test"
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sources: "sources.list"
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sources: "../sources.list"
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waves: True
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waves: True
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defines:
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defines:
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SIM: "hi"
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SIM: "hi"
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@@ -3,7 +3,7 @@ tests:
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toplevel: "cpu_65c02"
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toplevel: "cpu_65c02"
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modules:
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modules:
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- "verilog6502_32bit_asm_test"
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- "verilog6502_32bit_asm_test"
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sources: "sources.list"
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sources: "../sources.list"
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waves: True
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waves: True
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defines:
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defines:
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SIM: "hi"
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SIM: "hi"
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@@ -3,7 +3,7 @@ tests:
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toplevel: "verilog6502_wrapper_tb"
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toplevel: "verilog6502_wrapper_tb"
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modules:
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modules:
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- "verilog6502_wrapper_test"
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- "verilog6502_wrapper_test"
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sources: "sources.list"
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sources: "../sources.list"
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waves: True
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waves: True
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defines:
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defines:
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SIM: "hi"
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SIM: "hi"
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@@ -14,7 +14,7 @@ logic i_irq_ext;
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logic i_nmi_ext;
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logic i_nmi_ext;
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verilog6502_wrapper u_dut(
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verilog6502_embedded_wrapper u_dut(
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.clk(clk),
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.clk(clk),
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.rst(rst),
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.rst(rst),
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.s_apb(s_apb),
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.s_apb(s_apb),
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@@ -1,5 +1,5 @@
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verilator.vlt
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verilator.vlt
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verilog6502_wrapper_tb.sv
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embedded_wrapper/verilog6502_wrapper_tb.sv
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../src/sources.list
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../src/sources.list
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@@ -7,7 +7,7 @@
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// 0x00010000-0xFFFFEFFF External AXI
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// 0x00010000-0xFFFFEFFF External AXI
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// 0xFFFFF000-0xFFFFFFFF Processor IO
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// 0xFFFFF000-0xFFFFFFFF Processor IO
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module verilog6502_wrapper(
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module verilog6502_embedded_wrapper(
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input clk,
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input clk,
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input rst,
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input rst,
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387
src/fpga6502.sv
387
src/fpga6502.sv
@@ -1,387 +0,0 @@
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module fpga6502 (
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output jtagCtrl_tdi,
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input jtagCtrl_tdo,
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output jtagCtrl_enable,
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output jtagCtrl_capture,
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output jtagCtrl_shift,
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output jtagCtrl_update,
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output jtagCtrl_reset,
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input ut_jtagCtrl_tdi,
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output ut_jtagCtrl_tdo,
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input ut_jtagCtrl_enable,
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input ut_jtagCtrl_capture,
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input ut_jtagCtrl_shift,
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input ut_jtagCtrl_update,
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input ut_jtagCtrl_reset,
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input io_cfuClk,
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input io_cfuReset,
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input cpu0_customInstruction_cmd_valid,
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output cpu0_customInstruction_cmd_ready,
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input [9:0] cpu0_customInstruction_function_id,
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input [31:0] cpu0_customInstruction_inputs_0,
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input [31:0] cpu0_customInstruction_inputs_1,
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output cpu0_customInstruction_rsp_valid,
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input cpu0_customInstruction_rsp_ready,
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output [31:0] cpu0_customInstruction_outputs_0,
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input cpu1_customInstruction_cmd_valid,
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output cpu1_customInstruction_cmd_ready,
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input [9:0] cpu1_customInstruction_function_id,
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input [31:0] cpu1_customInstruction_inputs_0,
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input [31:0] cpu1_customInstruction_inputs_1,
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output cpu1_customInstruction_rsp_valid,
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input cpu1_customInstruction_rsp_ready,
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output [31:0] cpu1_customInstruction_outputs_0,
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input cpu2_customInstruction_cmd_valid,
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output cpu2_customInstruction_cmd_ready,
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input [9:0] cpu2_customInstruction_function_id,
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input [31:0] cpu2_customInstruction_inputs_0,
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input [31:0] cpu2_customInstruction_inputs_1,
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output cpu2_customInstruction_rsp_valid,
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input cpu2_customInstruction_rsp_ready,
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output [31:0] cpu2_customInstruction_outputs_0,
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input cpu3_customInstruction_cmd_valid,
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output cpu3_customInstruction_cmd_ready,
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input [9:0] cpu3_customInstruction_function_id,
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input [31:0] cpu3_customInstruction_inputs_0,
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input [31:0] cpu3_customInstruction_inputs_1,
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output cpu3_customInstruction_rsp_valid,
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input cpu3_customInstruction_rsp_ready,
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output [31:0] cpu3_customInstruction_outputs_0,
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output io_ddrMasters_0_aw_valid,
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input io_ddrMasters_0_aw_ready,
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output [31:0] io_ddrMasters_0_aw_payload_addr,
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output [3:0] io_ddrMasters_0_aw_payload_id,
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output [3:0] io_ddrMasters_0_aw_payload_region,
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output [7:0] io_ddrMasters_0_aw_payload_len,
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output [2:0] io_ddrMasters_0_aw_payload_size,
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output [1:0] io_ddrMasters_0_aw_payload_burst,
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output io_ddrMasters_0_aw_payload_lock,
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output [3:0] io_ddrMasters_0_aw_payload_cache,
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output [3:0] io_ddrMasters_0_aw_payload_qos,
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output [2:0] io_ddrMasters_0_aw_payload_prot,
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output io_ddrMasters_0_aw_payload_allStrb,
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output io_ddrMasters_0_w_valid,
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input io_ddrMasters_0_w_ready,
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output [127:0] io_ddrMasters_0_w_payload_data,
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output [15:0] io_ddrMasters_0_w_payload_strb,
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output io_ddrMasters_0_w_payload_last,
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input io_ddrMasters_0_b_valid,
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output io_ddrMasters_0_b_ready,
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input [3:0] io_ddrMasters_0_b_payload_id,
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input [1:0] io_ddrMasters_0_b_payload_resp,
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output io_ddrMasters_0_ar_valid,
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input io_ddrMasters_0_ar_ready,
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output [31:0] io_ddrMasters_0_ar_payload_addr,
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output [3:0] io_ddrMasters_0_ar_payload_id,
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output [3:0] io_ddrMasters_0_ar_payload_region,
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output [7:0] io_ddrMasters_0_ar_payload_len,
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output [2:0] io_ddrMasters_0_ar_payload_size,
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output [1:0] io_ddrMasters_0_ar_payload_burst,
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output io_ddrMasters_0_ar_payload_lock,
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output [3:0] io_ddrMasters_0_ar_payload_cache,
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output [3:0] io_ddrMasters_0_ar_payload_qos,
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output [2:0] io_ddrMasters_0_ar_payload_prot,
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input io_ddrMasters_0_r_valid,
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output io_ddrMasters_0_r_ready,
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input [127:0] io_ddrMasters_0_r_payload_data,
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input [3:0] io_ddrMasters_0_r_payload_id,
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input [1:0] io_ddrMasters_0_r_payload_resp,
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input io_ddrMasters_0_r_payload_last,
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input io_ddrMasters_0_clk,
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input io_ddrMasters_0_reset,
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output io_ddrMasters_memCheck_pass,
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output userInterruptA,
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output userInterruptB,
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output userInterruptC,
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output userInterruptD,
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output userInterruptE,
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output userInterruptF,
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output userInterruptH,
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output userInterruptG,
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output userInterruptI,
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input [3:0] system_gpio_0_io_read,
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output [3:0] system_gpio_0_io_write,
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output [3:0] system_gpio_0_io_writeEnable,
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output system_uart_0_io_txd,
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input system_uart_0_io_rxd,
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output system_spi_0_io_sclk_write,
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output system_spi_0_io_data_0_writeEnable,
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input system_spi_0_io_data_0_read,
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output system_spi_0_io_data_0_write,
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output system_spi_0_io_data_1_writeEnable,
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input system_spi_0_io_data_1_read,
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output system_spi_0_io_data_1_write,
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output system_spi_0_io_data_2_writeEnable,
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input system_spi_0_io_data_2_read,
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output system_spi_0_io_data_2_write,
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output system_spi_0_io_data_3_writeEnable,
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input system_spi_0_io_data_3_read,
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output system_spi_0_io_data_3_write,
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output [3:0] system_spi_0_io_ss,
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output system_i2c_0_io_sda_writeEnable,
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output system_i2c_0_io_sda_write,
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input system_i2c_0_io_sda_read,
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output system_i2c_0_io_scl_writeEnable,
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output system_i2c_0_io_scl_write,
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input system_i2c_0_io_scl_read,
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input [31:0] axiA_awaddr,
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input [7:0] axiA_awlen,
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input [2:0] axiA_awsize,
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input [1:0] axiA_awburst,
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input axiA_awlock,
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input [3:0] axiA_awcache,
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input [2:0] axiA_awprot,
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input [3:0] axiA_awqos,
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input [3:0] axiA_awregion,
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input axiA_awvalid,
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output axiA_awready,
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input [31:0] axiA_wdata,
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input [3:0] axiA_wstrb,
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input axiA_wvalid,
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input axiA_wlast,
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output axiA_wready,
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output [1:0] axiA_bresp,
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output axiA_bvalid,
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input axiA_bready,
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input [31:0] axiA_araddr,
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input [7:0] axiA_arlen,
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input [2:0] axiA_arsize,
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input [1:0] axiA_arburst,
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input axiA_arlock,
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input [3:0] axiA_arcache,
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input [2:0] axiA_arprot,
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input [3:0] axiA_arqos,
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input [3:0] axiA_arregion,
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input axiA_arvalid,
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output axiA_arready,
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output [31:0] axiA_rdata,
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output [1:0] axiA_rresp,
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output axiA_rlast,
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output axiA_rvalid,
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input axiA_rready,
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output axiAInterrupt,
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input cfg_done,
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output cfg_start,
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output cfg_sel,
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output cfg_reset,
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input io_peripheralClk,
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input io_peripheralReset,
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output io_asyncReset,
|
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input io_gpio_sw_n,
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||||||
input pll_peripheral_locked,
|
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||||||
input pll_system_locked,
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input pll_tse_locked,
|
|
||||||
// SDHC
|
|
||||||
input sd_base_clk,
|
|
||||||
output sd_clk_hi,
|
|
||||||
output sd_clk_lo,
|
|
||||||
input sd_cmd_i,
|
|
||||||
output sd_cmd_o,
|
|
||||||
output sd_cmd_oe,
|
|
||||||
input [3:0] sd_dat_i,
|
|
||||||
output [3:0] sd_dat_o,
|
|
||||||
output [3:0] sd_dat_oe,
|
|
||||||
input sd_cd_n,
|
|
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input sd_wp,
|
|
||||||
// TSEMAC
|
|
||||||
input io_tseClk,
|
|
||||||
// MAC
|
|
||||||
output [3:0] rgmii_txd_HI,
|
|
||||||
output [3:0] rgmii_txd_LO,
|
|
||||||
output rgmii_tx_ctl_HI,
|
|
||||||
output rgmii_tx_ctl_LO,
|
|
||||||
output rgmii_txc_HI,
|
|
||||||
output rgmii_txc_LO,
|
|
||||||
input [3:0] rgmii_rxd_HI,
|
|
||||||
input [3:0] rgmii_rxd_LO,
|
|
||||||
input rgmii_rx_ctl_HI,
|
|
||||||
input rgmii_rx_ctl_LO,
|
|
||||||
input mux_clk,
|
|
||||||
output [1:0] mux_clk_sw,
|
|
||||||
// PHY
|
|
||||||
output phy_rst,
|
|
||||||
input phy_mdi,
|
|
||||||
output phy_mdo,
|
|
||||||
output phy_mdo_en,
|
|
||||||
output phy_mdc,
|
|
||||||
input rgmii_rxc,
|
|
||||||
input rgmii_rxc_slow
|
|
||||||
);
|
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
top_soc u_top_soc (
|
|
||||||
.jtagCtrl_tdi (jtagCtrl_tdi),
|
|
||||||
.jtagCtrl_tdo (jtagCtrl_tdo),
|
|
||||||
.jtagCtrl_enable (jtagCtrl_enable),
|
|
||||||
.jtagCtrl_capture (jtagCtrl_capture),
|
|
||||||
.jtagCtrl_shift (jtagCtrl_shift),
|
|
||||||
.jtagCtrl_update (jtagCtrl_update),
|
|
||||||
.jtagCtrl_reset (jtagCtrl_reset),
|
|
||||||
.ut_jtagCtrl_tdi (ut_jtagCtrl_tdi),
|
|
||||||
.ut_jtagCtrl_tdo (ut_jtagCtrl_tdo),
|
|
||||||
.ut_jtagCtrl_enable (ut_jtagCtrl_enable),
|
|
||||||
.ut_jtagCtrl_capture (ut_jtagCtrl_capture),
|
|
||||||
.ut_jtagCtrl_shift (ut_jtagCtrl_shift),
|
|
||||||
.ut_jtagCtrl_update (ut_jtagCtrl_update),
|
|
||||||
.ut_jtagCtrl_reset (ut_jtagCtrl_reset),
|
|
||||||
.io_cfuClk (io_cfuClk),
|
|
||||||
.io_cfuReset (io_cfuReset),
|
|
||||||
.io_ddrMasters_0_aw_valid (io_ddrMasters_0_aw_valid),
|
|
||||||
.io_ddrMasters_0_aw_ready (io_ddrMasters_0_aw_ready),
|
|
||||||
.io_ddrMasters_0_aw_payload_addr (io_ddrMasters_0_aw_payload_addr),
|
|
||||||
.io_ddrMasters_0_aw_payload_id (io_ddrMasters_0_aw_payload_id),
|
|
||||||
.io_ddrMasters_0_aw_payload_region (io_ddrMasters_0_aw_payload_region),
|
|
||||||
.io_ddrMasters_0_aw_payload_len (io_ddrMasters_0_aw_payload_len),
|
|
||||||
.io_ddrMasters_0_aw_payload_size (io_ddrMasters_0_aw_payload_size),
|
|
||||||
.io_ddrMasters_0_aw_payload_burst (io_ddrMasters_0_aw_payload_burst),
|
|
||||||
.io_ddrMasters_0_aw_payload_lock (io_ddrMasters_0_aw_payload_lock),
|
|
||||||
.io_ddrMasters_0_aw_payload_cache (io_ddrMasters_0_aw_payload_cache),
|
|
||||||
.io_ddrMasters_0_aw_payload_qos (io_ddrMasters_0_aw_payload_qos),
|
|
||||||
.io_ddrMasters_0_aw_payload_prot (io_ddrMasters_0_aw_payload_prot),
|
|
||||||
.io_ddrMasters_0_aw_payload_allStrb (io_ddrMasters_0_aw_payload_allStrb),
|
|
||||||
.io_ddrMasters_0_w_valid (io_ddrMasters_0_w_valid),
|
|
||||||
.io_ddrMasters_0_w_ready (io_ddrMasters_0_w_ready),
|
|
||||||
.io_ddrMasters_0_w_payload_data (io_ddrMasters_0_w_payload_data),
|
|
||||||
.io_ddrMasters_0_w_payload_strb (io_ddrMasters_0_w_payload_strb),
|
|
||||||
.io_ddrMasters_0_w_payload_last (io_ddrMasters_0_w_payload_last),
|
|
||||||
.io_ddrMasters_0_b_valid (io_ddrMasters_0_b_valid),
|
|
||||||
.io_ddrMasters_0_b_ready (io_ddrMasters_0_b_ready),
|
|
||||||
.io_ddrMasters_0_b_payload_id (io_ddrMasters_0_b_payload_id),
|
|
||||||
.io_ddrMasters_0_b_payload_resp (io_ddrMasters_0_b_payload_resp),
|
|
||||||
.io_ddrMasters_0_ar_valid (io_ddrMasters_0_ar_valid),
|
|
||||||
.io_ddrMasters_0_ar_ready (io_ddrMasters_0_ar_ready),
|
|
||||||
.io_ddrMasters_0_ar_payload_addr (io_ddrMasters_0_ar_payload_addr),
|
|
||||||
.io_ddrMasters_0_ar_payload_id (io_ddrMasters_0_ar_payload_id),
|
|
||||||
.io_ddrMasters_0_ar_payload_region (io_ddrMasters_0_ar_payload_region),
|
|
||||||
.io_ddrMasters_0_ar_payload_len (io_ddrMasters_0_ar_payload_len),
|
|
||||||
.io_ddrMasters_0_ar_payload_size (io_ddrMasters_0_ar_payload_size),
|
|
||||||
.io_ddrMasters_0_ar_payload_burst (io_ddrMasters_0_ar_payload_burst),
|
|
||||||
.io_ddrMasters_0_ar_payload_lock (io_ddrMasters_0_ar_payload_lock),
|
|
||||||
.io_ddrMasters_0_ar_payload_cache (io_ddrMasters_0_ar_payload_cache),
|
|
||||||
.io_ddrMasters_0_ar_payload_qos (io_ddrMasters_0_ar_payload_qos),
|
|
||||||
.io_ddrMasters_0_ar_payload_prot (io_ddrMasters_0_ar_payload_prot),
|
|
||||||
.io_ddrMasters_0_r_valid (io_ddrMasters_0_r_valid),
|
|
||||||
.io_ddrMasters_0_r_ready (io_ddrMasters_0_r_ready),
|
|
||||||
.io_ddrMasters_0_r_payload_data (io_ddrMasters_0_r_payload_data),
|
|
||||||
.io_ddrMasters_0_r_payload_id (io_ddrMasters_0_r_payload_id),
|
|
||||||
.io_ddrMasters_0_r_payload_resp (io_ddrMasters_0_r_payload_resp),
|
|
||||||
.io_ddrMasters_0_r_payload_last (io_ddrMasters_0_r_payload_last),
|
|
||||||
.io_ddrMasters_0_clk (io_ddrMasters_0_clk),
|
|
||||||
.io_ddrMasters_0_reset (io_ddrMasters_0_reset),
|
|
||||||
.io_ddrMasters_memCheck_pass (io_ddrMasters_memCheck_pass),
|
|
||||||
.userInterruptA (userInterruptA),
|
|
||||||
.userInterruptB (userInterruptB),
|
|
||||||
.userInterruptC (userInterruptC),
|
|
||||||
.userInterruptD (userInterruptD),
|
|
||||||
.userInterruptE (userInterruptE),
|
|
||||||
.userInterruptF (userInterruptF),
|
|
||||||
.userInterruptH (userInterruptH),
|
|
||||||
.userInterruptG (userInterruptG),
|
|
||||||
.userInterruptI (userInterruptI),
|
|
||||||
.system_gpio_0_io_read (system_gpio_0_io_read),
|
|
||||||
.system_gpio_0_io_write (system_gpio_0_io_write),
|
|
||||||
.system_gpio_0_io_writeEnable (system_gpio_0_io_writeEnable),
|
|
||||||
.system_uart_0_io_txd (system_uart_0_io_txd),
|
|
||||||
.system_uart_0_io_rxd (system_uart_0_io_rxd),
|
|
||||||
.system_spi_0_io_sclk_write (system_spi_0_io_sclk_write),
|
|
||||||
.system_spi_0_io_data_0_writeEnable (system_spi_0_io_data_0_writeEnable),
|
|
||||||
.system_spi_0_io_data_0_read (system_spi_0_io_data_0_read),
|
|
||||||
.system_spi_0_io_data_0_write (system_spi_0_io_data_0_write),
|
|
||||||
.system_spi_0_io_data_1_writeEnable (system_spi_0_io_data_1_writeEnable),
|
|
||||||
.system_spi_0_io_data_1_read (system_spi_0_io_data_1_read),
|
|
||||||
.system_spi_0_io_data_1_write (system_spi_0_io_data_1_write),
|
|
||||||
.system_spi_0_io_data_2_writeEnable (system_spi_0_io_data_2_writeEnable),
|
|
||||||
.system_spi_0_io_data_2_read (system_spi_0_io_data_2_read),
|
|
||||||
.system_spi_0_io_data_2_write (system_spi_0_io_data_2_write),
|
|
||||||
.system_spi_0_io_data_3_writeEnable (system_spi_0_io_data_3_writeEnable),
|
|
||||||
.system_spi_0_io_data_3_read (system_spi_0_io_data_3_read),
|
|
||||||
.system_spi_0_io_data_3_write (system_spi_0_io_data_3_write),
|
|
||||||
.system_spi_0_io_ss (system_spi_0_io_ss),
|
|
||||||
.system_i2c_0_io_sda_writeEnable (system_i2c_0_io_sda_writeEnable),
|
|
||||||
.system_i2c_0_io_sda_write (system_i2c_0_io_sda_write),
|
|
||||||
.system_i2c_0_io_sda_read (system_i2c_0_io_sda_read),
|
|
||||||
.system_i2c_0_io_scl_writeEnable (system_i2c_0_io_scl_writeEnable),
|
|
||||||
.system_i2c_0_io_scl_write (system_i2c_0_io_scl_write),
|
|
||||||
.system_i2c_0_io_scl_read (system_i2c_0_io_scl_read),
|
|
||||||
.axiA_awaddr (axiA_awaddr),
|
|
||||||
.axiA_awlen (axiA_awlen),
|
|
||||||
.axiA_awsize (axiA_awsize),
|
|
||||||
.axiA_awburst (axiA_awburst),
|
|
||||||
.axiA_awlock (axiA_awlock),
|
|
||||||
.axiA_awcache (axiA_awcache),
|
|
||||||
.axiA_awprot (axiA_awprot),
|
|
||||||
.axiA_awqos (axiA_awqos),
|
|
||||||
.axiA_awregion (axiA_awregion),
|
|
||||||
.axiA_awvalid (axiA_awvalid),
|
|
||||||
.axiA_awready (axiA_awready),
|
|
||||||
.axiA_wdata (axiA_wdata),
|
|
||||||
.axiA_wstrb (axiA_wstrb),
|
|
||||||
.axiA_wvalid (axiA_wvalid),
|
|
||||||
.axiA_wlast (axiA_wlast),
|
|
||||||
.axiA_wready (axiA_wready),
|
|
||||||
.axiA_bresp (axiA_bresp),
|
|
||||||
.axiA_bvalid (axiA_bvalid),
|
|
||||||
.axiA_bready (axiA_bready),
|
|
||||||
.axiA_araddr (axiA_araddr),
|
|
||||||
.axiA_arlen (axiA_arlen),
|
|
||||||
.axiA_arsize (axiA_arsize),
|
|
||||||
.axiA_arburst (axiA_arburst),
|
|
||||||
.axiA_arlock (axiA_arlock),
|
|
||||||
.axiA_arcache (axiA_arcache),
|
|
||||||
.axiA_arprot (axiA_arprot),
|
|
||||||
.axiA_arqos (axiA_arqos),
|
|
||||||
.axiA_arregion (axiA_arregion),
|
|
||||||
.axiA_arvalid (axiA_arvalid),
|
|
||||||
.axiA_arready (axiA_arready),
|
|
||||||
.axiA_rdata (axiA_rdata),
|
|
||||||
.axiA_rresp (axiA_rresp),
|
|
||||||
.axiA_rlast (axiA_rlast),
|
|
||||||
.axiA_rvalid (axiA_rvalid),
|
|
||||||
.axiA_rready (axiA_rready),
|
|
||||||
.axiAInterrupt (axiAInterrupt),
|
|
||||||
.cfg_done (cfg_done),
|
|
||||||
.cfg_start (cfg_start),
|
|
||||||
.cfg_sel (cfg_sel),
|
|
||||||
.cfg_reset (cfg_reset),
|
|
||||||
.io_peripheralClk (io_peripheralClk),
|
|
||||||
.io_peripheralReset (io_peripheralReset),
|
|
||||||
.io_asyncReset (io_asyncReset),
|
|
||||||
.io_gpio_sw_n (io_gpio_sw_n),
|
|
||||||
.pll_peripheral_locked (pll_peripheral_locked),
|
|
||||||
.pll_system_locked (pll_system_locked),
|
|
||||||
.pll_tse_locked (pll_tse_locked),
|
|
||||||
.sd_base_clk (sd_base_clk),
|
|
||||||
.sd_clk_hi (sd_clk_hi),
|
|
||||||
.sd_clk_lo (sd_clk_lo),
|
|
||||||
.sd_cmd_i (sd_cmd_i),
|
|
||||||
.sd_cmd_o (sd_cmd_o),
|
|
||||||
.sd_cmd_oe (sd_cmd_oe),
|
|
||||||
.sd_dat_i (sd_dat_i),
|
|
||||||
.sd_dat_o (sd_dat_o),
|
|
||||||
.sd_dat_oe (sd_dat_oe),
|
|
||||||
.sd_cd_n (sd_cd_n),
|
|
||||||
.sd_wp (sd_wp),
|
|
||||||
.io_tseClk (io_tseClk),
|
|
||||||
.rgmii_txd_HI (rgmii_txd_HI),
|
|
||||||
.rgmii_txd_LO (rgmii_txd_LO),
|
|
||||||
.rgmii_tx_ctl_HI (rgmii_tx_ctl_HI),
|
|
||||||
.rgmii_tx_ctl_LO (rgmii_tx_ctl_LO),
|
|
||||||
.rgmii_txc_HI (rgmii_txc_HI),
|
|
||||||
.rgmii_txc_LO (rgmii_txc_LO),
|
|
||||||
.rgmii_rxd_HI (rgmii_rxd_HI),
|
|
||||||
.rgmii_rxd_LO (rgmii_rxd_LO),
|
|
||||||
.rgmii_rx_ctl_HI (rgmii_rx_ctl_HI),
|
|
||||||
.rgmii_rx_ctl_LO (rgmii_rx_ctl_LO),
|
|
||||||
.mux_clk (mux_clk),
|
|
||||||
.mux_clk_sw (mux_clk_sw),
|
|
||||||
.phy_rst (phy_rst),
|
|
||||||
.phy_mdi (phy_mdi),
|
|
||||||
.phy_mdo (phy_mdo),
|
|
||||||
.phy_mdo_en (phy_mdo_en),
|
|
||||||
.phy_mdc (phy_mdc),
|
|
||||||
.rgmii_rxc (rgmii_rxc),
|
|
||||||
.rgmii_rxc_slow (rgmii_rxc_slow)
|
|
||||||
);
|
|
||||||
|
|
||||||
endmodule
|
|
||||||
@@ -1,11 +1,11 @@
|
|||||||
regs/verilog6502_io_regs_pkg.sv
|
embedded_wrapper/regs/verilog6502_io_regs_pkg.sv
|
||||||
regs/verilog6502_io_regs.sv
|
embedded_wrapper/regs/verilog6502_io_regs.sv
|
||||||
verilog6502_addr_decoder.sv
|
embedded_wrapper/verilog6502_addr_decoder.sv
|
||||||
verilog6502_internal_memory.sv
|
embedded_wrapper/verilog6502_internal_memory.sv
|
||||||
verilog6502_apb_adapter.sv
|
embedded_wrapper/verilog6502_apb_adapter.sv
|
||||||
verilog6502_external_memory.sv
|
embedded_wrapper/verilog6502_external_memory.sv
|
||||||
verilog6502_wrapper.sv
|
embedded_wrapper/verilog6502_embedded_wrapper.sv
|
||||||
|
|
||||||
|
|
||||||
ALU.v
|
original_core/ALU.v
|
||||||
cpu_65c02.v
|
original_core/cpu_65c02.v
|
||||||
|
|||||||
Reference in New Issue
Block a user