Get it working more

sim/application_wrapper/cache/application_wrapper_cache_miss_handler_test.py

@@ -122,6 +122,8 @@ async def test_sanity(dut):
     cocotb.start_soon(Clock(dut.i_clk, CLK_PERIOD, unit="ns").start())
     cocotb.start_soon(handle_cache_arrays(dut))
 
+    dut.i_cpu_we.value = 0
+
     dut.i_rst.value = Immediate(1)
     for _ in range(10):
         await RisingEdge(dut.i_clk)
@@ -158,6 +160,8 @@ async def test_clean_eviction(dut):
     cocotb.start_soon(handle_writeback(dut))
     cocotb.start_soon(handle_bus_interface(dut))
 
+    dut.i_cpu_we.value = 0
+
     dut.i_rst.value = Immediate(1)
     for _ in range(10):
         await RisingEdge(dut.i_clk)
@@ -198,6 +202,8 @@ async def test_eviction(dut):
     cocotb.start_soon(handle_writeback(dut))
     cocotb.start_soon(handle_bus_interface(dut))
 
+    dut.i_cpu_we.value = 0
+
     dut.i_rst.value = Immediate(1)
     for _ in range(10):
         await RisingEdge(dut.i_clk)
@@ -238,6 +244,8 @@ async def test_request_ownership(dut):
     cocotb.start_soon(handle_writeback(dut))
     cocotb.start_soon(handle_bus_interface(dut))
 
+    dut.i_cpu_we.value = 0
+
     dut.i_rst.value = Immediate(1)
     for _ in range(10):
         await RisingEdge(dut.i_clk)
@@ -280,6 +288,7 @@ async def test_way_read_thrash(dut):
     cocotb.start_soon(handle_writeback(dut))
     cocotb.start_soon(handle_bus_interface(dut))
 
+    dut.i_cpu_we.value = 0
     dut.i_rst.value = Immediate(1)
     for _ in range(10):
         await RisingEdge(dut.i_clk)
@@ -297,3 +306,97 @@ async def test_way_read_thrash(dut):
             await RisingEdge(dut.i_clk)
 
     await Timer(1, "us")
+
+
+@cocotb.test
+async def test_write_waw(dut):
+    cocotb.start_soon(Clock(dut.i_clk, CLK_PERIOD, unit="ns").start())
+    cocotb.start_soon(handle_cache_arrays(dut))
+    cocotb.start_soon(handle_lru_arrays(dut))
+    cocotb.start_soon(handle_writeback(dut))
+    cocotb.start_soon(handle_bus_interface(dut))
+
+    dut.i_rst.value = Immediate(1)
+    for _ in range(10):
+        await RisingEdge(dut.i_clk)
+    dut.i_rst.value = 0
+
+    await RisingEdge(dut.o_rdy)
+
+    INDEX = 7
+    TAG = 0xabcd
+
+
+    # unused tag
+    dut.i_cpu_tag.value = 0xffff
+    dut.i_rdy.value = 1
+
+    dut.i_cpu_we.value = 1
+    dut.i_cpu_index.value = INDEX
+    dut.i_cpu_offset.value = 1
+    dut.i_cpu_data.value = 0xaa
+    await RisingEdge(dut.i_clk)
+    dut.i_cpu_tag.value = TAG
+
+    while not dut.o_rdy.value:
+        await RisingEdge(dut.i_clk)
+
+    dut.i_cpu_we.value = 1
+    dut.i_cpu_index.value = INDEX
+    dut.i_cpu_offset.value = 2
+    dut.i_cpu_data.value = 0x55
+    await RisingEdge(dut.i_clk)
+    dut.i_cpu_tag.value = TAG
+
+    while not dut.o_rdy.value:
+        await RisingEdge(dut.i_clk)
+
+    dut.i_cpu_we.value = 0
+
+    await Timer(1, "us")
+
+@cocotb.test
+async def test_write_raw(dut):
+    cocotb.start_soon(Clock(dut.i_clk, CLK_PERIOD, unit="ns").start())
+    cocotb.start_soon(handle_cache_arrays(dut))
+    cocotb.start_soon(handle_lru_arrays(dut))
+    cocotb.start_soon(handle_writeback(dut))
+    cocotb.start_soon(handle_bus_interface(dut))
+
+    dut.i_rst.value = Immediate(1)
+    for _ in range(10):
+        await RisingEdge(dut.i_clk)
+    dut.i_rst.value = 0
+
+    await RisingEdge(dut.o_rdy)
+
+    INDEX = 7
+    TAG = 0xabcd
+
+
+    # unused tag
+    dut.i_cpu_tag.value = 0xffff
+    dut.i_rdy.value = 1
+
+    dut.i_cpu_we.value = 1
+    dut.i_cpu_index.value = INDEX
+    dut.i_cpu_offset.value = 1
+    dut.i_cpu_data.value = 0x41
+    await RisingEdge(dut.i_clk)
+    dut.i_cpu_tag.value = TAG
+
+    while not dut.o_rdy.value:
+        await RisingEdge(dut.i_clk)
+
+    dut.i_cpu_we.value = 0
+    dut.i_cpu_index.value = INDEX
+    dut.i_cpu_offset.value = 1
+    await RisingEdge(dut.i_clk)
+    dut.i_cpu_tag.value = TAG
+
+    while not dut.o_rdy.value:
+        await RisingEdge(dut.i_clk)
+
+    dut.i_cpu_we.value = 0
+
+    await Timer(1, "us")