Last commit before I nuke it
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@@ -88,7 +88,7 @@ logic [31:0] cache_miss_count, cache_miss_count_next;
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// reset counter
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logic [INDEX_W-1:0] clear_counter, clear_counter_next;
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enum logic [2:0] {RESET, CLEAR, IDLE, READY, EVICT, READ} prev_state, state, state_next;
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enum logic [2:0] {RESET, CLEAR, IDLE, READY, EVICT, READ, WAIT_CLEAN_UNIQUE} prev_state, state, state_next;
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always_ff @(posedge i_clk) begin
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if (i_rst) begin
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@@ -263,6 +263,23 @@ always_comb begin
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// We are accessing something we just wrote to
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if (latched_we) begin
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// if we are writing to a shared cacheline, we must make it unique first!
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if (current_data.shared) begin
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o_rdy = '0;
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o_cache_cmd = CACHE_CLEAN_UNIQUE;
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o_cache_valid = '1;
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latched_we_next = we_d1;
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latched_data_next = data_d1;
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read_index_next = index_d1;
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read_offset_next = offset_d1;
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state_next = WAIT_CLEAN_UNIQUE;
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end
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write_data = current_data;
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write_data[offset_d1*8 +: 8] = latched_data;
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@@ -284,9 +301,9 @@ always_comb begin
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end else begin
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o_data = current_data[offset_d1*8 +: 8];
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end
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o_rdy = '1;
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end
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o_rdy = '1;
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end
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end
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@@ -303,14 +320,18 @@ always_comb begin
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READ: begin
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o_cache_addr = read_address;
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o_cache_cmd = CACHE_READ;
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if (latched_we) begin
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o_cache_cmd = CACHE_READ_UNIQUE;
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end else begin
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o_cache_cmd = CACHE_READ_SHARED;
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end
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o_cache_valid = '1;
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write_index = read_index;
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write_data = i_cache_data;
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write_meta_tag.tag = read_address[31:INDEX_W+OFFSET_W];
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write_meta_tag.valid = '1;
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write_meta_tag.shared = '0;
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write_meta_tag.shared = ~latched_we; // if we are about to write, then we requested unique
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write_meta_tag.clean = ~latched_we; // if we are about to write, then mark dirty
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data_write_enable = i_cache_rdy;
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@@ -327,6 +348,28 @@ always_comb begin
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end
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end
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WAIT_CLEAN_UNIQUE: begin
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// Write data after making it unique
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if (i_cache_rdy) begin
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write_data[offset_d1*8 +: 8] = latched_data;
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data_write_enable = i_cache_rdy;
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meta_tag_write_enable = i_cache_rdy;
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write_meta_tag.tag = read_address[31:INDEX_W+OFFSET_W];
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write_meta_tag.valid = '1;
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write_meta_tag.shared = '0;
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write_meta_tag.clean = '0;
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write_index = index_d1;
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if (index == write_index) begin
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current_data_next = write_data;
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end
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state_next = READY;
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end
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end
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default: begin
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state_next = READY;
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end
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@@ -361,6 +404,20 @@ end
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already be dirty anyway.
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*/
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/*
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In order for this to be a coherent requester, we need to adjust the protocol slightly
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* CPU Requests data to READ: Send ReadShared request
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* CPU Requests data to WRITE: Send ReadUnique request
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* CPU Writes to data already in cache: CleanUnique
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* Clean cacheline overwritten: Send Evict request
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* Dirty cacheline overwritten: Send WriteBackFull request
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The cache <-> CHI interface is handled by a separate module.
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*/
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endmodule
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@@ -10,10 +10,12 @@ package application_wrapper_cache_pkg;
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logic write_through;
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} page_table_entry_t;
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typedef enum logic [1:0] {
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typedef enum logic [2:0] {
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CACHE_NONE,
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CACHE_READ,
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CACHE_WRITE
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CACHE_READ_SHARED,
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CACHE_READ_UNIQUE,
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CACHE_WRITE,
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CACHE_CLEAN_UNIQUE
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} cache_cmd_e;
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endpackage
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