Add design doc

but I didn't really read it

src/application_wrapper/cache/design_doc.md

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+# Top level requirements
+
+1. Parameterizable cache size (default 64)
+2. Non-parameterizable cacheline width (static 64)
+3. Single cycle access required for use with 6502.
+4. Support MESI cache coherency Protocl (I L L)
+5. Direct mapped cache for low latency
+6. Interface with other coherent components
+
+## Single Cycle Access
+
+For reads, the 6502 presents an address on the address bus and expects data on
+the din bus on the very next cycle. Because the 6502 has so few registers, it
+is critical for memory to have as little latency as possible. For this reason,
+the cache is also direct mapped. Future versions could make this associative,
+but not right now.
+
+## MESI Cache Coherency
+
+Cachelines must support the illinois protocol. Compatibility with CHI is shown
+below:
+
+MODIFIED: when this line is evicted, we write the cacheline to main memory
+
+EXCLUSIVE: We can write to this cacheline without informing the other caches,
+since we are the only ones with this cacheline
+
+SHARED: If we write to this cachline, we must notify the coherenc controller
+so that it can invalidate all other copies of the cacheline
+
+INVALID: If we read from a cacheline, send out a request to the coherency
+controller to see if anybody else has a copy. If they do, then read the
+data from the other cache. Otherwise, read from main memory.
+If we write to this cacheline, send a request to the coherency controller
+to see if anybody else has this cachline. If they have it, then read the
+data from the cache which has it (the first one if multiple do) and invalidate
+the entries in all caches which have it.
+
+## Interface
+
+The interface is based off of the CHI interface, with 4 separate physical
+interfaces: REQ, RSP, DAT, SNP.
+
+The CPU cache will send out commands on the REQ interface. The coherency
+controller will also send out commands on the REQ interface. The response
+channel contains the response to the request, not the data. Data comes on
+the DAT interface. SNP requests are sent on the SNP interface, and responses
+and data come back on the same interfaces. Like CHI, if the response has
+data the then response and data both come back on the DAT interface, if the
+response has no data then it just comes back on the RSP interface.
+
+SNP requests only come from the coherency controller.