Add 32 bit BRK

sim/verilog6502_32bit_test.py

@@ -0,0 +1,20 @@
+import cocotb
+from cocotb.handle import Immediate
+
+from cocotb.clock import Clock
+from cocotb.triggers import Timer, RisingEdge
+
+CLK_PERIOD = 5
+
+@cocotb.test
+async def test_absolute(dut):
+    cocotb.start_soon(Clock(dut.clk, CLK_PERIOD, unit="ns").start())
+
+    dut.RDY.value = Immediate(1)
+
+    dut.reset.value = Immediate(1)
+    for _ in range(10):
+        await RisingEdge(dut.clk)
+    dut.reset.value = 0
+
+    await Timer(1, "us")