Get it to compile at least

src/application_wrapper/cache/application_wrapper_cache_bus_interface.sv

@@ -0,0 +1,68 @@
+import application_wrapper_cache_pkg::*;
+
+module application_wrapper_cache_bus_interface #(
+    parameter DATA_W = 64*8
+) (
+    input  logic                i_clk,
+    input  logic                i_rst,
+
+    input  logic [31:0]         i_cpu_memory_addr,
+    input  logic                i_cpu_memory_valid,
+    input  cache_cmd_e          i_cpu_memory_cmd,
+
+    output logic [DATA_W-1:0]   o_cpu_memory_data,
+    output logic                o_cpu_memory_done,
+    output cache_resp_e         o_cpu_memory_resp,
+
+    output logic [31:0]         o_snoop_addr,
+    output snoop_cmd_e          o_snoop_cmd,
+    output logic                o_snoop_valid,
+
+    input  logic [31:0]         i_writeback_addr,
+    input  logic [DATA_W-1:0]   i_writeback_data,
+    input  logic                i_writeback_valid,
+    output logic                o_writeback_done,
+
+    // CHI Interface
+    output logic                o_txsactive,
+    input  logic                o_rxsactive,
+
+    output logic                o_txlinkactivereq,
+    input  logic                i_txlinkactiveack,
+
+
+    output logic                o_txreqflitpend,
+    output logic                o_txreqflitv,
+    output logic [REQ_W-1:0]    o_txreqflit,
+    input  logic                i_txreqlcrdv,
+
+    output logic                o_txrspflitpend,
+    output logic                o_txrspflitv,
+    output logic [RSP_W-1:0]    o_txrspflit,
+    input  logic                i_txrsplcrdv,
+
+    output logic                o_txdatflitpend,
+    output logic                o_txdatflitv,
+    output logic [DAT_W-1:0]    o_txdatflit,
+    input  logic                i_txdatlcrdv,
+
+    input  logic                i_rxlinkactivereq,
+    output logic                o_rxlinkactiveack,
+
+    input  logic                i_rxrspflitpend,
+    input  logic                i_rxrspflitv,
+    input  logic [RSP_W-1:0]    i_rxrspflit,
+    output logic                i_rxrsplcrdv,
+
+    input  logic                i_rxdatflitpend,
+    input  logic                i_rxdatflitv,
+    input  logic [DAT_W-1:0]    i_rxdatflit,
+    output logic                o_rxdatlcrdv,
+
+    input  logic                i_rxsnpflitpend,
+    input  logic                i_rxsnpflitv,
+    input  logic [SNP_W-1:0]    i_rxsnpflit,
+    output logic                o_rxsnplcrdv
+);
+
+endmodule

src/application_wrapper/cache/application_wrapper_cache_lru.sv

@@ -0,0 +1,27 @@
+module application_wrapper_cache_lru #(
+    // This should be NUM_WAYS - 1
+    parameter LRU_W = 3,
+    parameter NUM_SETS = 64
+) (
+    input  logic [INDEX_W-1:0]  i_read_index,
+    input  logic                i_read_valid,
+    output logic [LRU_W-1:0]   o_read_data,
+
+    input  logic [INDEX_W-1:0]  i_write_index,
+    input  logic                i_write_valid,
+    input  logic [LRU_W-1:0]    i_write_data   
+);
+
+logic [LRU_W-1:0] lru_array [NUM_SETS];
+
+always @(posedge i_clk) begin
+    if (i_write_valid) begin
+        lru_array[i_write_index] = i_write_data;
+    end
+
+    if (i_read_valid) begin
+        o_read_data = lru_array[i_read_index];
+    end
+end
+
+endmodule

src/application_wrapper/cache/application_wrapper_cache_pkg.sv

@@ -32,4 +32,10 @@ package application_wrapper_cache_pkg;
         MESI_MODIFIED
     } mesi_e;
 
+    typedef enum logic [1:0] {
+        CACHE_SNP_NONE,
+        CACHE_SNP_INVALIDATE,
+        CACHE_SNP_SHARE
+    } snoop_cmd_e;
+
 endpackage

src/application_wrapper/cache/application_wrapper_cache_snooping.sv

@@ -0,0 +1,40 @@
+import application_wrapper_cache_pkg::*;
+
+module application_wrapper_cache_snooping #(
+    parameter NUM_WAYS = 4,
+    parameter NUM_SETS = 64,
+    
+    localparam CPU_W = 8,
+    localparam DATA_W = 64*8,
+    localparam OFFSET_W = 6,
+    localparam INDEX_W = $clog2(NUM_SETS),
+    localparam TAG_W = 32 - INDEX_W - OFFSET_W,
+    localparam LRU_W = NUM_WAYS-1,
+
+    localparam META_W = TAG_W + 2
+) (
+    input  logic                i_clk,
+    input  logic                i_rst,
+
+    input  logic [31:0]         i_snoop_addr,
+    input  snoop_cmd_e          i_snoop_cmd,            
+
+    output logic [INDEX_W-1:0]  o_read_index,
+    output logic                o_read_valid,
+
+    input  logic [DATA_W-1:0]   i_read_data [NUM_WAYS],
+    input  logic [META_W-1:0]   i_read_meta [NUM_WAYS],
+
+    output logic [INDEX_W-1:0]  o_write_index,
+    output logic [NUM_WAYS-1:0] o_write_valid,
+
+    output logic [DATA_W-1:0]   o_write_data,
+    output logic [META_W-1:0]   o_write_meta,
+
+    output logic [DATA_W-1:0]   o_writeback_data,
+    output logic [31:0]         o_writeback_addr,
+    output logic                o_writeback_valid,
+    input  logic                i_writeback_done
+);
+
+endmodule

src/application_wrapper/cache/application_wrapper_cache_top.sv

@@ -0,0 +1,347 @@
+import application_wrapper_cache_pkg::*;
+
+module application_wrapper_cache_top #(
+    parameter NUM_WAYS = 4,
+    parameter NUM_SETS = 64,
+
+    localparam DATA_W = 64*8,
+    localparam OFFSET_W = 6,
+    localparam INDEX_W = $clog2(NUM_SETS),
+    localparam TAG_W = 32 - INDEX_W - OFFSET_W,
+    localparam LRU_W = NUM_WAYS-1,
+
+    localparam META_W = TAG_W + 2
+) (
+    input  logic                i_clk,
+    input  logic                i_rst,
+
+    // CPU Interface
+    input  logic [31:0]         i_cpu_addr,
+    input  logic                i_we,
+    input  logic                i_cpu_sync,
+    input  logic [7:0]          i_cpu_data,
+    output logic [7:0]          o_cpu_data,
+    input  logic                i_cpu_rdy,
+    output logic                o_cpu_rdy,
+
+
+    // CHI Interface
+    output logic                o_txsactive,
+    input  logic                o_rxsactive,
+
+    output logic                o_txlinkactivereq,
+    input  logic                i_txlinkactiveack,
+
+
+    output logic                o_txreqflitpend,
+    output logic                o_txreqflitv,
+    output logic [REQ_W-1:0]    o_txreqflit,
+    input  logic                i_txreqlcrdv,
+
+    output logic                o_txrspflitpend,
+    output logic                o_txrspflitv,
+    output logic [RSP_W-1:0]    o_txrspflit,
+    input  logic                i_txrsplcrdv,
+
+    output logic                o_txdatflitpend,
+    output logic                o_txdatflitv,
+    output logic [DAT_W-1:0]    o_txdatflit,
+    input  logic                i_txdatlcrdv,
+
+    input  logic                i_rxlinkactivereq,
+    output logic                o_rxlinkactiveack,
+
+    input  logic                i_rxrspflitpend,
+    input  logic                i_rxrspflitv,
+    input  logic [RSP_W-1:0]    i_rxrspflit,
+    output logic                i_rxrsplcrdv,
+
+    input  logic                i_rxdatflitpend,
+    input  logic                i_rxdatflitv,
+    input  logic [DAT_W-1:0]    i_rxdatflit,
+    output logic                o_rxdatlcrdv,
+
+    input  logic                i_rxsnpflitpend,
+    input  logic                i_rxsnpflitv,
+    input  logic [SNP_W-1:0]    i_rxsnpflit,
+    output logic                o_rxsnplcrdv
+);
+
+
+// ngl idk what the difference is between mmu_rdy and mmu_valid
+logic                           mmu_rdy;
+logic                           mmu_valid;
+
+logic [31:0]                    mmu_phys_address;
+page_table_entry_t              mmu_page_table_entry;
+
+application_wrapper_mmu #(
+    .TLB_COUNT                  (32),
+    .ADDR_WIDTH                 (32),
+    .LOG2_PAGE_SIZE             (12)
+) u_mmu (
+    .i_clk                      (i_clk),
+    .i_rst                      (i_rst),
+
+    .i_cpu_addr                 (i_cpu_addr),
+    .i_rdy                      (i_cpu_rdy | o_cpu_rdy),
+    .o_rdy                      (mmu_rdy),
+
+    .o_phys_address             (mmu_phys_address),
+    .o_table_entry              (mmu_page_table_entry),
+    .o_mmu_valid                (mmu_valid)
+);
+
+logic [TAG_W-1:0]               cpu_tag;
+logic [INDEX_W-1:0]             cpu_index;
+logic [OFFSET_W-1:0]            cpu_offset;
+
+logic                           miss_handler_rdy;
+
+
+logic [INDEX_W-1:0]             cpu_read_index;
+logic                           cpu_read_valid;
+logic [DATA_W-1:0]              cpu_read_data [NUM_WAYS];
+logic [META_W-1:0]              cpu_read_meta [NUM_WAYS];
+
+logic [INDEX_W-1:0]             cpu_write_index;
+logic [NUM_WAYS-1:0]            cpu_write_valid;
+logic [DATA_W-1:0]              cpu_write_data;
+logic [META_W-1:0]              cpu_write_meta;
+
+logic [INDEX_W-1:0]             snoop_read_index;
+logic                           snoop_read_valid;
+logic [DATA_W-1:0]              snoop_read_data [NUM_WAYS];
+logic [META_W-1:0]              snoop_read_meta [NUM_WAYS];
+
+logic [INDEX_W-1:0]             snoop_write_index;
+logic [NUM_WAYS-1:0]            snoop_write_valid;
+logic [DATA_W-1:0]              snoop_write_data;
+logic [META_W-1:0]              snoop_write_meta;
+
+
+// should the snoop unit also modify the LRU?
+// I don't think so...
+logic [INDEX_W-1:0]             cpu_lru_read_index;
+logic                           cpu_lru_read_valid;
+logic [LRU_W-1:0]               cpu_lru_read_data;
+            
+logic [INDEX_W-1:0]             cpu_lru_write_index;
+logic                           cpu_lru_write_valid;
+logic [LRU_W-1:0]               cpu_lru_write_data;
+
+logic [DATA_W-1:0]              cpu_writeback_data;
+logic [31:0]                    cpu_writeback_addr;
+logic                           cpu_writeback_valid;
+logic                           cpu_writeback_done;
+
+logic [DATA_W-1:0]              snoop_writeback_data;
+logic [31:0]                    snoop_writeback_addr;
+logic                           snoop_writeback_valid;
+logic                           snoop_writeback_done;
+
+logic [31:0]                    cpu_memory_addr;
+logic                           cpu_memory_valid;
+cache_cmd_e                     cpu_memory_cmd;
+
+logic [DATA_W-1:0]              cpu_memory_data;
+logic                           cpu_memory_done;
+cache_resp_e                    cpu_memory_resp;
+
+logic [31:0]                    snoop_memory_addr;
+logic                           snoop_memory_valid;
+cache_cmd_e                     snoop_memory_cmd;
+
+logic [DATA_W-1:0]              snoop_memory_data;
+logic                           snoop_memory_done;
+cache_resp_e                    snoop_memory_resp;
+
+// there should be a bypass path here
+
+// separate tag, index, offset from the physical address
+assign cpu_tag = mmu_phys_address[31:INDEX_W+OFFSET_W];
+
+assign cpu_index = i_cpu_addr[INDEX_W+OFFSET_W-1:OFFSET_W];
+assign cpu_offset = i_cpu_addr[OFFSET_W-1:0];
+
+application_wrapper_cache_miss_handler #(
+    .NUM_WAYS                   (NUM_WAYS),
+    .NUM_SETS                   (NUM_SETS)
+) u_miss_handler (
+    .i_clk                      (i_clk),
+    .i_rst                      (i_rst),
+
+    .i_cpu_tag                  (cpu_tag),
+    .i_cpu_index                (cpu_index),
+    .i_cpu_offset               (cpu_offset),
+
+    .i_rdy                      (mmu_rdy),
+    .o_rdy                      (miss_handler_rdy),
+
+    .i_cpu_we                   (i_cpu_we),
+
+    .i_cpu_data                 (i_cpu_data),
+    .o_cpu_data                 (o_cpu_data),
+
+    .o_read_index               (cpu_read_index),
+    .o_read_valid               (cpu_read_valid),
+    .i_read_data                (cpu_read_data),
+    .i_read_meta                (cpu_read_meta),
+
+    .o_write_index              (cpu_write_index),
+    .o_write_valid              (cpu_write_valid),
+    .o_write_data               (cpu_write_data),
+    .o_write_meta               (cpu_write_meta),
+
+    .o_lru_read_index           (cpu_lru_read_index),
+    .o_lru_read_valid           (cpu_lru_read_valid),
+    .i_lru_read_data            (cpu_lru_read_data),
+
+    .o_lru_write_index          (cpu_lru_write_index),
+    .o_lru_write_valid          (cpu_lru_write_valid),
+    .o_lru_write_data           (cpu_lru_write_data),
+
+    .o_writeback_data           (cpu_writeback_data),
+    .o_writeback_addr           (cpu_writeback_addr),
+    .o_writeback_valid          (cpu_writeback_valid),
+    .i_writeback_done           (cpu_writeback_done),
+
+    .o_memory_addr              (cpu_memory_addr),
+    .o_memory_valid             (cpu_memory_valid),
+    .o_memory_cmd               (cpu_memory_cmd),
+
+    .i_memory_data              (cpu_memory_data),
+    .i_memory_done              (cpu_memory_done),
+    .i_memory_resp              (cpu_memory_resp)
+);
+
+application_wrapper_cache_arrays #(
+    .NUM_WAYS                   (NUM_WAYS),
+    .NUM_SETS                   (NUM_SETS)
+) u_cache_arrays (
+    .i_clk                      (i_clk),
+
+    .i_cpu_read_index           (cpu_read_index),
+    .i_cpu_read_valid           (cpu_read_valid),
+
+    .o_cpu_read_data            (cpu_read_data),
+    .o_cpu_read_meta            (cpu_read_meta),
+
+    .i_cpu_write_index          (cpu_write_index),
+    .i_cpu_write_valid          (cpu_write_valid),
+
+    .i_cpu_write_data           (cpu_write_data),
+    .i_cpu_write_meta           (cpu_write_meta),
+
+    .i_snoop_read_index         (snoop_read_index),
+    .i_snoop_read_valid         (snoop_read_valid),
+
+    .o_snoop_read_data          (snoop_read_data),
+    .o_snoop_read_meta          (snoop_read_meta),
+
+    .i_snoop_write_index        (snoop_write_index),
+    .i_snoop_write_valid        (snoop_write_valid),
+
+    .i_snoop_write_data         (snoop_write_data),
+    .i_snoop_write_meta         (snoop_write_meta)
+);
+
+application_wrapper_cache_lru #(
+    .LRU_W                      (LRU_W),
+    .NUM_SETS                   (NUM_SETS)
+) u_lru (
+    .i_read_index               (cpu_lru_read_index),
+    .i_read_valid               (cpu_lru_read_valid),
+    .o_read_data                (cpu_lru_read_data),
+
+    .i_write_index              (cpu_lru_write_index),
+    .i_write_valid              (cpu_lru_write_valid),
+    .i_write_data               (cpu_lru_write_data)
+);
+
+application_wrapper_cache_writeback_buffer #(
+    .DATA_W                     (DATA_W)
+) u_writeback_buffer (
+    .i_clk                      (i_clk),
+    .i_rst                      (i_rst),
+
+    .i_cpu_writeback_data       (cpu_writeback_data),
+    .i_cpu_writeback_addr       (cpu_writeback_addr),
+    .i_cpu_writeback_valid      (cpu_writeback_valid),
+    .o_cpu_writeback_done       (cpu_writeback_done),
+
+    .i_snoop_writeback_data     (snoop_writeback_data),
+    .i_snoop_writeback_addr     (snoop_writeback_addr),
+    .i_snoop_writeback_valid    (snoop_writeback_valid),
+    .o_snoop_writeback_done     (snoop_writeback_done),
+
+    .o_bus_writeback_data       (bus_writeback_data),
+    .o_bus_writeback_addr       (bus_writeback_addr),
+    .o_bus_writeback_valid      (bus_writeback_valid),
+    .i_bus_writeback_done       (bus_writeback_done)
+);
+
+application_wrapper_cache_bus_interface #(
+    .DATA_W                     (DATA_W)
+) u_bus_interface (
+    .i_clk                      (i_clk),
+    .i_rst                      (i_rst),
+
+    .i_cpu_memory_addr          (cpu_memory_addr),
+    .i_cpu_memory_valid         (cpu_memory_valid),
+    .i_cpu_memory_cmd           (cpu_memory_cmd),
+
+    .o_cpu_memory_data          (cpu_memory_data),
+    .o_cpu_memory_done          (cpu_memory_done),
+    .o_cpu_memory_resp          (cpu_memory_resp),
+
+    .o_snoop_addr               (snoop_addr),
+    .o_snoop_cmd                (snoop_cmd),
+    .o_snoop_valid              (snoop_valid),
+
+    .i_writeback_addr           (bus_writeback_addr),
+    .i_writeback_data           (bus_writeback_data),
+    .i_writeback_valid          (bus_writeback_valid),
+    .o_writeback_done           (bus_writeback_done),
+
+    .o_txsactive                (o_txsactive),
+    .o_rxsactive                (o_rxsactive),
+
+    .o_txlinkactivereq          (o_txlinkactivereq),
+    .i_txlinkactiveack          (i_txlinkactiveack),
+
+    .o_txreqflitpend            (o_txreqflitpend),
+    .o_txreqflitv               (o_txreqflitv),
+    .o_txreqflit                (o_txreqflit),
+    .i_txreqlcrdv               (i_txreqlcrdv),
+
+    .o_txrspflitpend            (o_txrspflitpend),
+    .o_txrspflitv               (o_txrspflitv),
+    .o_txrspflit                (o_txrspflit),
+    .i_txrsplcrdv               (i_txrsplcrdv),
+
+    .o_txdatflitpend            (o_txdatflitpend),
+    .o_txdatflitv               (o_txdatflitv),
+    .o_txdatflit                (o_txdatflit),
+    .i_txdatlcrdv               (i_txdatlcrdv),
+
+    .i_rxlinkactivereq          (i_rxlinkactivereq),
+    .o_rxlinkactiveack          (o_rxlinkactiveack),
+
+    .i_rxrspflitpend            (i_rxrspflitpend),
+    .i_rxrspflitv               (i_rxrspflitv),
+    .i_rxrspflit                (i_rxrspflit),
+    .i_rxrsplcrdv               (i_rxrsplcrdv),
+
+    .i_rxdatflitpend            (i_rxdatflitpend),
+    .i_rxdatflitv               (i_rxdatflitv),
+    .i_rxdatflit                (i_rxdatflit),
+    .o_rxdatlcrdv               (o_rxdatlcrdv),
+
+    .i_rxsnpflitpend            (i_rxsnpflitpend),
+    .i_rxsnpflitv               (i_rxsnpflitv),
+    .i_rxsnpflit                (i_rxsnpflit),
+    .o_rxsnplcrdv               (o_rxsnplcrdv)
+);
+
+endmodule

src/application_wrapper/cache/application_wrapper_cache_writeback_buffer.sv

@@ -0,0 +1,23 @@
+module application_wrapper_cache_writeback_buffer #(
+    parameter DATA_W = 64*8
+) (
+    input  logic                i_clk,
+    input  logic                i_rst,
+
+    input  logic [DATA_W-1:0]   i_cpu_writeback_data,
+    input  logic [31:0]         i_cpu_writeback_addr,
+    input  logic                i_cpu_writeback_valid,
+    output logic                o_cpu_writeback_done,
+
+    input  logic [DATA_W-1:0]   i_snoop_writeback_data,
+    input  logic [31:0]         i_snoop_writeback_addr,
+    input  logic                i_snoop_writeback_valid,
+    output logic                o_snoop_writeback_done,
+
+    output logic [DATA_W-1:0]   o_bus_writeback_data,
+    output logic [31:0]         o_bus_writeback_addr,
+    output logic                o_bus_writeback_valid,
+    input  logic                i_bus_writeback_done
+);
+
+endmodule

src/application_wrapper/cache/application_wrapper_mmu.sv

@@ -9,13 +9,27 @@ module application_wrapper_mmu #(
     input  logic                    i_rst,
 
     input  logic [ADDR_WIDTH-1:0]   i_cpu_addr,
-    input                           i_we,
+    input  logic                    i_rdy,
-    input                           i_rdy,
+    output logic                    o_rdy,
-    input                           o_rdy,
 
     output logic [ADDR_WIDTH-1:0]   o_phys_address,
     output page_table_entry_t       o_table_entry,
     output logic                    o_mmu_valid
 );
 
+assign o_rdy = '1;
+
+always @(posedge i_clk) begin
+    o_mmu_valid <= i_rdy;
+    o_phys_address <= i_cpu_addr;
+
+    o_table_entry.cache_disable <= '0;
+    o_table_entry.read_eanble <= '1;
+    o_table_entry.write_enable <= '1;
+    o_table_entry.execute_enable <= '1;
+    o_table_entry.supervisor <= '1;
+    o_table_entry.present <= '1;
+    o_table_entry.write_through <= '0;
+end
+
 endmodule

src/application_wrapper/sources.list

@@ -1,7 +1,11 @@
 cache/application_wrapper_cache_pkg.sv
 cache/application_wrapper_cache_arrays.sv
+cache/application_wrapper_cache_bus_interface.sv
+cache/application_wrapper_cache_lru.sv
 cache/application_wrapper_cache_miss_handler.sv
-cache/application_wrapper_mmu.sv
+cache/application_wrapper_cache_snooping.sv
 cache/application_wrapper_cache_top.sv
+cache/application_wrapper_cache_writeback_buffer.sv
+cache/application_wrapper_mmu.sv
 
 application_wrapper_top.sv