Add cc65 code

sim/asm_source/Makefile

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+
+
+# work in progress
+.SUFFIXES:
+
+
+PROGRAMS=jsr_test lda_test
+
+SRCS=$(wildcard *.s)
+OBJS=$(SRCS:.s=.o)
+
+CA65=$(CC65_BIN)/ca65
+LD65=$(CC65_BIN)/ld65
+
+CA_ARGS=--cpu 65c032
+
+all: $(PROGRAMS)
+
+$(PROGRAMS): $(PROGRAM=$(.TARGET))
+
+%.o: %.s
+	$(CA65) $(CA_ARGS) $^ -o $@ -l $@.lst
+
+$(PROGRAMS): $(OBJS)
+	$(LD65) -o $@ -C memory.cfg vectors.o $@.o
+
+clean:
+	rm -rf $(PROGRAMS) $(OBJS)
+	rm -rf *.o *.lst

sim/asm_source/jsr_test.s

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+.export vec_reset, vec_irq, vec_nmi
+
+.segment "CODE"
+
+vec_nmi:
+vec_reset:
+vec_irq:
+
+
+jsr_test:
+    bra jsr_test

sim/asm_source/lda_test.s

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+.export vec_reset, vec_irq, vec_nmi
+
+.ZEROPAGE
+
+zp0: .res 1
+zp1: .res 4
+zp2: .res 8
+zp3: .res 4
+
+.CODE
+
+data1:  .byte 1
+data2:  .byte 2
+data3:  .byte 3
+data4:  .byte 4
+data5:  .byte 5
+data6:  .res 4 
+        .byte 6
+data7:  .res 2
+        .byte 7
+
+vec_nmi:
+vec_reset:
+vec_irq:
+
+
+prepare_test:
+    lda data1
+    sta zp0
+
+    lda #.LOBYTE(data2)
+    sta zp1
+    lda #.HIBYTE(data2)
+    sta zp1+1
+    lda #.BANKBYTE(data2)
+    sta zp1+2
+    lda #.TOPBYTE(data2)
+    sta zp1+3
+
+    lda #.LOBYTE(data4)
+    sta zp2+4
+    lda #.HIBYTE(data4)
+    sta zp2+5
+    lda #.BANKBYTE(data4)
+    sta zp2+6
+    lda #.TOPBYTE(data4)
+    sta zp2+7
+
+    lda #.LOBYTE(data5-2)
+    sta zp3
+    lda #.HIBYTE(data5-2)
+    sta zp3+1
+    lda #.BANKBYTE(data5-2)
+    sta zp3+2
+    lda #.TOPBYTE(data5-2)
+    sta zp3+3
+
+lda_test:
+    lda zp0         ; data 1
+    lda (zp1)       ; data 2
+    lda data3       ; data 3
+    ldx #$4
+    ldy #$2
+    lda (zp2,x)     ; data 4
+    lda (zp3),y     ; data 5
+    lda data6,x     ; data 6
+    lda data7,y     ; data 7
+    wai

sim/asm_source/memory.cfg

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+MEMORY {
+    ZP: start = $0, size = $100;
+    RAM:  start = $fffff000, size = $1000, file=%O;
+}
+
+SEGMENTS {
+    ZEROPAGE:   load = ZP,  type = zp;
+    CODE:       load = RAM, type = ro;
+    RODATA:     load = RAM, type = ro;
+    DATA:       load = RAM, type = rw;
+    BSS:        load = RAM, type = bss, define = yes;
+    VECTORS:    load = RAM, type = ro, start = $FFFFFFF4;
+}

sim/asm_source/vectors.s

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+.import vec_reset, vec_irq, vec_nmi
+
+.segment "VECTORS": dword
+
+.addr vec_nmi
+.addr vec_reset
+.addr vec_irq