Add jsr and rts

sim/verilog6502_32bit_test.py

@@ -476,6 +476,70 @@ async def test_indirect_indexed(dut):
     await check_instruction_sequence(dut, expected_cpu_outputs)
 
 @cocotb.test
+async def test_jsr(dut):
+    cocotb.start_soon(Clock(dut.clk, CLK_PERIOD, unit="ns").start())
+    cocotb.start_soon(handle_memory(dut))
+
+    write_dword(0xfffffff4, 0x200)
+
+    # @0x200
+    # ldx #$0
+    # txs
+    # jsr $12345678
+    # wai
+    #
+    # @0x1234
+    # rts
+    write_bytes(0x200, [0xa2, 0xff, 0x9a, 0x20, 0x78, 0x56, 0x34, 0x12, 0xcb])
+    write_bytes(0x12345678, [0x60])
+
+    dut.RDY.value = Immediate(1)
+
+    dut.reset.value = Immediate(1)
+    for _ in range(10):
+        await RisingEdge(dut.clk)
+    dut.reset.value = 0
+
+    expected_cpu_outputs = [
+        None,   # ignore reset sequence
+        None,
+        None,
+        None,
+        None,
+        None,
+        None,
+        None,
+        None,
+        (0x00000200, False, None),  # ldx #$00
+        (0x00000201, False, None),  # Immediate
+        (0x00000202, False, None),  # txs
+        (0x00000203, False, None),  # second cycle of txs
+        (0x00000203, False, None),  # jsr $12345678
+        (0x00000204, False, None),  # first byte of address
+        (0x000001ff, True,  0x00),  # 24-31
+        (0x000001fe, True,  0x00),  # 16-23
+        (0x000001fd, True,  0x02),  # 8-15
+        (0x000001fc, True,  0x05),  # 7-0
+        (0x00000205, False, None),  # second byte of address
+        (0x00000206, False, None),  # third byte of address
+        (0x00000207, False, None),  # fourth byte of address
+        (0x00000208, False, None),  # receive last byte of address
+        (0x12345678, False, None),  # rts
+        (0x12345679, False, None),  # rts
+        (0x000001fb, False, None),  # current stack while we add 1 to it
+        (0x000001fc, False, None),  # 7-0
+        (0x000001fd, False, None),  # 15-8
+        (0x000001fe, False, None),  # 23-16
+        (0x000001ff, False, None),  # 31-24
+        (0x1234567c, False, None),  # Updating PC before jump
+        (0x00000208, False, None),  # WAI
+        (0x00000209, False, None),  # second wai
+        (0x0000020a, False, None),  # third wai
+    ]
+
+    await check_instruction_sequence(dut, expected_cpu_outputs)
+
+# @cocotb.test
 async def test_adc(dut):
     cocotb.start_soon(Clock(dut.clk, CLK_PERIOD, unit="ns").start())
     cocotb.start_soon(handle_memory(dut))