Add RTI

sim/verilog6502_32bit_test.py

@@ -539,7 +539,73 @@ async def test_jsr(dut):
 
     await check_instruction_sequence(dut, expected_cpu_outputs)
 
-# @cocotb.test
+@cocotb.test
+async def test_rti(dut):
+    cocotb.start_soon(Clock(dut.clk, CLK_PERIOD, unit="ns").start())
+    cocotb.start_soon(handle_memory(dut))
+
+    write_dword(0xfffffff4, 0x200)
+    write_dword(0xfffffffc, 0x300)
+
+
+    # @0x200
+    # ldx #$ff
+    # txs
+    # brk
+    # wai
+    # @0x300
+    # rti
+
+    write_bytes(0x200, [0xa2, 0xff, 0x9a, 0x00, 0x00, 0xcb]) # BRK is technically a 2 byte instruction
+    write_bytes(0x300, [0x40])
+
+    dut.RDY.value = Immediate(1)
+
+    dut.reset.value = Immediate(1)
+    for _ in range(10):
+        await RisingEdge(dut.clk)
+    dut.reset.value = 0
+
+    expected_cpu_outputs = [
+        None,   # ignore reset sequence
+        None,
+        None,
+        None,
+        None,
+        None,
+        None,
+        None,
+        None,
+        (0x00000200, False, None),  # ldx #$ff
+        (0x00000201, False, None),  # immediate
+        (0x00000202, False, None),  # txs
+        (0x00000203, False, None),  # txs
+        (0x00000203, False, None),  # brk
+        (0x00000204, False, None),  # brk
+        (0x000001ff, True,  0x00),  # brk   31-24
+        (0x000001fe, True,  0x00),  # brk   13-16
+        (0x000001fd, True,  0x02),  # brk   15-08
+        (0x000001fc, True,  0x05),  # brk   07-00
+        (0x000001fb, True,  0xb4),  # brk   flags
+        (0xfffffffc, False, None),  # vector
+        (0xfffffffd, False, None),  # vector
+        (0xfffffffe, False, None),  # vector
+        (0xffffffff, False, None),  # vector 
+        (0x00000300, False, None),  # rti
+        (0x00000301, False, None),  # rti
+        (0x000001fa, False, None),  # rti
+        (0x000001fb, False, None),  # rti
+        (0x000001fc, False, None),  # rti
+        (0x000001fd, False, None),  # rti
+        (0x000001fe, False, None),  # rti
+        (0x000001ff, False, None),  # rti
+        (0x00000205, False, None),  # wai
+    ]
+
+    await check_instruction_sequence(dut, expected_cpu_outputs)
+
+
+@cocotb.test
 async def test_adc(dut):
     cocotb.start_soon(Clock(dut.clk, CLK_PERIOD, unit="ns").start())
     cocotb.start_soon(handle_memory(dut))