Create project

2026-04-18 18:50:18 -07:00
commit db61ca2d74
21 changed files with 1726 additions and 0 deletions
--- a/sim/verilog6502_wrapper.yaml
+++ b/sim/verilog6502_wrapper.yaml
@@ -0,0 +1,9 @@
+tests:
+  - name: "verilog6502_wrapper"
+    toplevel: "verilog6502_wrapper_tb"
+    modules:
+      - "verilog6502_wrapper_test"
+    sources: "sources.list"
+    waves: True
+    defines:
+      SIM: "hi"