Create project

2026-04-18 18:50:18 -07:00
commit db61ca2d74
21 changed files with 1726 additions and 0 deletions
--- a/src/regs/verilog6502_io_regs.rdl
+++ b/src/regs/verilog6502_io_regs.rdl
@@ -0,0 +1,60 @@
+addrmap verilog6502_io_regs {
+    name = "";
+    desc = "";
+
+    reg {
+        name = "Core Control";
+        desc = "";
+
+        field {
+            name = "reset";
+            desc = "";
+            hw   = r;
+            sw   = rw;
+        } reset[0:0] = 0x1;
+    
+    } core_ctrl @ 0x0;
+
+    reg {
+        name = "AXI Base Address";
+        desc = "";
+
+        field {
+            name = "val";
+            desc = "";
+            hw   = r;
+            sw   = rw;
+        } val[31:0] = 0x0;
+        
+    } axi_base_address @ 0x10;
+
+    reg {
+        name = "nmi";
+
+        field {
+            name = "nmi";
+            desc = "";
+            hw   = r;
+            sw   = rw;
+        } nmi[31:16] = 0x200;
+    } nmi @ 0xff8;
+
+    reg {
+        name = "reset_brq";
+        desc = "";
+
+        field {
+            name = "reset";
+            desc = "";
+            hw   = r;
+            sw   = rw;
+        } reset[15:0] = 0x200;
+        
+        field {
+            name = "brq";
+            desc = "";
+            hw   = r;
+            sw   = rw;
+        } brk[31:16] = 0x200;
+    } reset_brq @ 0xffc;
+};