bslathi19/wireguard_fpga
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This commit is contained in:
Byron Lathi
2026-08-13 08:35:49 -07:00
parent 82c05ac4dc
commit 2f2727777b
541 changed files with 184695 additions and 10058 deletions
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11
Ti375C529_devkit/Ti375C529_devkit.peri.xml
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@@ -1,5 +1,5 @@
<?xml version="1.0" encoding="UTF-8"?>
<efxpt:design_db name="Ti375C529_devkit" device_def="Ti375C529" version="2026.1.132" db_version="20261009" last_change_date="Sat Aug 8 20:48:48 2026" xmlns:efxpt="http://www.efinixinc.com/peri_design_db" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xsi:schemaLocation="http://www.efinixinc.com/peri_design_db peri_design_db.xsd ">
<efxpt:design_db name="Ti375C529_devkit" device_def="Ti375C529" version="2025.2.288.2.10" db_version="20252999" last_change_date="Sun Aug 9 19:10:50 2026" xmlns:efxpt="http://www.efinixinc.com/peri_design_db" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xsi:schemaLocation="http://www.efinixinc.com/peri_design_db peri_design_db.xsd ">
<efxpt:device_info>
<efxpt:iobank_info>
<efxpt:iobank name="2A" iostd="1.8 V LVCMOS" is_dyn_voltage="false" mode_sel_name="2A_MODE_SEL"/>
@@ -248,13 +248,13 @@
<efxpt:gen_pin>
<efxpt:pin name="" type_name="SHIFT_ENA" is_bus="false"/>
<efxpt:pin name="" type_name="DESKEWED" is_bus="false"/>
<efxpt:pin name="" type_name="CFG_CLK" is_bus="false" is_clk="true" is_clk_invert="false"/>
<efxpt:pin name="" type_name="CFG_DATA_IN" is_bus="false"/>
<efxpt:pin name="" type_name="CFG_DATA_OUT" is_bus="false"/>
<efxpt:pin name="" type_name="CFG_SEL" is_bus="false"/>
<efxpt:pin name="" type_name="USER_SSC_EN" is_bus="false"/>
<efxpt:pin name="" type_name="SHIFT" is_bus="true"/>
<efxpt:pin name="" type_name="SHIFT_SEL" is_bus="true"/>
<efxpt:pin name="" type_name="CFG_CLK" is_bus="false" is_clk="true" is_clk_invert="false"/>
</efxpt:gen_pin>
<efxpt:comp_output_clock name="io_sysFbClk" number="0" out_divider="40" is_dyn_phase="false" phase_setting="0" is_inverted="false" conn_type="gclk" clkmux_buf_name="">
<efxpt:gen_pin/>
@@ -295,13 +295,13 @@
<efxpt:gen_pin>
<efxpt:pin name="" type_name="SHIFT_ENA" is_bus="false"/>
<efxpt:pin name="" type_name="DESKEWED" is_bus="false"/>
<efxpt:pin name="" type_name="CFG_CLK" is_bus="false" is_clk="true" is_clk_invert="false"/>
<efxpt:pin name="" type_name="CFG_DATA_IN" is_bus="false"/>
<efxpt:pin name="" type_name="CFG_DATA_OUT" is_bus="false"/>
<efxpt:pin name="" type_name="CFG_SEL" is_bus="false"/>
<efxpt:pin name="" type_name="USER_SSC_EN" is_bus="false"/>
<efxpt:pin name="" type_name="SHIFT" is_bus="true"/>
<efxpt:pin name="" type_name="SHIFT_SEL" is_bus="true"/>
<efxpt:pin name="" type_name="CFG_CLK" is_bus="false" is_clk="true" is_clk_invert="false"/>
</efxpt:gen_pin>
<efxpt:comp_output_clock name="io_memFbClk" number="0" out_divider="40" is_dyn_phase="false" phase_setting="0" is_inverted="false" conn_type="gclk" clkmux_buf_name="">
<efxpt:gen_pin/>
@@ -346,13 +346,13 @@
<efxpt:gen_pin>
<efxpt:pin name="" type_name="SHIFT_ENA" is_bus="false"/>
<efxpt:pin name="" type_name="DESKEWED" is_bus="false"/>
<efxpt:pin name="" type_name="CFG_CLK" is_bus="false" is_clk="true" is_clk_invert="false"/>
<efxpt:pin name="" type_name="CFG_DATA_IN" is_bus="false"/>
<efxpt:pin name="" type_name="CFG_DATA_OUT" is_bus="false"/>
<efxpt:pin name="" type_name="CFG_SEL" is_bus="false"/>
<efxpt:pin name="" type_name="USER_SSC_EN" is_bus="false"/>
<efxpt:pin name="" type_name="SHIFT" is_bus="true"/>
<efxpt:pin name="" type_name="SHIFT_SEL" is_bus="true"/>
<efxpt:pin name="" type_name="CFG_CLK" is_bus="false" is_clk="true" is_clk_invert="false"/>
</efxpt:gen_pin>
<efxpt:comp_output_clock name="tse_pll_clk_CLKOUT0" number="0" out_divider="10" is_dyn_phase="false" phase_setting="0" is_inverted="false" conn_type="gclk" clkmux_buf_name="">
<efxpt:gen_pin/>
@@ -559,7 +559,6 @@
<efxpt:param name="DQ_PULLUP_ODT" value="Hi-Z" value_type="str"/>
<efxpt:param name="FPGA_VREF_RANGE0" value="20.300" value_type="float"/>
<efxpt:param name="FPGA_VREF_RANGE1" value="23.000" value_type="float"/>
<efxpt:param name="LP_AUTO_MODE" value="Disable" value_type="str"/>
<efxpt:param name="MEM_FPGA_VREF_RANGE" value="Range 1" value_type="str"/>
</efxpt:cs_fpga>
<efxpt:cs_memory>
@@ -665,7 +664,7 @@
<efxpt:param name="CUSTOM_INSTRUCTION_3_EN" value="true" value_type="bool"/>
<efxpt:param name="JTAG_TYPE" value="FPGA" value_type="str"/>
<efxpt:param name="MEM_CLK_SOURCE" value="Clock 0" value_type="str"/>
<efxpt:param name="OCR_FILE_PATH" value="EfxSapphireHpSoc_bootloader/default_bootloader.hex" value_type="str"/>
<efxpt:param name="OCR_FILE_PATH" value="" value_type="str"/>
<efxpt:param name="PIPELINE_SOC_AXI_MEM_INTERFACE_EN" value="false" value_type="bool"/>
<efxpt:param name="SYS_CLK_SOURCE" value="Clock 0" value_type="str"/>
<efxpt:param name="WRITEBUFFER_SOC_AXI_INTERFACE_EN" value="false" value_type="bool"/>