bslathi19/wireguard_fpga
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This commit is contained in:
Byron Lathi
2026-08-08 21:41:43 -07:00
parent a76a054387
commit 82c05ac4dc
102 changed files with 80937 additions and 633 deletions
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.gitignore vendored
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__pycache__/
# Simulations
sim_build/
sim_build/
outflow/
work*/

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.gitmodules vendored
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[submodule "src/common/crypto"]
path = src/common/crypto
url = ../../bslathi19/crypto.git
[submodule "src/common/taxi"]
path = src/common/taxi
url = ../../bslathi19/taxi.git
[submodule "src/common/fifo"]
path = src/common/fifo
url = https://github.com/olofk/fifo.git
[submodule "src/common/taxi-bsl"]
path = src/common/taxi-bsl
url = ../../bslathi19/taxi-bsl.git

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Ti375C529_devkit/.lock Normal file
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4176154

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Ti375C529_devkit/EfxSapphireHpSoc_bootloader/default_bootloader.hex Normal file
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:02000004F90001
:1000000097110000938181AC23A00182732540F1F8
:1000100015C503A5018275DD0F0020020F10000039
:1000200083A7C181014581450146828723AEA18016
:100030000F001001054523A0A182828013818192C7
:1000400013850181938501811386C18163FAC500FF
:100050008322050023A0550011059105E3EAC5FEA2
:100060001385C181938581826377B50023200500C4
:0E0070001105E36DB5FEDD2A192001A0828086
:10007E00B70701E81307E01098C7B70701E81D4757
:10008E00D8C771A8B70603E8416791067D179C4251
:10009E00F98FF5DF856793870780370703E81CC361
:1000AE008280B70603E8416791067D179C42F98F5F
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:1000FE00B7C7B0F8E11794439386A60F984333879A
:10010E00E640E35D07FEB70603E8416791067D17FB
:10011E00130600109C42F98FE39EC7FE82804111A8
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:10013E00B70703E898D39546B70703E8D4D3B707B4
:10014E0003E898D71D47B70703E8D8D755371D3FA3
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:10019E00B70603E8416791067D179C42F98FF5DF9C
:1001AE00856793870788370703E81CC31305F00993
:1001BE001537C53DB7C7B0F8E11794434967130724
:1001CE00874F2A84BA9698433387E640E35D07FE4D
:1001DE00553D393FB70603E8416791067D179C42AE
:1001EE00F98FF5DF856793870788370703E81CC308
:1001FE009307D009130590026304F4001305900EC3
:10020E00D13D4935F535B70603E8416791067D17AF
:10021E009C42F98FF5DF856793870788370703E8D8
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:10023E0001454D350145793D0564B70402009535FC
:10024E00A2872380A7000504E31B94FE253D0565C8
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:10026E0022C44AC097070000938747061704000070
:10027E001304C40506C626C233898740638B8700E4
:10028E001359294081441C40850411048297E3ECE4
:10029E0024FF9707000093876703170400001304D9
:1002AE00E4023389874013592940638987008144CA
:1002BE001C40850411048297E3EC24FFB2402244D3
:0802CE009244024941018280C3
:0C02D6000000000000000000000000001C
:04000005F9000000FE
:00000001FF

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Ti375C529_devkit/Ti375C529_devkit.isf Normal file
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# Efinity Interface Configuration
# Version: 2026.1.132
# Date: 2026-08-08 20:48
#
# Copyright (C) 2013 - 2026 Efinix Inc. All rights reserved.
#
# Device: Ti375C529
# Package: 529-ball FBGA (final)
# Project: Ti375C529_devkit
# Configuration mode: active (x1)
# Timing Model: C4 (final)
# Device setting
design.set_device_property("2A","DYNAMIC_VOLTAGE","0","IOBANK")
design.set_mode_sel_name("2A","2A_MODE_SEL","2A")
design.set_device_property("2A","VOLTAGE","1.8","IOBANK")
design.set_device_property("2B","DYNAMIC_VOLTAGE","0","IOBANK")
design.set_mode_sel_name("2B","2B_MODE_SEL","2B")
design.set_device_property("2B","VOLTAGE","1.8","IOBANK")
design.set_device_property("2C","DYNAMIC_VOLTAGE","0","IOBANK")
design.set_mode_sel_name("2C","2C_MODE_SEL","2C")
design.set_device_property("2C","VOLTAGE","1.8","IOBANK")
design.set_device_property("2D","DYNAMIC_VOLTAGE","0","IOBANK")
design.set_mode_sel_name("2D","2D_MODE_SEL","2D")
design.set_device_property("2D","VOLTAGE","1.8","IOBANK")
design.set_device_property("2E","DYNAMIC_VOLTAGE","0","IOBANK")
design.set_mode_sel_name("2E","2E_MODE_SEL","2E")
design.set_device_property("2E","VOLTAGE","1.8","IOBANK")
design.set_device_property("4A_4B","DYNAMIC_VOLTAGE","0","IOBANK")
design.set_mode_sel_name("4A_4B","4A_4B_MODE_SEL","4A_4B")
design.set_device_property("4A_4B","VOLTAGE","1.8","IOBANK")
design.set_device_property("4C","DYNAMIC_VOLTAGE","0","IOBANK")
design.set_mode_sel_name("4C","4C_MODE_SEL","4C")
design.set_device_property("4C","VOLTAGE","1.8","IOBANK")
design.set_device_property("4D","DYNAMIC_VOLTAGE","0","IOBANK")
design.set_mode_sel_name("4D","4D_MODE_SEL","4D")
design.set_device_property("4D","VOLTAGE","1.8","IOBANK")
design.set_device_property("BL2_BL3","DYNAMIC_VOLTAGE","0","IOBANK")
design.set_mode_sel_name("BL2_BL3","BL2_BL3_MODE_SEL","BL2_BL3")
design.set_device_property("BL2_BL3","VOLTAGE","3.3","IOBANK")
design.set_device_property("BR0","DYNAMIC_VOLTAGE","0","IOBANK")
design.set_mode_sel_name("BR0","BR0_MODE_SEL","BR0")
design.set_device_property("BR0","VOLTAGE","3.3","IOBANK")
design.set_device_property("BR3_BR4","DYNAMIC_VOLTAGE","0","IOBANK")
design.set_mode_sel_name("BR3_BR4","BR3_BR4_MODE_SEL","BR3_BR4")
design.set_device_property("BR3_BR4","VOLTAGE","3.3","IOBANK")
design.set_device_property("TL1_TL5","DYNAMIC_VOLTAGE","0","IOBANK")
design.set_mode_sel_name("TL1_TL5","TL1_TL5_MODE_SEL","TL1_TL5")
design.set_device_property("TL1_TL5","VOLTAGE","3.3","IOBANK")
design.set_device_property("TR0","DYNAMIC_VOLTAGE","0","IOBANK")
design.set_mode_sel_name("TR0","TR0_MODE_SEL","TR0")
design.set_device_property("TR0","VOLTAGE","3.3","IOBANK")
design.set_device_property("TR1","DYNAMIC_VOLTAGE","0","IOBANK")
design.set_mode_sel_name("TR1","TR1_MODE_SEL","TR1")
design.set_device_property("TR1","VOLTAGE","3.3","IOBANK")
design.set_device_property("TR2","DYNAMIC_VOLTAGE","0","IOBANK")
design.set_mode_sel_name("TR2","TR2_MODE_SEL","TR2")
design.set_device_property("TR2","VOLTAGE","3.3","IOBANK")
design.set_device_property("seu","ENA_DETECT","0","SEU")
design.set_device_property("cfg","CBSEL_PIN","cfg_CBSEL","RU")
design.set_device_property("cfg","CLK_PIN","","RU")
design.set_device_property("cfg","CONFIG_PIN","cfg_CONFIG","RU")
design.set_device_property("cfg","ENA_PIN","cfg_ENA","RU")
design.set_device_property("cfg","ERROR_PIN","cfg_ERROR","RU")
design.set_device_property("cfg","INVERT_CLK_EN","0","RU")
design.set_device_property("cfg","RECONFIG_EN","0","RU")
design.set_device_property("cfg","REMOTE_UPDATE_RETRIES","3","RU")
design.set_device_property("Bottom","CORE0_PIN","","CLKMUX")
design.set_device_property("Bottom","CORE1_PIN","","CLKMUX")
design.set_device_property("Bottom","CORE2_PIN","","CLKMUX")
design.set_device_property("Bottom","CORE3_PIN","","CLKMUX")
design.set_device_property("Bottom","DYN_MUX0_EN","0","CLKMUX")
design.set_device_property("Bottom","DYN_MUX7_EN","0","CLKMUX")
design.set_device_property("Left","CORE0_PIN","","CLKMUX")
design.set_device_property("Left","CORE1_PIN","","CLKMUX")
design.set_device_property("Left","CORE2_PIN","","CLKMUX")
design.set_device_property("Left","CORE3_PIN","","CLKMUX")
design.set_device_property("Left","DYN_MUX0_EN","0","CLKMUX")
design.set_device_property("Left","DYN_MUX7_EN","0","CLKMUX")
design.set_device_property("Right","CORE0_PIN","","CLKMUX")
design.set_device_property("Right","CORE1_PIN","","CLKMUX")
design.set_device_property("Right","CORE2_PIN","","CLKMUX")
design.set_device_property("Right","CORE3_PIN","","CLKMUX")
design.set_device_property("Right","DYN_MUX0_EN","0","CLKMUX")
design.set_device_property("Right","DYN_MUX7_EN","0","CLKMUX")
design.set_device_property("Top","CORE0_PIN","","CLKMUX")
design.set_device_property("Top","CORE1_PIN","","CLKMUX")
design.set_device_property("Top","CORE2_PIN","","CLKMUX")
design.set_device_property("Top","CORE3_PIN","","CLKMUX")
design.set_device_property("Top","DYN_MUX0_EN","0","CLKMUX")
design.set_device_property("Top","DYN_MUX7_EN","0","CLKMUX")
design.set_gpio_unused_state("INPUT_WEAK_PULLUP")
# Create instance
design.create_block("soc_jtag_inst1","JTAG")
design.create_block("qcrv32_inst1","SOC")
# Set property, non-defaults
design.set_property("soc_jtag_inst1","NAME","soc_jtag_inst1","JTAG")
design.set_property("soc_jtag_inst1","RESOURCE","JTAG_USER1","JTAG")
design.set_property("soc_jtag_inst1","CAPTURE","ut_jtagCtrl_capture","JTAG")
design.set_property("soc_jtag_inst1","DRCK","","JTAG")
design.set_property("soc_jtag_inst1","RESET","ut_jtagCtrl_reset","JTAG")
design.set_property("soc_jtag_inst1","RUNTEST","","JTAG")
design.set_property("soc_jtag_inst1","SEL","ut_jtagCtrl_enable","JTAG")
design.set_property("soc_jtag_inst1","SHIFT","ut_jtagCtrl_shift","JTAG")
design.set_property("soc_jtag_inst1","TCK","jtagCtrl_tck","JTAG")
design.set_property("soc_jtag_inst1","TDI","ut_jtagCtrl_tdi","JTAG")
design.set_property("soc_jtag_inst1","TMS","","JTAG")
design.set_property("soc_jtag_inst1","UPDATE","ut_jtagCtrl_update","JTAG")
design.set_property("soc_jtag_inst1","TDO","ut_jtagCtrl_tdo","JTAG")
design.set_property("qcrv32_inst1","AXIAINTERRUPT_PIN","axiAInterrupt","SOC")
design.set_property("qcrv32_inst1","AXIA_ARADDR_PIN","axiA_araddr","SOC")
design.set_property("qcrv32_inst1","AXIA_ARBURST_PIN","axiA_arburst","SOC")
design.set_property("qcrv32_inst1","AXIA_ARCACHE_PIN","axiA_arcache","SOC")
design.set_property("qcrv32_inst1","AXIA_ARLEN_PIN","axiA_arlen","SOC")
design.set_property("qcrv32_inst1","AXIA_ARLOCK_PIN","axiA_arlock","SOC")
design.set_property("qcrv32_inst1","AXIA_ARPROT_PIN","axiA_arprot","SOC")
design.set_property("qcrv32_inst1","AXIA_ARQOS_PIN","axiA_arqos","SOC")
design.set_property("qcrv32_inst1","AXIA_ARREADY_PIN","axiA_arready","SOC")
design.set_property("qcrv32_inst1","AXIA_ARREGION_PIN","axiA_arregion","SOC")
design.set_property("qcrv32_inst1","AXIA_ARSIZE_PIN","axiA_arsize","SOC")
design.set_property("qcrv32_inst1","AXIA_ARVALID_PIN","axiA_arvalid","SOC")
design.set_property("qcrv32_inst1","AXIA_AWADDR_PIN","axiA_awaddr","SOC")
design.set_property("qcrv32_inst1","AXIA_AWBURST_PIN","axiA_awburst","SOC")
design.set_property("qcrv32_inst1","AXIA_AWCACHE_PIN","axiA_awcache","SOC")
design.set_property("qcrv32_inst1","AXIA_AWLEN_PIN","axiA_awlen","SOC")
design.set_property("qcrv32_inst1","AXIA_AWLOCK_PIN","axiA_awlock","SOC")
design.set_property("qcrv32_inst1","AXIA_AWPROT_PIN","axiA_awprot","SOC")
design.set_property("qcrv32_inst1","AXIA_AWQOS_PIN","axiA_awqos","SOC")
design.set_property("qcrv32_inst1","AXIA_AWREADY_PIN","axiA_awready","SOC")
design.set_property("qcrv32_inst1","AXIA_AWREGION_PIN","axiA_awregion","SOC")
design.set_property("qcrv32_inst1","AXIA_AWSIZE_PIN","axiA_awsize","SOC")
design.set_property("qcrv32_inst1","AXIA_AWVALID_PIN","axiA_awvalid","SOC")
design.set_property("qcrv32_inst1","AXIA_BREADY_PIN","axiA_bready","SOC")
design.set_property("qcrv32_inst1","AXIA_BRESP_PIN","axiA_bresp","SOC")
design.set_property("qcrv32_inst1","AXIA_BVALID_PIN","axiA_bvalid","SOC")
design.set_property("qcrv32_inst1","AXIA_RDATA_PIN","axiA_rdata","SOC")
design.set_property("qcrv32_inst1","AXIA_RLAST_PIN","axiA_rlast","SOC")
design.set_property("qcrv32_inst1","AXIA_RREADY_PIN","axiA_rready","SOC")
design.set_property("qcrv32_inst1","AXIA_RRESP_PIN","axiA_rresp","SOC")
design.set_property("qcrv32_inst1","AXIA_RVALID_PIN","axiA_rvalid","SOC")
design.set_property("qcrv32_inst1","AXIA_WDATA_PIN","axiA_wdata","SOC")
design.set_property("qcrv32_inst1","AXIA_WLAST_PIN","axiA_wlast","SOC")
design.set_property("qcrv32_inst1","AXIA_WREADY_PIN","axiA_wready","SOC")
design.set_property("qcrv32_inst1","AXIA_WSTRB_PIN","axiA_wstrb","SOC")
design.set_property("qcrv32_inst1","AXIA_WVALID_PIN","axiA_wvalid","SOC")
design.set_property("qcrv32_inst1","AXI_MASTER_EN","1","SOC")
design.set_property("qcrv32_inst1","AXI_SLAVE_EN","1","SOC")
design.set_property("qcrv32_inst1","CPU0_CUSTOMINSTRUCTION_CMD_READY_PIN","cpu0_customInstruction_cmd_ready","SOC")
design.set_property("qcrv32_inst1","CPU0_CUSTOMINSTRUCTION_CMD_VALID_PIN","cpu0_customInstruction_cmd_valid","SOC")
design.set_property("qcrv32_inst1","CPU0_CUSTOMINSTRUCTION_FUNCTION_ID_PIN","cpu0_customInstruction_function_id","SOC")
design.set_property("qcrv32_inst1","CPU0_CUSTOMINSTRUCTION_INPUTS_0_PIN","cpu0_customInstruction_inputs_0","SOC")
design.set_property("qcrv32_inst1","CPU0_CUSTOMINSTRUCTION_INPUTS_1_PIN","cpu0_customInstruction_inputs_1","SOC")
design.set_property("qcrv32_inst1","CPU0_CUSTOMINSTRUCTION_OUTPUTS_0_PIN","cpu0_customInstruction_outputs_0","SOC")
design.set_property("qcrv32_inst1","CPU0_CUSTOMINSTRUCTION_RSP_READY_PIN","cpu0_customInstruction_rsp_ready","SOC")
design.set_property("qcrv32_inst1","CPU0_CUSTOMINSTRUCTION_RSP_VALID_PIN","cpu0_customInstruction_rsp_valid","SOC")
design.set_property("qcrv32_inst1","CPU1_CUSTOMINSTRUCTION_CMD_READY_PIN","cpu1_customInstruction_cmd_ready","SOC")
design.set_property("qcrv32_inst1","CPU1_CUSTOMINSTRUCTION_CMD_VALID_PIN","cpu1_customInstruction_cmd_valid","SOC")
design.set_property("qcrv32_inst1","CPU1_CUSTOMINSTRUCTION_FUNCTION_ID_PIN","cpu1_customInstruction_function_id","SOC")
design.set_property("qcrv32_inst1","CPU1_CUSTOMINSTRUCTION_INPUTS_0_PIN","cpu1_customInstruction_inputs_0","SOC")
design.set_property("qcrv32_inst1","CPU1_CUSTOMINSTRUCTION_INPUTS_1_PIN","cpu1_customInstruction_inputs_1","SOC")
design.set_property("qcrv32_inst1","CPU1_CUSTOMINSTRUCTION_OUTPUTS_0_PIN","cpu1_customInstruction_outputs_0","SOC")
design.set_property("qcrv32_inst1","CPU1_CUSTOMINSTRUCTION_RSP_READY_PIN","cpu1_customInstruction_rsp_ready","SOC")
design.set_property("qcrv32_inst1","CPU1_CUSTOMINSTRUCTION_RSP_VALID_PIN","cpu1_customInstruction_rsp_valid","SOC")
design.set_property("qcrv32_inst1","CPU2_CUSTOMINSTRUCTION_CMD_READY_PIN","cpu2_customInstruction_cmd_ready","SOC")
design.set_property("qcrv32_inst1","CPU2_CUSTOMINSTRUCTION_CMD_VALID_PIN","cpu2_customInstruction_cmd_valid","SOC")
design.set_property("qcrv32_inst1","CPU2_CUSTOMINSTRUCTION_FUNCTION_ID_PIN","cpu2_customInstruction_function_id","SOC")
design.set_property("qcrv32_inst1","CPU2_CUSTOMINSTRUCTION_INPUTS_0_PIN","cpu2_customInstruction_inputs_0","SOC")
design.set_property("qcrv32_inst1","CPU2_CUSTOMINSTRUCTION_INPUTS_1_PIN","cpu2_customInstruction_inputs_1","SOC")
design.set_property("qcrv32_inst1","CPU2_CUSTOMINSTRUCTION_OUTPUTS_0_PIN","cpu2_customInstruction_outputs_0","SOC")
design.set_property("qcrv32_inst1","CPU2_CUSTOMINSTRUCTION_RSP_READY_PIN","cpu2_customInstruction_rsp_ready","SOC")
design.set_property("qcrv32_inst1","CPU2_CUSTOMINSTRUCTION_RSP_VALID_PIN","cpu2_customInstruction_rsp_valid","SOC")
design.set_property("qcrv32_inst1","CPU3_CUSTOMINSTRUCTION_CMD_READY_PIN","cpu3_customInstruction_cmd_ready","SOC")
design.set_property("qcrv32_inst1","CPU3_CUSTOMINSTRUCTION_CMD_VALID_PIN","cpu3_customInstruction_cmd_valid","SOC")
design.set_property("qcrv32_inst1","CPU3_CUSTOMINSTRUCTION_FUNCTION_ID_PIN","cpu3_customInstruction_function_id","SOC")
design.set_property("qcrv32_inst1","CPU3_CUSTOMINSTRUCTION_INPUTS_0_PIN","cpu3_customInstruction_inputs_0","SOC")
design.set_property("qcrv32_inst1","CPU3_CUSTOMINSTRUCTION_INPUTS_1_PIN","cpu3_customInstruction_inputs_1","SOC")
design.set_property("qcrv32_inst1","CPU3_CUSTOMINSTRUCTION_OUTPUTS_0_PIN","cpu3_customInstruction_outputs_0","SOC")
design.set_property("qcrv32_inst1","CPU3_CUSTOMINSTRUCTION_RSP_READY_PIN","cpu3_customInstruction_rsp_ready","SOC")
design.set_property("qcrv32_inst1","CPU3_CUSTOMINSTRUCTION_RSP_VALID_PIN","cpu3_customInstruction_rsp_valid","SOC")
design.set_property("qcrv32_inst1","CUSTOM_INSTRUCTION_0_EN","1","SOC")
design.set_property("qcrv32_inst1","CUSTOM_INSTRUCTION_1_EN","1","SOC")
design.set_property("qcrv32_inst1","CUSTOM_INSTRUCTION_2_EN","1","SOC")
design.set_property("qcrv32_inst1","CUSTOM_INSTRUCTION_3_EN","1","SOC")
design.set_property("qcrv32_inst1","IO_ASYNCRESET_PIN","io_asyncReset","SOC")
design.set_property("qcrv32_inst1","IO_CFUCLK_INVERT_EN","0","SOC")
design.set_property("qcrv32_inst1","IO_CFUCLK_PIN","io_cfuClk","SOC")
design.set_property("qcrv32_inst1","IO_CFURESET_PIN","io_cfuReset","SOC")
design.set_property("qcrv32_inst1","IO_DDRMASTERS_0_AR_PAYLOAD_ADDR_PIN","io_ddrMasters_0_ar_payload_addr","SOC")
design.set_property("qcrv32_inst1","IO_DDRMASTERS_0_AR_PAYLOAD_BURST_PIN","io_ddrMasters_0_ar_payload_burst","SOC")
design.set_property("qcrv32_inst1","IO_DDRMASTERS_0_AR_PAYLOAD_CACHE_PIN","io_ddrMasters_0_ar_payload_cache","SOC")
design.set_property("qcrv32_inst1","IO_DDRMASTERS_0_AR_PAYLOAD_ID_PIN","io_ddrMasters_0_ar_payload_id","SOC")
design.set_property("qcrv32_inst1","IO_DDRMASTERS_0_AR_PAYLOAD_LEN_PIN","io_ddrMasters_0_ar_payload_len","SOC")
design.set_property("qcrv32_inst1","IO_DDRMASTERS_0_AR_PAYLOAD_LOCK_PIN","io_ddrMasters_0_ar_payload_lock","SOC")
design.set_property("qcrv32_inst1","IO_DDRMASTERS_0_AR_PAYLOAD_PROT_PIN","io_ddrMasters_0_ar_payload_prot","SOC")
design.set_property("qcrv32_inst1","IO_DDRMASTERS_0_AR_PAYLOAD_QOS_PIN","io_ddrMasters_0_ar_payload_qos","SOC")
design.set_property("qcrv32_inst1","IO_DDRMASTERS_0_AR_PAYLOAD_REGION_PIN","io_ddrMasters_0_ar_payload_region","SOC")
design.set_property("qcrv32_inst1","IO_DDRMASTERS_0_AR_PAYLOAD_SIZE_PIN","io_ddrMasters_0_ar_payload_size","SOC")
design.set_property("qcrv32_inst1","IO_DDRMASTERS_0_AR_READY_PIN","io_ddrMasters_0_ar_ready","SOC")
design.set_property("qcrv32_inst1","IO_DDRMASTERS_0_AR_VALID_PIN","io_ddrMasters_0_ar_valid","SOC")
design.set_property("qcrv32_inst1","IO_DDRMASTERS_0_AW_PAYLOAD_ADDR_PIN","io_ddrMasters_0_aw_payload_addr","SOC")
design.set_property("qcrv32_inst1","IO_DDRMASTERS_0_AW_PAYLOAD_ALLSTRB_PIN","io_ddrMasters_0_aw_payload_allStrb","SOC")
design.set_property("qcrv32_inst1","IO_DDRMASTERS_0_AW_PAYLOAD_BURST_PIN","io_ddrMasters_0_aw_payload_burst","SOC")
design.set_property("qcrv32_inst1","IO_DDRMASTERS_0_AW_PAYLOAD_CACHE_PIN","io_ddrMasters_0_aw_payload_cache","SOC")
design.set_property("qcrv32_inst1","IO_DDRMASTERS_0_AW_PAYLOAD_ID_PIN","io_ddrMasters_0_aw_payload_id","SOC")
design.set_property("qcrv32_inst1","IO_DDRMASTERS_0_AW_PAYLOAD_LEN_PIN","io_ddrMasters_0_aw_payload_len","SOC")
design.set_property("qcrv32_inst1","IO_DDRMASTERS_0_AW_PAYLOAD_LOCK_PIN","io_ddrMasters_0_aw_payload_lock","SOC")
design.set_property("qcrv32_inst1","IO_DDRMASTERS_0_AW_PAYLOAD_PROT_PIN","io_ddrMasters_0_aw_payload_prot","SOC")
design.set_property("qcrv32_inst1","IO_DDRMASTERS_0_AW_PAYLOAD_QOS_PIN","io_ddrMasters_0_aw_payload_qos","SOC")
design.set_property("qcrv32_inst1","IO_DDRMASTERS_0_AW_PAYLOAD_REGION_PIN","io_ddrMasters_0_aw_payload_region","SOC")
design.set_property("qcrv32_inst1","IO_DDRMASTERS_0_AW_PAYLOAD_SIZE_PIN","io_ddrMasters_0_aw_payload_size","SOC")
design.set_property("qcrv32_inst1","IO_DDRMASTERS_0_AW_READY_PIN","io_ddrMasters_0_aw_ready","SOC")
design.set_property("qcrv32_inst1","IO_DDRMASTERS_0_AW_VALID_PIN","io_ddrMasters_0_aw_valid","SOC")
design.set_property("qcrv32_inst1","IO_DDRMASTERS_0_B_PAYLOAD_ID_PIN","io_ddrMasters_0_b_payload_id","SOC")
design.set_property("qcrv32_inst1","IO_DDRMASTERS_0_B_PAYLOAD_RESP_PIN","io_ddrMasters_0_b_payload_resp","SOC")
design.set_property("qcrv32_inst1","IO_DDRMASTERS_0_B_READY_PIN","io_ddrMasters_0_b_ready","SOC")
design.set_property("qcrv32_inst1","IO_DDRMASTERS_0_B_VALID_PIN","io_ddrMasters_0_b_valid","SOC")
design.set_property("qcrv32_inst1","IO_DDRMASTERS_0_CLK_INVERT_EN","0","SOC")
design.set_property("qcrv32_inst1","IO_DDRMASTERS_0_CLK_PIN","io_ddrMasters_0_clk","SOC")
design.set_property("qcrv32_inst1","IO_DDRMASTERS_0_RESET_PIN","io_ddrMasters_0_reset","SOC")
design.set_property("qcrv32_inst1","IO_DDRMASTERS_0_R_PAYLOAD_DATA_PIN","io_ddrMasters_0_r_payload_data","SOC")
design.set_property("qcrv32_inst1","IO_DDRMASTERS_0_R_PAYLOAD_ID_PIN","io_ddrMasters_0_r_payload_id","SOC")
design.set_property("qcrv32_inst1","IO_DDRMASTERS_0_R_PAYLOAD_LAST_PIN","io_ddrMasters_0_r_payload_last","SOC")
design.set_property("qcrv32_inst1","IO_DDRMASTERS_0_R_PAYLOAD_RESP_PIN","io_ddrMasters_0_r_payload_resp","SOC")
design.set_property("qcrv32_inst1","IO_DDRMASTERS_0_R_READY_PIN","io_ddrMasters_0_r_ready","SOC")
design.set_property("qcrv32_inst1","IO_DDRMASTERS_0_R_VALID_PIN","io_ddrMasters_0_r_valid","SOC")
design.set_property("qcrv32_inst1","IO_DDRMASTERS_0_W_PAYLOAD_DATA_PIN","io_ddrMasters_0_w_payload_data","SOC")
design.set_property("qcrv32_inst1","IO_DDRMASTERS_0_W_PAYLOAD_LAST_PIN","io_ddrMasters_0_w_payload_last","SOC")
design.set_property("qcrv32_inst1","IO_DDRMASTERS_0_W_PAYLOAD_STRB_PIN","io_ddrMasters_0_w_payload_strb","SOC")
design.set_property("qcrv32_inst1","IO_DDRMASTERS_0_W_READY_PIN","io_ddrMasters_0_w_ready","SOC")
design.set_property("qcrv32_inst1","IO_DDRMASTERS_0_W_VALID_PIN","io_ddrMasters_0_w_valid","SOC")
design.set_property("qcrv32_inst1","IO_JTAG_TCK_INVERT_EN","0","SOC")
design.set_property("qcrv32_inst1","IO_JTAG_TCK_PIN","","SOC")
design.set_property("qcrv32_inst1","IO_JTAG_TDI_PIN","","SOC")
design.set_property("qcrv32_inst1","IO_JTAG_TDO_PIN","","SOC")
design.set_property("qcrv32_inst1","IO_JTAG_TMS_PIN","","SOC")
design.set_property("qcrv32_inst1","IO_PERIPHERALCLK_INVERT_EN","0","SOC")
design.set_property("qcrv32_inst1","IO_PERIPHERALCLK_PIN","io_peripheralClk","SOC")
design.set_property("qcrv32_inst1","IO_PERIPHERALRESET_PIN","io_peripheralReset","SOC")
design.set_property("qcrv32_inst1","IO_SYSTEMRESET_PIN","io_systemReset","SOC")
design.set_property("qcrv32_inst1","JTAGCTRL_CAPTURE_PIN","jtagCtrl_capture","SOC")
design.set_property("qcrv32_inst1","JTAGCTRL_ENABLE_PIN","jtagCtrl_enable","SOC")
design.set_property("qcrv32_inst1","JTAGCTRL_RESET_PIN","jtagCtrl_reset","SOC")
design.set_property("qcrv32_inst1","JTAGCTRL_SHIFT_PIN","jtagCtrl_shift","SOC")
design.set_property("qcrv32_inst1","JTAGCTRL_TCK_INVERT_EN","0","SOC")
design.set_property("qcrv32_inst1","JTAGCTRL_TCK_PIN","jtagCtrl_tck","SOC")
design.set_property("qcrv32_inst1","JTAGCTRL_TDI_PIN","jtagCtrl_tdi","SOC")
design.set_property("qcrv32_inst1","JTAGCTRL_TDO_PIN","jtagCtrl_tdo","SOC")
design.set_property("qcrv32_inst1","JTAGCTRL_UPDATE_PIN","jtagCtrl_update","SOC")
design.set_property("qcrv32_inst1","JTAG_TYPE","FPGA","SOC")
design.set_property("qcrv32_inst1","MEM_CLK_SOURCE","Clock 0","SOC")
design.set_property("qcrv32_inst1","OCR_FILE_PATH","EfxSapphireHpSoc_bootloader/default_bootloader.hex","SOC")
design.set_property("qcrv32_inst1","PIPELINE_SOC_AXI_MEM_INTERFACE_EN","0","SOC")
design.set_property("qcrv32_inst1","SYS_CLK_SOURCE","Clock 0","SOC")
design.set_property("qcrv32_inst1","USERINTERRUPTA_PIN","userInterruptA","SOC")
design.set_property("qcrv32_inst1","USERINTERRUPTB_PIN","userInterruptB","SOC")
design.set_property("qcrv32_inst1","USERINTERRUPTC_PIN","userInterruptC","SOC")
design.set_property("qcrv32_inst1","USERINTERRUPTD_PIN","userInterruptD","SOC")
design.set_property("qcrv32_inst1","USERINTERRUPTE_PIN","userInterruptE","SOC")
design.set_property("qcrv32_inst1","USERINTERRUPTF_PIN","userInterruptF","SOC")
design.set_property("qcrv32_inst1","USERINTERRUPTG_PIN","userInterruptG","SOC")
design.set_property("qcrv32_inst1","USERINTERRUPTH_PIN","userInterruptH","SOC")
design.set_property("qcrv32_inst1","USERINTERRUPTI_PIN","userInterruptI","SOC")
design.set_property("qcrv32_inst1","USERINTERRUPTJ_PIN","","SOC")
design.set_property("qcrv32_inst1","USERINTERRUPTK_PIN","","SOC")
design.set_property("qcrv32_inst1","USERINTERRUPTL_PIN","","SOC")
design.set_property("qcrv32_inst1","USERINTERRUPTM_PIN","","SOC")
design.set_property("qcrv32_inst1","USERINTERRUPTN_PIN","","SOC")
design.set_property("qcrv32_inst1","USERINTERRUPTO_PIN","","SOC")
design.set_property("qcrv32_inst1","USERINTERRUPTP_PIN","","SOC")
design.set_property("qcrv32_inst1","USERINTERRUPTQ_PIN","","SOC")
design.set_property("qcrv32_inst1","USERINTERRUPTR_PIN","","SOC")
design.set_property("qcrv32_inst1","USERINTERRUPTS_PIN","","SOC")
design.set_property("qcrv32_inst1","USERINTERRUPTT_PIN","","SOC")
design.set_property("qcrv32_inst1","USERINTERRUPTU_PIN","","SOC")
design.set_property("qcrv32_inst1","USERINTERRUPTV_PIN","","SOC")
design.set_property("qcrv32_inst1","USERINTERRUPTW_PIN","","SOC")
design.set_property("qcrv32_inst1","USERINTERRUPTX_PIN","","SOC")
design.set_property("qcrv32_inst1","WRITEBUFFER_SOC_AXI_INTERFACE_EN","0","SOC")
# Set resource assignment
design.assign_resource("soc_jtag_inst1","JTAG_USER1","JTAG")
design.assign_resource("qcrv32_inst1","SOC_0","SOC")

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Ti375C529_devkit/Ti375C529_devkit.peri.xml Normal file
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<?xml version="1.0" encoding="UTF-8"?>
<efxpt:design_db name="Ti375C529_devkit" device_def="Ti375C529" version="2026.1.132" db_version="20261009" last_change_date="Sat Aug 8 20:48:48 2026" xmlns:efxpt="http://www.efinixinc.com/peri_design_db" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xsi:schemaLocation="http://www.efinixinc.com/peri_design_db peri_design_db.xsd ">
<efxpt:device_info>
<efxpt:iobank_info>
<efxpt:iobank name="2A" iostd="1.8 V LVCMOS" is_dyn_voltage="false" mode_sel_name="2A_MODE_SEL"/>
<efxpt:iobank name="2B" iostd="1.8 V LVCMOS" is_dyn_voltage="false" mode_sel_name="2B_MODE_SEL"/>
<efxpt:iobank name="2C" iostd="1.8 V LVCMOS" is_dyn_voltage="false" mode_sel_name="2C_MODE_SEL"/>
<efxpt:iobank name="2D" iostd="1.8 V LVCMOS" is_dyn_voltage="false" mode_sel_name="2D_MODE_SEL"/>
<efxpt:iobank name="2E" iostd="1.8 V LVCMOS" is_dyn_voltage="false" mode_sel_name="2E_MODE_SEL"/>
<efxpt:iobank name="4A_4B" iostd="1.8 V LVCMOS" is_dyn_voltage="false" mode_sel_name="4A_4B_MODE_SEL"/>
<efxpt:iobank name="4C" iostd="1.8 V LVCMOS" is_dyn_voltage="false" mode_sel_name="4C_MODE_SEL"/>
<efxpt:iobank name="4D" iostd="1.8 V LVCMOS" is_dyn_voltage="false" mode_sel_name="4D_MODE_SEL"/>
<efxpt:iobank name="BL2_BL3" iostd="3.3 V LVCMOS" is_dyn_voltage="false" mode_sel_name="BL2_BL3_MODE_SEL"/>
<efxpt:iobank name="BR0" iostd="3.3 V LVCMOS" is_dyn_voltage="false" mode_sel_name="BR0_MODE_SEL"/>
<efxpt:iobank name="BR3_BR4" iostd="3.3 V LVCMOS" is_dyn_voltage="false" mode_sel_name="BR3_BR4_MODE_SEL"/>
<efxpt:iobank name="TL1_TL5" iostd="3.3 V LVCMOS" is_dyn_voltage="false" mode_sel_name="TL1_TL5_MODE_SEL"/>
<efxpt:iobank name="TR0" iostd="3.3 V LVCMOS" is_dyn_voltage="false" mode_sel_name="TR0_MODE_SEL"/>
<efxpt:iobank name="TR1" iostd="3.3 V LVCMOS" is_dyn_voltage="false" mode_sel_name="TR1_MODE_SEL"/>
<efxpt:iobank name="TR2" iostd="3.3 V LVCMOS" is_dyn_voltage="false" mode_sel_name="TR2_MODE_SEL"/>
</efxpt:iobank_info>
<efxpt:ctrl_info>
<efxpt:ctrl name="cfg" ctrl_def="CONFIG_CTRL0" clock_name="" is_clk_invert="false" cbsel_bus_name="cfg_CBSEL" config_ctrl_name="cfg_CONFIG" ena_capture_name="cfg_ENA" error_status_name="cfg_ERROR" um_signal_status_name="cfg_USR_STATUS" is_remote_update_enable="false" is_user_mode_enable="false">
<efxpt:gen_param>
<efxpt:param name="remote_update_retries" value="3" value_type="int"/>
</efxpt:gen_param>
</efxpt:ctrl>
</efxpt:ctrl_info>
<efxpt:seu_info>
<efxpt:seu name="seu" block_def="CONFIG_SEU0" mode="auto" ena_detect="false" wait_interval="16500000">
<efxpt:gen_pin>
<efxpt:pin name="seu_START" type_name="START" is_bus="false"/>
<efxpt:pin name="seu_INJECT_ERROR" type_name="INJECT_ERROR" is_bus="false"/>
<efxpt:pin name="seu_RST" type_name="RST" is_bus="false"/>
<efxpt:pin name="seu_CONFIG" type_name="CONFIG" is_bus="false"/>
<efxpt:pin name="seu_ERROR" type_name="ERROR" is_bus="false"/>
<efxpt:pin name="seu_DONE" type_name="DONE" is_bus="false"/>
</efxpt:gen_pin>
</efxpt:seu>
</efxpt:seu_info>
<efxpt:clkmux_info>
<efxpt:clkmux name="GCLKMUX_B" block_def="GCLKMUX_B" is_mux_bot0_dyn="false" is_mux_bot7_dyn="false">
<efxpt:gen_pin>
<efxpt:pin name="" type_name="ROUTE0" is_bus="false" is_clk="true" is_clk_invert="false"/>
<efxpt:pin name="" type_name="ROUTE1" is_bus="false" is_clk="true" is_clk_invert="false"/>
<efxpt:pin name="" type_name="ROUTE2" is_bus="false" is_clk="true" is_clk_invert="false"/>
<efxpt:pin name="" type_name="ROUTE3" is_bus="false" is_clk="true" is_clk_invert="false"/>
<efxpt:pin name="" type_name="DYN_MUX_OUT_0" is_bus="false"/>
<efxpt:pin name="" type_name="DYN_MUX_OUT_7" is_bus="false"/>
<efxpt:pin name="" type_name="DYN_MUX_SEL_0" is_bus="true"/>
<efxpt:pin name="" type_name="DYN_MUX_SEL_7" is_bus="true"/>
</efxpt:gen_pin>
</efxpt:clkmux>
<efxpt:clkmux name="GCLKMUX_L" block_def="GCLKMUX_L" is_mux_bot0_dyn="false" is_mux_bot7_dyn="false">
<efxpt:gen_pin>
<efxpt:pin name="" type_name="ROUTE0" is_bus="false" is_clk="true" is_clk_invert="false"/>
<efxpt:pin name="" type_name="ROUTE1" is_bus="false" is_clk="true" is_clk_invert="false"/>
<efxpt:pin name="" type_name="ROUTE2" is_bus="false" is_clk="true" is_clk_invert="false"/>
<efxpt:pin name="" type_name="ROUTE3" is_bus="false" is_clk="true" is_clk_invert="false"/>
<efxpt:pin name="" type_name="DYN_MUX_OUT_0" is_bus="false"/>
<efxpt:pin name="" type_name="DYN_MUX_OUT_7" is_bus="false"/>
<efxpt:pin name="" type_name="DYN_MUX_SEL_0" is_bus="true"/>
<efxpt:pin name="" type_name="DYN_MUX_SEL_7" is_bus="true"/>
</efxpt:gen_pin>
</efxpt:clkmux>
<efxpt:clkmux name="GCLKMUX_R" block_def="GCLKMUX_R" is_mux_bot0_dyn="false" is_mux_bot7_dyn="false">
<efxpt:gen_pin>
<efxpt:pin name="" type_name="ROUTE0" is_bus="false" is_clk="true" is_clk_invert="false"/>
<efxpt:pin name="" type_name="ROUTE1" is_bus="false" is_clk="true" is_clk_invert="false"/>
<efxpt:pin name="" type_name="ROUTE2" is_bus="false" is_clk="true" is_clk_invert="false"/>
<efxpt:pin name="" type_name="ROUTE3" is_bus="false" is_clk="true" is_clk_invert="false"/>
<efxpt:pin name="" type_name="DYN_MUX_OUT_0" is_bus="false"/>
<efxpt:pin name="" type_name="DYN_MUX_OUT_7" is_bus="false"/>
<efxpt:pin name="" type_name="DYN_MUX_SEL_0" is_bus="true"/>
<efxpt:pin name="" type_name="DYN_MUX_SEL_7" is_bus="true"/>
</efxpt:gen_pin>
</efxpt:clkmux>
<efxpt:clkmux name="GCLKMUX_T" block_def="GCLKMUX_T" is_mux_bot0_dyn="false" is_mux_bot7_dyn="false">
<efxpt:gen_pin>
<efxpt:pin name="" type_name="ROUTE0" is_bus="false" is_clk="true" is_clk_invert="false"/>
<efxpt:pin name="" type_name="ROUTE1" is_bus="false" is_clk="true" is_clk_invert="false"/>
<efxpt:pin name="" type_name="ROUTE2" is_bus="false" is_clk="true" is_clk_invert="false"/>
<efxpt:pin name="" type_name="ROUTE3" is_bus="false" is_clk="true" is_clk_invert="false"/>
<efxpt:pin name="" type_name="DYN_MUX_OUT_0" is_bus="false"/>
<efxpt:pin name="" type_name="DYN_MUX_OUT_7" is_bus="false"/>
<efxpt:pin name="" type_name="DYN_MUX_SEL_0" is_bus="true"/>
<efxpt:pin name="" type_name="DYN_MUX_SEL_7" is_bus="true"/>
</efxpt:gen_pin>
</efxpt:clkmux>
</efxpt:clkmux_info>
</efxpt:device_info>
<efxpt:gpio_info>
<efxpt:comp_gpio name="io_gpio_sw_n" gpio_def="GPIOL_52" mode="input" bus_name="" io_standard="3.3 V LVCMOS">
<efxpt:input_config name="io_gpio_sw_n" name_ddio_lo="" conn_type="normal" is_register="false" clock_name="" is_clock_inverted="false" pull_option="none" is_schmitt_trigger="false" ddio_type="none" is_bus_hold="false" delay="0" is_serial="false" is_dyn_delay="false" fastclk_name="" pullup_ena_name="io_gpio_sw_n_PULL_UP_ENA" dyn_delay_en_name="io_gpio_sw_n_DLY_ENA" dyn_delay_reset_name="io_gpio_sw_n_DLY_RST" dyn_delay_ctrl_name="io_gpio_sw_n_DLY_CTRL" clkmux_buf_name=""/>
</efxpt:comp_gpio>
<efxpt:comp_gpio name="phy_mdc" gpio_def="GPIOT_N_54" mode="output" bus_name="" io_standard="1.8 V LVCMOS">
<efxpt:output_config name="phy_mdc" name_ddio_lo="" register_option="none" clock_name="" is_clock_inverted="false" is_slew_rate="true" tied_option="none" ddio_type="none" delay="0" is_serial="false" drive_strength="4" fastclk_name=""/>
</efxpt:comp_gpio>
<efxpt:comp_gpio name="phy_mdio" gpio_def="GPIOT_P_55" mode="inout" bus_name="" io_standard="1.8 V LVCMOS">
<efxpt:input_config name="phy_mdi" name_ddio_lo="" conn_type="normal" is_register="true" clock_name="io_tseClk" is_clock_inverted="false" pull_option="none" is_schmitt_trigger="false" ddio_type="none" is_bus_hold="false" delay="0" is_serial="false" is_dyn_delay="false" fastclk_name="" pullup_ena_name="phy_mdio_PULL_UP_ENA" dyn_delay_en_name="phy_mdio_DLY_ENA" dyn_delay_reset_name="phy_mdio_DLY_RST" dyn_delay_ctrl_name="phy_mdio_DLY_CTRL" clkmux_buf_name=""/>
<efxpt:output_config name="phy_mdo" name_ddio_lo="" register_option="register" clock_name="io_tseClk" is_clock_inverted="false" is_slew_rate="true" tied_option="none" ddio_type="none" delay="0" is_serial="false" drive_strength="4" fastclk_name=""/>
<efxpt:output_enable_config name="phy_mdo_en" is_register="true" clock_name="io_tseClk" is_clock_inverted="false" name_oen="phy_mdio_OEN"/>
</efxpt:comp_gpio>
<efxpt:comp_gpio name="phy_rstn" gpio_def="GPIOR_144" mode="inout" bus_name="" io_standard="3.3 V LVCMOS">
<efxpt:input_config name="phy_rstn_IN" name_ddio_lo="" conn_type="normal" is_register="false" clock_name="" is_clock_inverted="false" pull_option="none" is_schmitt_trigger="false" ddio_type="none" is_bus_hold="false" delay="0" is_serial="false" is_dyn_delay="false" fastclk_name="" pullup_ena_name="phy_rstn_PULL_UP_ENA" dyn_delay_en_name="phy_rstn_DLY_ENA" dyn_delay_reset_name="phy_rstn_DLY_RST" dyn_delay_ctrl_name="phy_rstn_DLY_CTRL" clkmux_buf_name=""/>
<efxpt:output_config name="phy_rstn_OUT" name_ddio_lo="" register_option="none" clock_name="" is_clock_inverted="false" is_slew_rate="false" tied_option="__gnd__" ddio_type="none" delay="0" is_serial="false" drive_strength="4" fastclk_name=""/>
<efxpt:output_enable_config name="phy_rst" is_register="false" clock_name="" is_clock_inverted="false" name_oen="phy_rstn_OEN"/>
</efxpt:comp_gpio>
<efxpt:comp_gpio name="rgmii_rx_ctl" gpio_def="GPIOT_N_56" mode="input" bus_name="" io_standard="1.8 V LVCMOS">
<efxpt:input_config name="rgmii_rx_ctl_HI" name_ddio_lo="rgmii_rx_ctl_LO" conn_type="normal" is_register="true" clock_name="rgmii_rxc" is_clock_inverted="false" pull_option="none" is_schmitt_trigger="false" ddio_type="resync" is_bus_hold="false" delay="0" is_serial="false" is_dyn_delay="false" fastclk_name="" pullup_ena_name="rgmii_rx_ctl_PULL_UP_ENA" dyn_delay_en_name="rgmii_rx_ctl_DLY_ENA" dyn_delay_reset_name="rgmii_rx_ctl_DLY_RST" dyn_delay_ctrl_name="rgmii_rx_ctl_DLY_CTRL" clkmux_buf_name=""/>
</efxpt:comp_gpio>
<efxpt:comp_gpio name="rgmii_rxc_phy" gpio_def="GPIOT_N_55" mode="input" bus_name="" io_standard="1.8 V LVCMOS">
<efxpt:input_config name="rgmii_rxc_phy" name_ddio_lo="" conn_type="normal" is_register="false" clock_name="" is_clock_inverted="false" pull_option="none" is_schmitt_trigger="false" ddio_type="none" is_bus_hold="false" delay="0" is_serial="false" is_dyn_delay="false" fastclk_name="" pullup_ena_name="rgmii_rxc_phy_PULL_UP_ENA" dyn_delay_en_name="rgmii_rxc_phy_DLY_ENA" dyn_delay_reset_name="rgmii_rxc_phy_DLY_RST" dyn_delay_ctrl_name="rgmii_rxc_phy_DLY_CTRL" clkmux_buf_name=""/>
</efxpt:comp_gpio>
<efxpt:comp_gpio name="rgmii_rxc_slow" gpio_def="GPIOT_P_59" mode="input" bus_name="" io_standard="1.8 V LVCMOS">
<efxpt:input_config name="rgmii_rxc_slow" name_ddio_lo="" conn_type="normal" is_register="false" clock_name="" is_clock_inverted="false" pull_option="none" is_schmitt_trigger="false" ddio_type="none" is_bus_hold="false" delay="0" is_serial="false" is_dyn_delay="false" fastclk_name="" pullup_ena_name="rgmii_rxc_slow_PULL_UP_ENA" dyn_delay_en_name="rgmii_rxc_slow_DLY_ENA" dyn_delay_reset_name="rgmii_rxc_slow_DLY_RST" dyn_delay_ctrl_name="rgmii_rxc_slow_DLY_CTRL" clkmux_buf_name=""/>
</efxpt:comp_gpio>
<efxpt:comp_gpio name="rgmii_rxd[0]" gpio_def="GPIOT_P_57" mode="input" bus_name="rgmii_rxd" io_standard="1.8 V LVCMOS">
<efxpt:input_config name="rgmii_rxd_HI[0]" name_ddio_lo="rgmii_rxd_LO[0]" conn_type="normal" is_register="true" clock_name="rgmii_rxc" is_clock_inverted="false" pull_option="none" is_schmitt_trigger="false" ddio_type="resync" is_bus_hold="false" delay="0" is_serial="false" is_dyn_delay="false" fastclk_name="" pullup_ena_name="rgmii_rxd_PULL_UP_ENA[0]" dyn_delay_en_name="rgmii_rxd_DLY_ENA[0]" dyn_delay_reset_name="rgmii_rxd_DLY_RST[0]" dyn_delay_ctrl_name="rgmii_rxd_DLY_CTRL[0]" clkmux_buf_name=""/>
</efxpt:comp_gpio>
<efxpt:comp_gpio name="rgmii_rxd[1]" gpio_def="GPIOT_N_57" mode="input" bus_name="rgmii_rxd" io_standard="1.8 V LVCMOS">
<efxpt:input_config name="rgmii_rxd_HI[1]" name_ddio_lo="rgmii_rxd_LO[1]" conn_type="normal" is_register="true" clock_name="rgmii_rxc" is_clock_inverted="false" pull_option="none" is_schmitt_trigger="false" ddio_type="resync" is_bus_hold="false" delay="0" is_serial="false" is_dyn_delay="false" fastclk_name="" pullup_ena_name="rgmii_rxd_PULL_UP_ENA[1]" dyn_delay_en_name="rgmii_rxd_DLY_ENA[1]" dyn_delay_reset_name="rgmii_rxd_DLY_RST[1]" dyn_delay_ctrl_name="rgmii_rxd_DLY_CTRL[1]" clkmux_buf_name=""/>
</efxpt:comp_gpio>
<efxpt:comp_gpio name="rgmii_rxd[2]" gpio_def="GPIOT_P_58" mode="input" bus_name="rgmii_rxd" io_standard="1.8 V LVCMOS">
<efxpt:input_config name="rgmii_rxd_HI[2]" name_ddio_lo="rgmii_rxd_LO[2]" conn_type="normal" is_register="true" clock_name="rgmii_rxc" is_clock_inverted="false" pull_option="none" is_schmitt_trigger="false" ddio_type="resync" is_bus_hold="false" delay="0" is_serial="false" is_dyn_delay="false" fastclk_name="" pullup_ena_name="rgmii_rxd_PULL_UP_ENA[2]" dyn_delay_en_name="rgmii_rxd_DLY_ENA[2]" dyn_delay_reset_name="rgmii_rxd_DLY_RST[2]" dyn_delay_ctrl_name="rgmii_rxd_DLY_CTRL[2]" clkmux_buf_name=""/>
</efxpt:comp_gpio>
<efxpt:comp_gpio name="rgmii_rxd[3]" gpio_def="GPIOT_N_58" mode="input" bus_name="rgmii_rxd" io_standard="1.8 V LVCMOS">
<efxpt:input_config name="rgmii_rxd_HI[3]" name_ddio_lo="rgmii_rxd_LO[3]" conn_type="normal" is_register="true" clock_name="rgmii_rxc" is_clock_inverted="false" pull_option="none" is_schmitt_trigger="false" ddio_type="resync" is_bus_hold="false" delay="0" is_serial="false" is_dyn_delay="false" fastclk_name="" pullup_ena_name="rgmii_rxd_PULL_UP_ENA[3]" dyn_delay_en_name="rgmii_rxd_DLY_ENA[3]" dyn_delay_reset_name="rgmii_rxd_DLY_RST[3]" dyn_delay_ctrl_name="rgmii_rxd_DLY_CTRL[3]" clkmux_buf_name=""/>
</efxpt:comp_gpio>
<efxpt:comp_gpio name="rgmii_tx_ctl" gpio_def="GPIOT_N_51" mode="output" bus_name="" io_standard="1.8 V LVCMOS">
<efxpt:output_config name="rgmii_tx_ctl_HI" name_ddio_lo="rgmii_tx_ctl_LO" register_option="register" clock_name="io_tseClk" is_clock_inverted="false" is_slew_rate="false" tied_option="none" ddio_type="resync" delay="0" is_serial="false" drive_strength="16" fastclk_name=""/>
</efxpt:comp_gpio>
<efxpt:comp_gpio name="rgmii_txc" gpio_def="GPIOT_P_52" mode="output" bus_name="" io_standard="1.8 V LVCMOS">
<efxpt:output_config name="rgmii_txc_HI" name_ddio_lo="rgmii_txc_LO" register_option="register" clock_name="io_tseClk_90" is_clock_inverted="false" is_slew_rate="false" tied_option="none" ddio_type="resync" delay="0" is_serial="false" drive_strength="16" fastclk_name=""/>
</efxpt:comp_gpio>
<efxpt:comp_gpio name="rgmii_txd[0]" gpio_def="GPIOT_N_52" mode="output" bus_name="rgmii_txd" io_standard="1.8 V LVCMOS">
<efxpt:output_config name="rgmii_txd_HI[0]" name_ddio_lo="rgmii_txd_LO[0]" register_option="register" clock_name="io_tseClk" is_clock_inverted="false" is_slew_rate="false" tied_option="none" ddio_type="resync" delay="0" is_serial="false" drive_strength="16" fastclk_name=""/>
</efxpt:comp_gpio>
<efxpt:comp_gpio name="rgmii_txd[1]" gpio_def="GPIOT_P_53" mode="output" bus_name="rgmii_txd" io_standard="1.8 V LVCMOS">
<efxpt:output_config name="rgmii_txd_HI[1]" name_ddio_lo="rgmii_txd_LO[1]" register_option="register" clock_name="io_tseClk" is_clock_inverted="false" is_slew_rate="false" tied_option="none" ddio_type="resync" delay="0" is_serial="false" drive_strength="16" fastclk_name=""/>
</efxpt:comp_gpio>
<efxpt:comp_gpio name="rgmii_txd[2]" gpio_def="GPIOT_N_53" mode="output" bus_name="rgmii_txd" io_standard="1.8 V LVCMOS">
<efxpt:output_config name="rgmii_txd_HI[2]" name_ddio_lo="rgmii_txd_LO[2]" register_option="register" clock_name="io_tseClk" is_clock_inverted="false" is_slew_rate="false" tied_option="none" ddio_type="resync" delay="0" is_serial="false" drive_strength="16" fastclk_name=""/>
</efxpt:comp_gpio>
<efxpt:comp_gpio name="rgmii_txd[3]" gpio_def="GPIOT_P_54" mode="output" bus_name="rgmii_txd" io_standard="1.8 V LVCMOS">
<efxpt:output_config name="rgmii_txd_HI[3]" name_ddio_lo="rgmii_txd_LO[3]" register_option="register" clock_name="io_tseClk" is_clock_inverted="false" is_slew_rate="false" tied_option="none" ddio_type="resync" delay="0" is_serial="false" drive_strength="16" fastclk_name=""/>
</efxpt:comp_gpio>
<efxpt:comp_gpio name="sd_cd_n" gpio_def="GPIOT_P_49" mode="input" bus_name="" io_standard="1.8 V LVCMOS">
<efxpt:input_config name="sd_cd_n" name_ddio_lo="" conn_type="normal" is_register="false" clock_name="" is_clock_inverted="false" pull_option="none" is_schmitt_trigger="false" ddio_type="none" is_bus_hold="false" delay="0" is_serial="false" is_dyn_delay="false" fastclk_name="" pullup_ena_name="sd_cd_n_PULL_UP_ENA" dyn_delay_en_name="sd_cd_n_DLY_ENA" dyn_delay_reset_name="sd_cd_n_DLY_RST" dyn_delay_ctrl_name="sd_cd_n_DLY_CTRL" clkmux_buf_name=""/>
</efxpt:comp_gpio>
<efxpt:comp_gpio name="sd_clk" gpio_def="GPIOR_166" mode="output" bus_name="" io_standard="3.3 V LVCMOS">
<efxpt:output_config name="sd_clk_hi" name_ddio_lo="" register_option="register" clock_name="sd_base_clk" is_clock_inverted="false" is_slew_rate="false" tied_option="none" ddio_type="none" delay="0" is_serial="false" drive_strength="2" fastclk_name=""/>
</efxpt:comp_gpio>
<efxpt:comp_gpio name="sd_cmd" gpio_def="GPIOR_167" mode="inout" bus_name="" io_standard="3.3 V LVCMOS">
<efxpt:input_config name="sd_cmd_i" name_ddio_lo="" conn_type="normal" is_register="false" clock_name="" is_clock_inverted="false" pull_option="none" is_schmitt_trigger="false" ddio_type="none" is_bus_hold="false" delay="0" is_serial="false" is_dyn_delay="false" fastclk_name="" pullup_ena_name="sd_cmd_PULL_UP_ENA" dyn_delay_en_name="sd_cmd_DLY_ENA" dyn_delay_reset_name="sd_cmd_DLY_RST" dyn_delay_ctrl_name="sd_cmd_DLY_CTRL" clkmux_buf_name=""/>
<efxpt:output_config name="sd_cmd_o" name_ddio_lo="" register_option="none" clock_name="sd_base_clk" is_clock_inverted="false" is_slew_rate="false" tied_option="none" ddio_type="none" delay="0" is_serial="false" drive_strength="4" fastclk_name=""/>
<efxpt:output_enable_config name="sd_cmd_oe" is_register="false" clock_name="sd_base_clk" is_clock_inverted="false" name_oen="sd_cmd_OEN"/>
</efxpt:comp_gpio>
<efxpt:comp_gpio name="sd_dat[0]" gpio_def="GPIOR_168" mode="inout" bus_name="sd_dat" io_standard="3.3 V LVCMOS">
<efxpt:input_config name="sd_dat_i[0]" name_ddio_lo="" conn_type="normal" is_register="false" clock_name="" is_clock_inverted="false" pull_option="none" is_schmitt_trigger="false" ddio_type="none" is_bus_hold="false" delay="0" is_serial="false" is_dyn_delay="false" fastclk_name="" pullup_ena_name="sd_dat_PULL_UP_ENA[0]" dyn_delay_en_name="sd_dat_DLY_ENA[0]" dyn_delay_reset_name="sd_dat_DLY_RST[0]" dyn_delay_ctrl_name="sd_dat_DLY_CTRL[0]" clkmux_buf_name=""/>
<efxpt:output_config name="sd_dat_o[0]" name_ddio_lo="" register_option="none" clock_name="sd_base_clk" is_clock_inverted="false" is_slew_rate="false" tied_option="none" ddio_type="none" delay="0" is_serial="false" drive_strength="4" fastclk_name=""/>
<efxpt:output_enable_config name="sd_dat_oe[0]" is_register="false" clock_name="sd_base_clk" is_clock_inverted="false" name_oen="sd_dat_OEN[0]"/>
</efxpt:comp_gpio>
<efxpt:comp_gpio name="sd_dat[1]" gpio_def="GPIOR_169" mode="inout" bus_name="sd_dat" io_standard="3.3 V LVCMOS">
<efxpt:input_config name="sd_dat_i[1]" name_ddio_lo="" conn_type="normal" is_register="false" clock_name="" is_clock_inverted="false" pull_option="none" is_schmitt_trigger="false" ddio_type="none" is_bus_hold="false" delay="0" is_serial="false" is_dyn_delay="false" fastclk_name="" pullup_ena_name="sd_dat_PULL_UP_ENA[1]" dyn_delay_en_name="sd_dat_DLY_ENA[1]" dyn_delay_reset_name="sd_dat_DLY_RST[1]" dyn_delay_ctrl_name="sd_dat_DLY_CTRL[1]" clkmux_buf_name=""/>
<efxpt:output_config name="sd_dat_o[1]" name_ddio_lo="" register_option="none" clock_name="sd_base_clk" is_clock_inverted="false" is_slew_rate="false" tied_option="none" ddio_type="none" delay="0" is_serial="false" drive_strength="4" fastclk_name=""/>
<efxpt:output_enable_config name="sd_dat_oe[1]" is_register="false" clock_name="sd_base_clk" is_clock_inverted="false" name_oen="sd_dat_OEN[1]"/>
</efxpt:comp_gpio>
<efxpt:comp_gpio name="sd_dat[2]" gpio_def="GPIOR_170" mode="inout" bus_name="sd_dat" io_standard="3.3 V LVCMOS">
<efxpt:input_config name="sd_dat_i[2]" name_ddio_lo="" conn_type="normal" is_register="false" clock_name="" is_clock_inverted="false" pull_option="none" is_schmitt_trigger="false" ddio_type="none" is_bus_hold="false" delay="0" is_serial="false" is_dyn_delay="false" fastclk_name="" pullup_ena_name="sd_dat_PULL_UP_ENA[2]" dyn_delay_en_name="sd_dat_DLY_ENA[2]" dyn_delay_reset_name="sd_dat_DLY_RST[2]" dyn_delay_ctrl_name="sd_dat_DLY_CTRL[2]" clkmux_buf_name=""/>
<efxpt:output_config name="sd_dat_o[2]" name_ddio_lo="" register_option="none" clock_name="sd_base_clk" is_clock_inverted="false" is_slew_rate="false" tied_option="none" ddio_type="none" delay="0" is_serial="false" drive_strength="4" fastclk_name=""/>
<efxpt:output_enable_config name="sd_dat_oe[2]" is_register="false" clock_name="sd_base_clk" is_clock_inverted="false" name_oen="sd_dat_OEN[2]"/>
</efxpt:comp_gpio>
<efxpt:comp_gpio name="sd_dat[3]" gpio_def="GPIOR_171" mode="inout" bus_name="sd_dat" io_standard="3.3 V LVCMOS">
<efxpt:input_config name="sd_dat_i[3]" name_ddio_lo="" conn_type="normal" is_register="false" clock_name="" is_clock_inverted="false" pull_option="none" is_schmitt_trigger="false" ddio_type="none" is_bus_hold="false" delay="0" is_serial="false" is_dyn_delay="false" fastclk_name="" pullup_ena_name="sd_dat_PULL_UP_ENA[3]" dyn_delay_en_name="sd_dat_DLY_ENA[3]" dyn_delay_reset_name="sd_dat_DLY_RST[3]" dyn_delay_ctrl_name="sd_dat_DLY_CTRL[3]" clkmux_buf_name=""/>
<efxpt:output_config name="sd_dat_o[3]" name_ddio_lo="" register_option="none" clock_name="sd_base_clk" is_clock_inverted="false" is_slew_rate="false" tied_option="none" ddio_type="none" delay="0" is_serial="false" drive_strength="4" fastclk_name=""/>
<efxpt:output_enable_config name="sd_dat_oe[3]" is_register="false" clock_name="sd_base_clk" is_clock_inverted="false" name_oen="sd_dat_OEN[3]"/>
</efxpt:comp_gpio>
<efxpt:comp_gpio name="sd_wp" gpio_def="GPIOR_102" mode="input" bus_name="" io_standard="3.3 V LVCMOS">
<efxpt:input_config name="sd_wp" name_ddio_lo="" conn_type="normal" is_register="false" clock_name="" is_clock_inverted="false" pull_option="none" is_schmitt_trigger="false" ddio_type="none" is_bus_hold="false" delay="0" is_serial="false" is_dyn_delay="false" fastclk_name="" pullup_ena_name="sd_wp_PULL_UP_ENA" dyn_delay_en_name="sd_wp_DLY_ENA" dyn_delay_reset_name="sd_wp_DLY_RST" dyn_delay_ctrl_name="sd_wp_DLY_CTRL" clkmux_buf_name=""/>
</efxpt:comp_gpio>
<efxpt:comp_gpio name="soc_pll_peri_clk_ext_clk" gpio_def="GPIOT_P_50" mode="input" bus_name="" io_standard="1.8 V LVCMOS">
<efxpt:input_config name="soc_pll_peri_clk_ext_clk" name_ddio_lo="" conn_type="pll_clkin" is_register="false" clock_name="" is_clock_inverted="false" pull_option="none" is_schmitt_trigger="false" ddio_type="none" is_bus_hold="false" delay="0" is_serial="false" is_dyn_delay="false" fastclk_name="" pullup_ena_name="soc_pll_peri_clk_ext_clk_PULL_UP_ENA" dyn_delay_en_name="soc_pll_peri_clk_ext_clk_DLY_ENA" dyn_delay_reset_name="soc_pll_peri_clk_ext_clk_DLY_RST" dyn_delay_ctrl_name="soc_pll_peri_clk_ext_clk_DLY_CTRL" clkmux_buf_name=""/>
</efxpt:comp_gpio>
<efxpt:comp_gpio name="soc_pll_sys_clk_ext_clk" gpio_def="GPIOL_25" mode="input" bus_name="" io_standard="3.3 V LVCMOS">
<efxpt:input_config name="soc_pll_sys_clk_ext_clk" name_ddio_lo="" conn_type="pll_clkin" is_register="false" clock_name="" is_clock_inverted="false" pull_option="none" is_schmitt_trigger="false" ddio_type="none" is_bus_hold="false" delay="0" is_serial="false" is_dyn_delay="false" fastclk_name="" pullup_ena_name="soc_pll_sys_clk_ext_clk_PULL_UP_ENA" dyn_delay_en_name="soc_pll_sys_clk_ext_clk_DLY_ENA" dyn_delay_reset_name="soc_pll_sys_clk_ext_clk_DLY_RST" dyn_delay_ctrl_name="soc_pll_sys_clk_ext_clk_DLY_CTRL" clkmux_buf_name=""/>
</efxpt:comp_gpio>
<efxpt:comp_gpio name="system_gpio_0_io[0]" gpio_def="GPIOT_P_19" mode="inout" bus_name="system_gpio_0_io" io_standard="1.8 V LVCMOS">
<efxpt:input_config name="system_gpio_0_io_read[0]" name_ddio_lo="" conn_type="normal" is_register="false" clock_name="" is_clock_inverted="false" pull_option="none" is_schmitt_trigger="false" ddio_type="none" is_bus_hold="false" delay="0" is_serial="false" is_dyn_delay="false" fastclk_name="" pullup_ena_name="system_gpio_0_io_PULL_UP_ENA[0]" dyn_delay_en_name="system_gpio_0_io_DLY_ENA[0]" dyn_delay_reset_name="system_gpio_0_io_DLY_RST[0]" dyn_delay_ctrl_name="system_gpio_0_io_DLY_CTRL[0]" clkmux_buf_name=""/>
<efxpt:output_config name="system_gpio_0_io_write[0]" name_ddio_lo="" register_option="none" clock_name="" is_clock_inverted="false" is_slew_rate="false" tied_option="none" ddio_type="none" delay="0" is_serial="false" drive_strength="4" fastclk_name=""/>
<efxpt:output_enable_config name="system_gpio_0_io_writeEnable[0]" is_register="false" clock_name="" is_clock_inverted="false" name_oen="system_gpio_0_io_OEN[0]"/>
</efxpt:comp_gpio>
<efxpt:comp_gpio name="system_gpio_0_io[1]" gpio_def="GPIOL_23" mode="inout" bus_name="system_gpio_0_io" io_standard="3.3 V LVCMOS">
<efxpt:input_config name="system_gpio_0_io_read[1]" name_ddio_lo="" conn_type="normal" is_register="false" clock_name="" is_clock_inverted="false" pull_option="none" is_schmitt_trigger="false" ddio_type="none" is_bus_hold="false" delay="0" is_serial="false" is_dyn_delay="false" fastclk_name="" pullup_ena_name="system_gpio_0_io_PULL_UP_ENA[1]" dyn_delay_en_name="system_gpio_0_io_DLY_ENA[1]" dyn_delay_reset_name="system_gpio_0_io_DLY_RST[1]" dyn_delay_ctrl_name="system_gpio_0_io_DLY_CTRL[1]" clkmux_buf_name=""/>
<efxpt:output_config name="system_gpio_0_io_write[1]" name_ddio_lo="" register_option="none" clock_name="" is_clock_inverted="false" is_slew_rate="false" tied_option="none" ddio_type="none" delay="0" is_serial="false" drive_strength="2" fastclk_name=""/>
<efxpt:output_enable_config name="system_gpio_0_io_writeEnable[1]" is_register="false" clock_name="" is_clock_inverted="false" name_oen="system_gpio_0_io_OEN[1]"/>
</efxpt:comp_gpio>
<efxpt:comp_gpio name="system_gpio_0_io[2]" gpio_def="GPIOL_24" mode="inout" bus_name="system_gpio_0_io" io_standard="3.3 V LVCMOS">
<efxpt:input_config name="system_gpio_0_io_read[2]" name_ddio_lo="" conn_type="normal" is_register="false" clock_name="" is_clock_inverted="false" pull_option="none" is_schmitt_trigger="false" ddio_type="none" is_bus_hold="false" delay="0" is_serial="false" is_dyn_delay="false" fastclk_name="" pullup_ena_name="system_gpio_0_io_PULL_UP_ENA[2]" dyn_delay_en_name="system_gpio_0_io_DLY_ENA[2]" dyn_delay_reset_name="system_gpio_0_io_DLY_RST[2]" dyn_delay_ctrl_name="system_gpio_0_io_DLY_CTRL[2]" clkmux_buf_name=""/>
<efxpt:output_config name="system_gpio_0_io_write[2]" name_ddio_lo="" register_option="none" clock_name="" is_clock_inverted="false" is_slew_rate="false" tied_option="none" ddio_type="none" delay="0" is_serial="false" drive_strength="2" fastclk_name=""/>
<efxpt:output_enable_config name="system_gpio_0_io_writeEnable[2]" is_register="false" clock_name="" is_clock_inverted="false" name_oen="system_gpio_0_io_OEN[2]"/>
</efxpt:comp_gpio>
<efxpt:comp_gpio name="system_gpio_0_io[3]" gpio_def="GPIOT_N_50" mode="inout" bus_name="system_gpio_0_io" io_standard="1.8 V LVCMOS">
<efxpt:input_config name="system_gpio_0_io_read[3]" name_ddio_lo="" conn_type="normal" is_register="false" clock_name="" is_clock_inverted="false" pull_option="none" is_schmitt_trigger="false" ddio_type="none" is_bus_hold="false" delay="0" is_serial="false" is_dyn_delay="false" fastclk_name="" pullup_ena_name="system_gpio_0_io_PULL_UP_ENA[3]" dyn_delay_en_name="system_gpio_0_io_DLY_ENA[3]" dyn_delay_reset_name="system_gpio_0_io_DLY_RST[3]" dyn_delay_ctrl_name="system_gpio_0_io_DLY_CTRL[3]" clkmux_buf_name=""/>
<efxpt:output_config name="system_gpio_0_io_write[3]" name_ddio_lo="" register_option="none" clock_name="" is_clock_inverted="false" is_slew_rate="false" tied_option="none" ddio_type="none" delay="0" is_serial="false" drive_strength="4" fastclk_name=""/>
<efxpt:output_enable_config name="system_gpio_0_io_writeEnable[3]" is_register="false" clock_name="" is_clock_inverted="false" name_oen="system_gpio_0_io_OEN[3]"/>
</efxpt:comp_gpio>
<efxpt:comp_gpio name="system_i2c_0_io_scl" gpio_def="GPIOL_85" mode="inout" bus_name="" io_standard="3.3 V LVCMOS">
<efxpt:input_config name="system_i2c_0_io_scl_read" name_ddio_lo="" conn_type="normal" is_register="false" clock_name="" is_clock_inverted="false" pull_option="none" is_schmitt_trigger="false" ddio_type="none" is_bus_hold="false" delay="0" is_serial="false" is_dyn_delay="false" fastclk_name="" pullup_ena_name="system_i2c_0_io_scl_PULL_UP_ENA" dyn_delay_en_name="system_i2c_0_io_scl_DLY_ENA" dyn_delay_reset_name="system_i2c_0_io_scl_DLY_RST" dyn_delay_ctrl_name="system_i2c_0_io_scl_DLY_CTRL" clkmux_buf_name=""/>
<efxpt:output_config name="system_i2c_0_io_scl_write" name_ddio_lo="" register_option="none" clock_name="" is_clock_inverted="false" is_slew_rate="false" tied_option="none" ddio_type="none" delay="0" is_serial="false" drive_strength="2" fastclk_name=""/>
<efxpt:output_enable_config name="system_i2c_0_io_scl_writeEnable" is_register="false" clock_name="" is_clock_inverted="false" name_oen="system_i2c_0_io_scl_OEN"/>
</efxpt:comp_gpio>
<efxpt:comp_gpio name="system_i2c_0_io_sda" gpio_def="GPIOL_84" mode="inout" bus_name="" io_standard="3.3 V LVCMOS">
<efxpt:input_config name="system_i2c_0_io_sda_read" name_ddio_lo="" conn_type="normal" is_register="false" clock_name="" is_clock_inverted="false" pull_option="none" is_schmitt_trigger="false" ddio_type="none" is_bus_hold="false" delay="0" is_serial="false" is_dyn_delay="false" fastclk_name="" pullup_ena_name="system_i2c_0_io_sda_PULL_UP_ENA" dyn_delay_en_name="system_i2c_0_io_sda_DLY_ENA" dyn_delay_reset_name="system_i2c_0_io_sda_DLY_RST" dyn_delay_ctrl_name="system_i2c_0_io_sda_DLY_CTRL" clkmux_buf_name=""/>
<efxpt:output_config name="system_i2c_0_io_sda_write" name_ddio_lo="" register_option="none" clock_name="" is_clock_inverted="false" is_slew_rate="false" tied_option="none" ddio_type="none" delay="0" is_serial="false" drive_strength="2" fastclk_name=""/>
<efxpt:output_enable_config name="system_i2c_0_io_sda_writeEnable" is_register="false" clock_name="" is_clock_inverted="false" name_oen="system_i2c_0_io_sda_OEN"/>
</efxpt:comp_gpio>
<efxpt:comp_gpio name="system_spi_0_io_data_0" gpio_def="GPIOB_N_40" mode="inout" bus_name="" io_standard="1.8 V LVCMOS">
<efxpt:input_config name="system_spi_0_io_data_0_read" name_ddio_lo="" conn_type="normal" is_register="true" clock_name="io_peripheralClk" is_clock_inverted="false" pull_option="none" is_schmitt_trigger="false" ddio_type="none" is_bus_hold="false" delay="0" is_serial="false" is_dyn_delay="false" fastclk_name="" pullup_ena_name="system_spi_0_io_data_0_PULL_UP_ENA" dyn_delay_en_name="system_spi_0_io_data_0_DLY_ENA" dyn_delay_reset_name="system_spi_0_io_data_0_DLY_RST" dyn_delay_ctrl_name="system_spi_0_io_data_0_DLY_CTRL" clkmux_buf_name=""/>
<efxpt:output_config name="system_spi_0_io_data_0_write" name_ddio_lo="" register_option="register" clock_name="io_peripheralClk" is_clock_inverted="false" is_slew_rate="false" tied_option="none" ddio_type="none" delay="0" is_serial="false" drive_strength="4" fastclk_name=""/>
<efxpt:output_enable_config name="system_spi_0_io_data_0_writeEnable" is_register="true" clock_name="io_peripheralClk" is_clock_inverted="false" name_oen="system_spi_0_io_data_0_OEN"/>
</efxpt:comp_gpio>
<efxpt:comp_gpio name="system_spi_0_io_data_1" gpio_def="GPIOB_P_40" mode="inout" bus_name="" io_standard="1.8 V LVCMOS">
<efxpt:input_config name="system_spi_0_io_data_1_read" name_ddio_lo="" conn_type="normal" is_register="true" clock_name="io_peripheralClk" is_clock_inverted="false" pull_option="none" is_schmitt_trigger="false" ddio_type="none" is_bus_hold="false" delay="0" is_serial="false" is_dyn_delay="false" fastclk_name="" pullup_ena_name="system_spi_0_io_data_1_PULL_UP_ENA" dyn_delay_en_name="system_spi_0_io_data_1_DLY_ENA" dyn_delay_reset_name="system_spi_0_io_data_1_DLY_RST" dyn_delay_ctrl_name="system_spi_0_io_data_1_DLY_CTRL" clkmux_buf_name=""/>
<efxpt:output_config name="system_spi_0_io_data_1_write" name_ddio_lo="" register_option="register" clock_name="io_peripheralClk" is_clock_inverted="false" is_slew_rate="false" tied_option="none" ddio_type="none" delay="0" is_serial="false" drive_strength="4" fastclk_name=""/>
<efxpt:output_enable_config name="system_spi_0_io_data_1_writeEnable" is_register="true" clock_name="io_peripheralClk" is_clock_inverted="false" name_oen="system_spi_0_io_data_1_OEN"/>
</efxpt:comp_gpio>
<efxpt:comp_gpio name="system_spi_0_io_sclk_write" gpio_def="GPIOB_P_39" mode="output" bus_name="" io_standard="1.8 V LVCMOS">
<efxpt:output_config name="system_spi_0_io_sclk_write" name_ddio_lo="" register_option="register" clock_name="io_peripheralClk" is_clock_inverted="false" is_slew_rate="false" tied_option="none" ddio_type="none" delay="0" is_serial="false" drive_strength="4" fastclk_name=""/>
</efxpt:comp_gpio>
<efxpt:comp_gpio name="system_spi_0_io_ss" gpio_def="GPIOB_N_38" mode="output" bus_name="" io_standard="1.8 V LVCMOS">
<efxpt:output_config name="system_spi_0_io_ss[0]" name_ddio_lo="" register_option="register" clock_name="io_peripheralClk" is_clock_inverted="false" is_slew_rate="false" tied_option="none" ddio_type="none" delay="0" is_serial="false" drive_strength="4" fastclk_name=""/>
</efxpt:comp_gpio>
<efxpt:comp_gpio name="system_uart_0_io_rxd" gpio_def="GPIOR_145" mode="input" bus_name="" io_standard="3.3 V LVCMOS">
<efxpt:input_config name="system_uart_0_io_rxd" name_ddio_lo="" conn_type="normal" is_register="false" clock_name="" is_clock_inverted="false" pull_option="none" is_schmitt_trigger="false" ddio_type="none" is_bus_hold="false" delay="0" is_serial="false" is_dyn_delay="false" fastclk_name="" pullup_ena_name="system_uart_0_io_rxd_PULL_UP_ENA" dyn_delay_en_name="system_uart_0_io_rxd_DLY_ENA" dyn_delay_reset_name="system_uart_0_io_rxd_DLY_RST" dyn_delay_ctrl_name="system_uart_0_io_rxd_DLY_CTRL" clkmux_buf_name=""/>
</efxpt:comp_gpio>
<efxpt:comp_gpio name="system_uart_0_io_txd" gpio_def="GPIOR_165" mode="output" bus_name="" io_standard="3.3 V LVCMOS">
<efxpt:output_config name="system_uart_0_io_txd" name_ddio_lo="" register_option="none" clock_name="" is_clock_inverted="false" is_slew_rate="false" tied_option="none" ddio_type="none" delay="0" is_serial="false" drive_strength="2" fastclk_name=""/>
</efxpt:comp_gpio>
<efxpt:global_unused_config state="input with weak pullup"/>
<efxpt:bus name="system_gpio_0_io" mode="inout" msb="3" lsb="0"/>
<efxpt:bus name="rgmii_rxd" mode="input" msb="3" lsb="0"/>
<efxpt:bus name="rgmii_txd" mode="output" msb="3" lsb="0"/>
<efxpt:bus name="sd_dat" mode="inout" msb="3" lsb="0"/>
</efxpt:gpio_info>
<efxpt:pll_info>
<efxpt:pll name="soc_pll_sys_clk" pll_def="PLL_BL0" ref_clock_name="" ref_clock_freq="100.0000" multiplier="1" pre_divider="1" post_divider="1" reset_name="" locked_name="pll_system_locked" is_ipfrz="false" is_bypass_lock="true">
<efxpt:adv_prop ref_clock_mode="external" ref_clock1_name="" ext_ref_clock_id="3" clksel_name="" feedback_clock_name="io_sysFbClk" feedback_mode="local"/>
<efxpt:gen_pin>
<efxpt:pin name="" type_name="SHIFT_ENA" is_bus="false"/>
<efxpt:pin name="" type_name="DESKEWED" is_bus="false"/>
<efxpt:pin name="" type_name="CFG_CLK" is_bus="false" is_clk="true" is_clk_invert="false"/>
<efxpt:pin name="" type_name="CFG_DATA_IN" is_bus="false"/>
<efxpt:pin name="" type_name="CFG_DATA_OUT" is_bus="false"/>
<efxpt:pin name="" type_name="CFG_SEL" is_bus="false"/>
<efxpt:pin name="" type_name="USER_SSC_EN" is_bus="false"/>
<efxpt:pin name="" type_name="SHIFT" is_bus="true"/>
<efxpt:pin name="" type_name="SHIFT_SEL" is_bus="true"/>
</efxpt:gen_pin>
<efxpt:comp_output_clock name="io_sysFbClk" number="0" out_divider="40" is_dyn_phase="false" phase_setting="0" is_inverted="false" conn_type="gclk" clkmux_buf_name="">
<efxpt:gen_pin/>
<efxpt:gen_param/>
</efxpt:comp_output_clock>
<efxpt:comp_output_clock name="io_systemClk" number="1" out_divider="4" is_dyn_phase="false" phase_setting="0" is_inverted="false" conn_type="gclk" clkmux_buf_name="">
<efxpt:gen_pin/>
<efxpt:gen_param>
<efxpt:param name="HALF_DC_SHIFT_EN" value="false" value_type="bool"/>
<efxpt:param name="PDIV" value="2" value_type="int"/>
<efxpt:param name="PROG_DUTY_CYCLE_EN" value="false" value_type="bool"/>
<efxpt:param name="REQUEST_DUTY_CYCLE" value="50.0000" value_type="float"/>
<efxpt:param name="SWALLOWING_DIV" value="2" value_type="int"/>
</efxpt:gen_param>
</efxpt:comp_output_clock>
<efxpt:comp_output_clock name="io_memoryClk" number="2" out_divider="16" is_dyn_phase="false" phase_setting="0" is_inverted="false" conn_type="gclk" clkmux_buf_name="">
<efxpt:gen_pin/>
<efxpt:gen_param/>
</efxpt:comp_output_clock>
<efxpt:comp_output_clock name="ddrClk" number="3" out_divider="5" is_dyn_phase="false" phase_setting="0" is_inverted="false" conn_type="gclk" clkmux_buf_name="">
<efxpt:gen_pin/>
<efxpt:gen_param/>
</efxpt:comp_output_clock>
<efxpt:comp_prop/>
<efxpt:gen_param>
<efxpt:param name="DYN_RECONFIG_EN" value="false" value_type="bool"/>
<efxpt:param name="FRACTIONAL_EN" value="false" value_type="bool"/>
<efxpt:param name="FRACTIONAL_K" value="0" value_type="int"/>
<efxpt:param name="REFCLK" value="EXT_CLK1" value_type="str"/>
<efxpt:param name="SSC_AMPLITUDE" value="0.5000" value_type="float"/>
<efxpt:param name="SSC_EN" value="DISABLE" value_type="str"/>
<efxpt:param name="SSC_FREQUENCY" value="30.0000" value_type="float"/>
<efxpt:param name="SSC_MODULATION_TYPE" value="DOWN" value_type="str"/>
</efxpt:gen_param>
</efxpt:pll>
<efxpt:pll name="soc_pll_peri_clk" pll_def="PLL_TR0" ref_clock_name="" ref_clock_freq="25.0000" multiplier="4" pre_divider="1" post_divider="1" reset_name="" locked_name="pll_peripheral_locked" is_ipfrz="false" is_bypass_lock="true">
<efxpt:adv_prop ref_clock_mode="external" ref_clock1_name="" ext_ref_clock_id="2" clksel_name="" feedback_clock_name="io_memFbClk" feedback_mode="local"/>
<efxpt:gen_pin>
<efxpt:pin name="" type_name="SHIFT_ENA" is_bus="false"/>
<efxpt:pin name="" type_name="DESKEWED" is_bus="false"/>
<efxpt:pin name="" type_name="CFG_CLK" is_bus="false" is_clk="true" is_clk_invert="false"/>
<efxpt:pin name="" type_name="CFG_DATA_IN" is_bus="false"/>
<efxpt:pin name="" type_name="CFG_DATA_OUT" is_bus="false"/>
<efxpt:pin name="" type_name="CFG_SEL" is_bus="false"/>
<efxpt:pin name="" type_name="USER_SSC_EN" is_bus="false"/>
<efxpt:pin name="" type_name="SHIFT" is_bus="true"/>
<efxpt:pin name="" type_name="SHIFT_SEL" is_bus="true"/>
</efxpt:gen_pin>
<efxpt:comp_output_clock name="io_memFbClk" number="0" out_divider="40" is_dyn_phase="false" phase_setting="0" is_inverted="false" conn_type="gclk" clkmux_buf_name="">
<efxpt:gen_pin/>
<efxpt:gen_param/>
</efxpt:comp_output_clock>
<efxpt:comp_output_clock name="io_peripheralClk" number="1" out_divider="20" is_dyn_phase="false" phase_setting="0" is_inverted="false" conn_type="gclk" clkmux_buf_name="">
<efxpt:gen_pin/>
<efxpt:gen_param>
<efxpt:param name="HALF_DC_SHIFT_EN" value="false" value_type="bool"/>
<efxpt:param name="PDIV" value="10" value_type="int"/>
<efxpt:param name="PROG_DUTY_CYCLE_EN" value="false" value_type="bool"/>
<efxpt:param name="REQUEST_DUTY_CYCLE" value="50.0000" value_type="float"/>
<efxpt:param name="SWALLOWING_DIV" value="10" value_type="int"/>
</efxpt:gen_param>
</efxpt:comp_output_clock>
<efxpt:comp_output_clock name="io_ddrMasters_0_clk" number="2" out_divider="16" is_dyn_phase="false" phase_setting="0" is_inverted="false" conn_type="gclk" clkmux_buf_name="">
<efxpt:gen_pin/>
<efxpt:gen_param/>
</efxpt:comp_output_clock>
<efxpt:comp_output_clock name="io_cfuClk" number="3" out_divider="32" is_dyn_phase="false" phase_setting="0" is_inverted="false" conn_type="gclk" clkmux_buf_name="">
<efxpt:gen_pin/>
<efxpt:gen_param/>
</efxpt:comp_output_clock>
<efxpt:comp_output_clock name="sd_base_clk" number="4" out_divider="40" is_dyn_phase="false" phase_setting="0" is_inverted="false" conn_type="gclk" clkmux_buf_name="">
<efxpt:gen_pin/>
<efxpt:gen_param/>
</efxpt:comp_output_clock>
<efxpt:comp_prop/>
<efxpt:gen_param>
<efxpt:param name="DYN_RECONFIG_EN" value="false" value_type="bool"/>
<efxpt:param name="FRACTIONAL_EN" value="false" value_type="bool"/>
<efxpt:param name="FRACTIONAL_K" value="0" value_type="int"/>
<efxpt:param name="REFCLK" value="EXT_CLK0" value_type="str"/>
<efxpt:param name="SSC_AMPLITUDE" value="0.5000" value_type="float"/>
<efxpt:param name="SSC_EN" value="DISABLE" value_type="str"/>
<efxpt:param name="SSC_FREQUENCY" value="30.0000" value_type="float"/>
<efxpt:param name="SSC_MODULATION_TYPE" value="DOWN" value_type="str"/>
</efxpt:gen_param>
</efxpt:pll>
<efxpt:pll name="tse_pll_clk" pll_def="PLL_BL2" ref_clock_name="rgmii_rxc_phy" ref_clock_freq="125.0000" multiplier="1" pre_divider="1" post_divider="4" reset_name="" locked_name="pll_tse_locked" is_ipfrz="false" is_bypass_lock="true">
<efxpt:adv_prop ref_clock_mode="core" ref_clock1_name="" ext_ref_clock_id="2" clksel_name="" feedback_clock_name="tse_pll_clk_CLKOUT0" feedback_mode="local"/>
<efxpt:gen_pin>
<efxpt:pin name="" type_name="SHIFT_ENA" is_bus="false"/>
<efxpt:pin name="" type_name="DESKEWED" is_bus="false"/>
<efxpt:pin name="" type_name="CFG_CLK" is_bus="false" is_clk="true" is_clk_invert="false"/>
<efxpt:pin name="" type_name="CFG_DATA_IN" is_bus="false"/>
<efxpt:pin name="" type_name="CFG_DATA_OUT" is_bus="false"/>
<efxpt:pin name="" type_name="CFG_SEL" is_bus="false"/>
<efxpt:pin name="" type_name="USER_SSC_EN" is_bus="false"/>
<efxpt:pin name="" type_name="SHIFT" is_bus="true"/>
<efxpt:pin name="" type_name="SHIFT_SEL" is_bus="true"/>
</efxpt:gen_pin>
<efxpt:comp_output_clock name="tse_pll_clk_CLKOUT0" number="0" out_divider="10" is_dyn_phase="false" phase_setting="0" is_inverted="false" conn_type="gclk" clkmux_buf_name="">
<efxpt:gen_pin/>
<efxpt:gen_param/>
</efxpt:comp_output_clock>
<efxpt:comp_output_clock name="rgmii_rxc" number="1" out_divider="10" is_dyn_phase="false" phase_setting="0" is_inverted="false" conn_type="gclk" clkmux_buf_name="">
<efxpt:gen_pin/>
<efxpt:gen_param>
<efxpt:param name="HALF_DC_SHIFT_EN" value="false" value_type="bool"/>
<efxpt:param name="PDIV" value="5" value_type="int"/>
<efxpt:param name="PROG_DUTY_CYCLE_EN" value="false" value_type="bool"/>
<efxpt:param name="REQUEST_DUTY_CYCLE" value="50.0000" value_type="float"/>
<efxpt:param name="SWALLOWING_DIV" value="5" value_type="int"/>
</efxpt:gen_param>
</efxpt:comp_output_clock>
<efxpt:comp_output_clock name="io_tseClk_90" number="2" out_divider="10" is_dyn_phase="false" phase_setting="5" is_inverted="false" conn_type="gclk" clkmux_buf_name="">
<efxpt:gen_pin/>
<efxpt:gen_param/>
</efxpt:comp_output_clock>
<efxpt:comp_output_clock name="io_tseClk" number="3" out_divider="10" is_dyn_phase="false" phase_setting="0" is_inverted="false" conn_type="gclk" clkmux_buf_name="">
<efxpt:gen_pin/>
<efxpt:gen_param/>
</efxpt:comp_output_clock>
<efxpt:comp_prop/>
<efxpt:gen_param>
<efxpt:param name="DYN_RECONFIG_EN" value="false" value_type="bool"/>
<efxpt:param name="FRACTIONAL_EN" value="false" value_type="bool"/>
<efxpt:param name="FRACTIONAL_K" value="0" value_type="int"/>
<efxpt:param name="REFCLK" value="CORE_CLK1" value_type="str"/>
<efxpt:param name="SSC_AMPLITUDE" value="0.5000" value_type="float"/>
<efxpt:param name="SSC_EN" value="DISABLE" value_type="str"/>
<efxpt:param name="SSC_FREQUENCY" value="30.0000" value_type="float"/>
<efxpt:param name="SSC_MODULATION_TYPE" value="DOWN" value_type="str"/>
</efxpt:gen_param>
</efxpt:pll>
</efxpt:pll_info>
<efxpt:osc_info/>
<efxpt:lvds_info/>
<efxpt:jtag_info>
<efxpt:jtag name="soc_jtag_inst1" jtag_def="JTAG_USER1">
<efxpt:gen_pin>
<efxpt:pin name="ut_jtagCtrl_capture" type_name="CAPTURE" is_bus="false"/>
<efxpt:pin name="" type_name="DRCK" is_bus="false"/>
<efxpt:pin name="ut_jtagCtrl_reset" type_name="RESET" is_bus="false"/>
<efxpt:pin name="" type_name="RUNTEST" is_bus="false"/>
<efxpt:pin name="ut_jtagCtrl_enable" type_name="SEL" is_bus="false"/>
<efxpt:pin name="ut_jtagCtrl_shift" type_name="SHIFT" is_bus="false"/>
<efxpt:pin name="jtagCtrl_tck" type_name="TCK" is_bus="false"/>
<efxpt:pin name="ut_jtagCtrl_tdi" type_name="TDI" is_bus="false"/>
<efxpt:pin name="" type_name="TMS" is_bus="false"/>
<efxpt:pin name="ut_jtagCtrl_update" type_name="UPDATE" is_bus="false"/>
<efxpt:pin name="ut_jtagCtrl_tdo" type_name="TDO" is_bus="false"/>
</efxpt:gen_pin>
</efxpt:jtag>
</efxpt:jtag_info>
<efxpt:ddr_info>
<efxpt:adv_ddr name="soc_ddr_inst1" ddr_def="DDR_0" clkin_sel="0" data_width="32" physical_rank="1" mem_type="LPDDR4x" mem_density="8G">
<efxpt:axi_target0 is_axi_width_256="false" is_axi_enable="false">
<efxpt:gen_pin_axi>
<efxpt:pin name="" type_name="ACLK_0" is_bus="false" is_clk="true" is_clk_invert="false"/>
<efxpt:pin name="" type_name="ARSTN_0" is_bus="false"/>
<efxpt:pin name="" type_name="ARAPCMD_0" is_bus="false"/>
<efxpt:pin name="" type_name="ARREADY_0" is_bus="false"/>
<efxpt:pin name="" type_name="ARVALID_0" is_bus="false"/>
<efxpt:pin name="" type_name="ARLOCK_0" is_bus="false"/>
<efxpt:pin name="" type_name="ARQOS_0" is_bus="false"/>
<efxpt:pin name="" type_name="AWAPCMD_0" is_bus="false"/>
<efxpt:pin name="" type_name="AWALLSTRB_0" is_bus="false"/>
<efxpt:pin name="" type_name="AWCOBUF_0" is_bus="false"/>
<efxpt:pin name="" type_name="AWREADY_0" is_bus="false"/>
<efxpt:pin name="" type_name="AWVALID_0" is_bus="false"/>
<efxpt:pin name="" type_name="AWLOCK_0" is_bus="false"/>
<efxpt:pin name="" type_name="AWQOS_0" is_bus="false"/>
<efxpt:pin name="" type_name="BREADY_0" is_bus="false"/>
<efxpt:pin name="" type_name="BVALID_0" is_bus="false"/>
<efxpt:pin name="" type_name="RLAST_0" is_bus="false"/>
<efxpt:pin name="" type_name="RREADY_0" is_bus="false"/>
<efxpt:pin name="" type_name="RVALID_0" is_bus="false"/>
<efxpt:pin name="" type_name="WLAST_0" is_bus="false"/>
<efxpt:pin name="" type_name="WREADY_0" is_bus="false"/>
<efxpt:pin name="" type_name="WVALID_0" is_bus="false"/>
<efxpt:pin name="" type_name="ARADDR_0" is_bus="true"/>
<efxpt:pin name="" type_name="ARBURST_0" is_bus="true"/>
<efxpt:pin name="" type_name="ARID_0" is_bus="true"/>
<efxpt:pin name="" type_name="ARLEN_0" is_bus="true"/>
<efxpt:pin name="" type_name="ARSIZE_0" is_bus="true"/>
<efxpt:pin name="" type_name="AWADDR_0" is_bus="true"/>
<efxpt:pin name="" type_name="AWBURST_0" is_bus="true"/>
<efxpt:pin name="" type_name="AWID_0" is_bus="true"/>
<efxpt:pin name="" type_name="AWLEN_0" is_bus="true"/>
<efxpt:pin name="" type_name="AWSIZE_0" is_bus="true"/>
<efxpt:pin name="" type_name="AWCACHE_0" is_bus="true"/>
<efxpt:pin name="" type_name="BID_0" is_bus="true"/>
<efxpt:pin name="" type_name="BRESP_0" is_bus="true"/>
<efxpt:pin name="" type_name="RDATA_0" is_bus="true"/>
<efxpt:pin name="" type_name="RID_0" is_bus="true"/>
<efxpt:pin name="" type_name="RRESP_0" is_bus="true"/>
<efxpt:pin name="" type_name="WDATA_0" is_bus="true"/>
<efxpt:pin name="" type_name="WSTRB_0" is_bus="true"/>
</efxpt:gen_pin_axi>
</efxpt:axi_target0>
<efxpt:axi_target1 is_axi_width_256="false" is_axi_enable="false">
<efxpt:gen_pin_axi>
<efxpt:pin name="" type_name="ACLK_1" is_bus="false" is_clk="true" is_clk_invert="false"/>
<efxpt:pin name="" type_name="ARSTN_1" is_bus="false"/>
<efxpt:pin name="" type_name="ARAPCMD_1" is_bus="false"/>
<efxpt:pin name="" type_name="ARREADY_1" is_bus="false"/>
<efxpt:pin name="" type_name="ARVALID_1" is_bus="false"/>
<efxpt:pin name="" type_name="ARLOCK_1" is_bus="false"/>
<efxpt:pin name="" type_name="ARQOS_1" is_bus="false"/>
<efxpt:pin name="" type_name="AWAPCMD_1" is_bus="false"/>
<efxpt:pin name="" type_name="AWALLSTRB_1" is_bus="false"/>
<efxpt:pin name="" type_name="AWCOBUF_1" is_bus="false"/>
<efxpt:pin name="" type_name="AWREADY_1" is_bus="false"/>
<efxpt:pin name="" type_name="AWVALID_1" is_bus="false"/>
<efxpt:pin name="" type_name="AWLOCK_1" is_bus="false"/>
<efxpt:pin name="" type_name="AWQOS_1" is_bus="false"/>
<efxpt:pin name="" type_name="BREADY_1" is_bus="false"/>
<efxpt:pin name="" type_name="BVALID_1" is_bus="false"/>
<efxpt:pin name="" type_name="RLAST_1" is_bus="false"/>
<efxpt:pin name="" type_name="RREADY_1" is_bus="false"/>
<efxpt:pin name="" type_name="RVALID_1" is_bus="false"/>
<efxpt:pin name="" type_name="WLAST_1" is_bus="false"/>
<efxpt:pin name="" type_name="WREADY_1" is_bus="false"/>
<efxpt:pin name="" type_name="WVALID_1" is_bus="false"/>
<efxpt:pin name="" type_name="ARADDR_1" is_bus="true"/>
<efxpt:pin name="" type_name="ARBURST_1" is_bus="true"/>
<efxpt:pin name="" type_name="ARID_1" is_bus="true"/>
<efxpt:pin name="" type_name="ARLEN_1" is_bus="true"/>
<efxpt:pin name="" type_name="ARSIZE_1" is_bus="true"/>
<efxpt:pin name="" type_name="AWADDR_1" is_bus="true"/>
<efxpt:pin name="" type_name="AWBURST_1" is_bus="true"/>
<efxpt:pin name="" type_name="AWID_1" is_bus="true"/>
<efxpt:pin name="" type_name="AWLEN_1" is_bus="true"/>
<efxpt:pin name="" type_name="AWSIZE_1" is_bus="true"/>
<efxpt:pin name="" type_name="AWCACHE_1" is_bus="true"/>
<efxpt:pin name="" type_name="BID_1" is_bus="true"/>
<efxpt:pin name="" type_name="BRESP_1" is_bus="true"/>
<efxpt:pin name="" type_name="RDATA_1" is_bus="true"/>
<efxpt:pin name="" type_name="RID_1" is_bus="true"/>
<efxpt:pin name="" type_name="RRESP_1" is_bus="true"/>
<efxpt:pin name="" type_name="WDATA_1" is_bus="true"/>
<efxpt:pin name="" type_name="WSTRB_1" is_bus="true"/>
</efxpt:gen_pin_axi>
</efxpt:axi_target1>
<efxpt:gen_pin_controller>
<efxpt:pin name="io_sysFbClk" type_name="CTRL_CLK" is_bus="false" is_clk="true" is_clk_invert="false"/>
<efxpt:pin name="soc_ddr_inst1_CTRL_INT" type_name="CTRL_INT" is_bus="false"/>
<efxpt:pin name="soc_ddr_inst1_CTRL_MEM_RST_VALID" type_name="CTRL_MEM_RST_VALID" is_bus="false"/>
<efxpt:pin name="soc_ddr_inst1_CTRL_REFRESH" type_name="CTRL_REFRESH" is_bus="false"/>
<efxpt:pin name="soc_ddr_inst1_CTRL_BUSY" type_name="CTRL_BUSY" is_bus="false"/>
<efxpt:pin name="soc_ddr_inst1_CTRL_CMD_Q_ALMOST_FULL" type_name="CTRL_CMD_Q_ALMOST_FULL" is_bus="false"/>
<efxpt:pin name="soc_ddr_inst1_CTRL_DP_IDLE" type_name="CTRL_DP_IDLE" is_bus="false"/>
<efxpt:pin name="soc_ddr_inst1_CTRL_CKE" type_name="CTRL_CKE" is_bus="true"/>
<efxpt:pin name="soc_ddr_inst1_CTRL_PORT_BUSY" type_name="CTRL_PORT_BUSY" is_bus="true"/>
</efxpt:gen_pin_controller>
<efxpt:gen_pin_cfg_ctrl>
<efxpt:pin name="cfg_done" type_name="CFG_DONE" is_bus="false"/>
<efxpt:pin name="cfg_start" type_name="CFG_START" is_bus="false"/>
<efxpt:pin name="cfg_reset" type_name="CFG_RESET" is_bus="false"/>
<efxpt:pin name="cfg_sel" type_name="CFG_SEL" is_bus="false"/>
</efxpt:gen_pin_cfg_ctrl>
<efxpt:ctrl_reg_inf is_reg_ena="false">
<efxpt:gen_pin_ctrl_reg_inf>
<efxpt:pin name="" type_name="CR_ACLK" is_bus="false" is_clk="true" is_clk_invert="false"/>
<efxpt:pin name="soc_ddr_inst1_CR_ARESETN" type_name="CR_ARESETN" is_bus="false"/>
<efxpt:pin name="soc_ddr_inst1_CR_ARVALID" type_name="CR_ARVALID" is_bus="false"/>
<efxpt:pin name="soc_ddr_inst1_CR_ARREADY" type_name="CR_ARREADY" is_bus="false"/>
<efxpt:pin name="soc_ddr_inst1_CR_AWVALID" type_name="CR_AWVALID" is_bus="false"/>
<efxpt:pin name="soc_ddr_inst1_CR_AWREADY" type_name="CR_AWREADY" is_bus="false"/>
<efxpt:pin name="soc_ddr_inst1_CR_BVALID" type_name="CR_BVALID" is_bus="false"/>
<efxpt:pin name="soc_ddr_inst1_CR_BREADY" type_name="CR_BREADY" is_bus="false"/>
<efxpt:pin name="soc_ddr_inst1_CR_RLAST" type_name="CR_RLAST" is_bus="false"/>
<efxpt:pin name="soc_ddr_inst1_CR_RVALID" type_name="CR_RVALID" is_bus="false"/>
<efxpt:pin name="soc_ddr_inst1_CR_RREADY" type_name="CR_RREADY" is_bus="false"/>
<efxpt:pin name="soc_ddr_inst1_CR_WLAST" type_name="CR_WLAST" is_bus="false"/>
<efxpt:pin name="soc_ddr_inst1_CR_WVALID" type_name="CR_WVALID" is_bus="false"/>
<efxpt:pin name="soc_ddr_inst1_CR_WREADY" type_name="CR_WREADY" is_bus="false"/>
<efxpt:pin name="soc_ddr_inst1_CFG_PHY_RSTN" type_name="CFG_PHY_RSTN" is_bus="false"/>
<efxpt:pin name="soc_ddr_inst1_CTRL_RSTN" type_name="CTRL_RSTN" is_bus="false"/>
<efxpt:pin name="soc_ddr_inst1_CR_ARADDR" type_name="CR_ARADDR" is_bus="true"/>
<efxpt:pin name="soc_ddr_inst1_CR_ARID" type_name="CR_ARID" is_bus="true"/>
<efxpt:pin name="soc_ddr_inst1_CR_ARLEN" type_name="CR_ARLEN" is_bus="true"/>
<efxpt:pin name="soc_ddr_inst1_CR_ARSIZE" type_name="CR_ARSIZE" is_bus="true"/>
<efxpt:pin name="soc_ddr_inst1_CR_ARBURST" type_name="CR_ARBURST" is_bus="true"/>
<efxpt:pin name="soc_ddr_inst1_CR_AWADDR" type_name="CR_AWADDR" is_bus="true"/>
<efxpt:pin name="soc_ddr_inst1_CR_AWID" type_name="CR_AWID" is_bus="true"/>
<efxpt:pin name="soc_ddr_inst1_CR_AWLEN" type_name="CR_AWLEN" is_bus="true"/>
<efxpt:pin name="soc_ddr_inst1_CR_AWSIZE" type_name="CR_AWSIZE" is_bus="true"/>
<efxpt:pin name="soc_ddr_inst1_CR_AWBURST" type_name="CR_AWBURST" is_bus="true"/>
<efxpt:pin name="soc_ddr_inst1_CR_BID" type_name="CR_BID" is_bus="true"/>
<efxpt:pin name="soc_ddr_inst1_CR_BRESP" type_name="CR_BRESP" is_bus="true"/>
<efxpt:pin name="soc_ddr_inst1_CR_RDATA" type_name="CR_RDATA" is_bus="true"/>
<efxpt:pin name="soc_ddr_inst1_CR_RID" type_name="CR_RID" is_bus="true"/>
<efxpt:pin name="soc_ddr_inst1_CR_RRESP" type_name="CR_RRESP" is_bus="true"/>
<efxpt:pin name="soc_ddr_inst1_CR_WDATA" type_name="CR_WDATA" is_bus="true"/>
<efxpt:pin name="soc_ddr_inst1_CR_WSTRB" type_name="CR_WSTRB" is_bus="true"/>
</efxpt:gen_pin_ctrl_reg_inf>
</efxpt:ctrl_reg_inf>
<efxpt:cs_fpga>
<efxpt:param name="DQ_PULLDOWN_DRV" value="34.3" value_type="str"/>
<efxpt:param name="DQ_PULLDOWN_ODT" value="60" value_type="str"/>
<efxpt:param name="DQ_PULLUP_DRV" value="34.3" value_type="str"/>
<efxpt:param name="DQ_PULLUP_ODT" value="Hi-Z" value_type="str"/>
<efxpt:param name="FPGA_VREF_RANGE0" value="20.300" value_type="float"/>
<efxpt:param name="FPGA_VREF_RANGE1" value="23.000" value_type="float"/>
<efxpt:param name="LP_AUTO_MODE" value="Disable" value_type="str"/>
<efxpt:param name="MEM_FPGA_VREF_RANGE" value="Range 1" value_type="str"/>
</efxpt:cs_fpga>
<efxpt:cs_memory>
<efxpt:param name="BLEN" value="BL=16 Sequential" value_type="str"/>
<efxpt:param name="CA_ODT_CS0" value="RZQ/4" value_type="str"/>
<efxpt:param name="CA_ODT_CS1" value="RZQ/6" value_type="str"/>
<efxpt:param name="CA_VREF_RANGE0" value="22.000" value_type="float"/>
<efxpt:param name="CA_VREF_RANGE1" value="22.000" value_type="float"/>
<efxpt:param name="DQ_ODT_CS0" value="RZQ/4" value_type="str"/>
<efxpt:param name="DQ_ODT_CS1" value="RZQ/4" value_type="str"/>
<efxpt:param name="DQ_VREF_RANGE0" value="20.000" value_type="float"/>
<efxpt:param name="DQ_VREF_RANGE1" value="27.200" value_type="float"/>
<efxpt:param name="MEM_CA_RANGE" value="RANGE[1]" value_type="str"/>
<efxpt:param name="MEM_DQ_RANGE" value="RANGE[1]" value_type="str"/>
<efxpt:param name="NWR" value="nWR=6" value_type="str"/>
<efxpt:param name="ODTD_CA_CS0" value="Obeys ODT_CA Bond Pad" value_type="str"/>
<efxpt:param name="ODTD_CA_CS1" value="Obeys ODT_CA Bond Pad" value_type="str"/>
<efxpt:param name="ODTE_CK_CS0" value="Override Disabled" value_type="str"/>
<efxpt:param name="ODTE_CK_CS1" value="Override Disabled" value_type="str"/>
<efxpt:param name="ODTE_CS_CS0" value="Override Disabled" value_type="str"/>
<efxpt:param name="ODTE_CS_CS1" value="Override Disabled" value_type="str"/>
<efxpt:param name="PDDS_CS0" value="RZQ/6" value_type="str"/>
<efxpt:param name="PDDS_CS1" value="RZQ/6" value_type="str"/>
<efxpt:param name="RL_DBI_READ" value="Yes" value_type="str"/>
<efxpt:param name="RL_DBI_READ_DISABLED" value="RL=6,nRTP=8" value_type="str"/>
<efxpt:param name="RL_DBI_READ_ENABLED" value="RL=6,nRTP=8" value_type="str"/>
<efxpt:param name="RL_DBI_WRITE" value="Yes" value_type="str"/>
<efxpt:param name="WL_SET" value="Set A" value_type="str"/>
<efxpt:param name="WL_SET_A" value="WL=4" value_type="str"/>
<efxpt:param name="WL_SET_B" value="WL=4" value_type="str"/>
</efxpt:cs_memory>
<efxpt:cs_memory_timing>
<efxpt:param name="tCCD" value="8" value_type="int"/>
<efxpt:param name="tCCDMW" value="32" value_type="int"/>
<efxpt:param name="tFAW" value="40.000" value_type="float"/>
<efxpt:param name="tPPD" value="4" value_type="int"/>
<efxpt:param name="tRAS" value="42.000" value_type="float"/>
<efxpt:param name="tRCD" value="18.000" value_type="float"/>
<efxpt:param name="tRPab" value="21.000" value_type="float"/>
<efxpt:param name="tRPpb" value="18.000" value_type="float"/>
<efxpt:param name="tRRD" value="10.000" value_type="float"/>
<efxpt:param name="tRTP" value="7.500" value_type="float"/>
<efxpt:param name="tSR" value="15.000" value_type="float"/>
<efxpt:param name="tWR" value="18.000" value_type="float"/>
<efxpt:param name="tWTR" value="10.000" value_type="float"/>
</efxpt:cs_memory_timing>
<efxpt:pin_swap>
<efxpt:param name="CA[0]" value="CA[0]" value_type="str"/>
<efxpt:param name="CA[1]" value="CA[1]" value_type="str"/>
<efxpt:param name="CA[2]" value="CA[2]" value_type="str"/>
<efxpt:param name="CA[3]" value="CA[3]" value_type="str"/>
<efxpt:param name="CA[4]" value="CA[4]" value_type="str"/>
<efxpt:param name="CA[5]" value="CA[5]" value_type="str"/>
<efxpt:param name="DM[0]" value="DM[0]" value_type="str"/>
<efxpt:param name="DM[1]" value="DM[1]" value_type="str"/>
<efxpt:param name="DM[2]" value="DM[2]" value_type="str"/>
<efxpt:param name="DM[3]" value="DM[3]" value_type="str"/>
<efxpt:param name="DQ[0]" value="DQ[3]" value_type="str"/>
<efxpt:param name="DQ[10]" value="DQ[12]" value_type="str"/>
<efxpt:param name="DQ[11]" value="DQ[11]" value_type="str"/>
<efxpt:param name="DQ[12]" value="DQ[8]" value_type="str"/>
<efxpt:param name="DQ[13]" value="DQ[10]" value_type="str"/>
<efxpt:param name="DQ[14]" value="DQ[13]" value_type="str"/>
<efxpt:param name="DQ[15]" value="DQ[14]" value_type="str"/>
<efxpt:param name="DQ[16]" value="DQ[22]" value_type="str"/>
<efxpt:param name="DQ[17]" value="DQ[17]" value_type="str"/>
<efxpt:param name="DQ[18]" value="DQ[18]" value_type="str"/>
<efxpt:param name="DQ[19]" value="DQ[19]" value_type="str"/>
<efxpt:param name="DQ[1]" value="DQ[6]" value_type="str"/>
<efxpt:param name="DQ[20]" value="DQ[16]" value_type="str"/>
<efxpt:param name="DQ[21]" value="DQ[20]" value_type="str"/>
<efxpt:param name="DQ[22]" value="DQ[21]" value_type="str"/>
<efxpt:param name="DQ[23]" value="DQ[23]" value_type="str"/>
<efxpt:param name="DQ[24]" value="DQ[29]" value_type="str"/>
<efxpt:param name="DQ[25]" value="DQ[31]" value_type="str"/>
<efxpt:param name="DQ[26]" value="DQ[28]" value_type="str"/>
<efxpt:param name="DQ[27]" value="DQ[30]" value_type="str"/>
<efxpt:param name="DQ[28]" value="DQ[25]" value_type="str"/>
<efxpt:param name="DQ[29]" value="DQ[27]" value_type="str"/>
<efxpt:param name="DQ[2]" value="DQ[4]" value_type="str"/>
<efxpt:param name="DQ[30]" value="DQ[26]" value_type="str"/>
<efxpt:param name="DQ[31]" value="DQ[24]" value_type="str"/>
<efxpt:param name="DQ[3]" value="DQ[5]" value_type="str"/>
<efxpt:param name="DQ[4]" value="DQ[0]" value_type="str"/>
<efxpt:param name="DQ[5]" value="DQ[1]" value_type="str"/>
<efxpt:param name="DQ[6]" value="DQ[7]" value_type="str"/>
<efxpt:param name="DQ[7]" value="DQ[2]" value_type="str"/>
<efxpt:param name="DQ[8]" value="DQ[15]" value_type="str"/>
<efxpt:param name="DQ[9]" value="DQ[9]" value_type="str"/>
<efxpt:param name="ENABLE_PIN_SWAP" value="true" value_type="bool"/>
</efxpt:pin_swap>
</efxpt:adv_ddr>
</efxpt:ddr_info>
<efxpt:mipi_dphy_info/>
<efxpt:soc_info>
<efxpt:soc name="qcrv32_inst1" block_def="SOC_0">
<efxpt:gen_param>
<efxpt:param name="AXI_MASTER_EN" value="true" value_type="bool"/>
<efxpt:param name="AXI_SLAVE_EN" value="true" value_type="bool"/>
<efxpt:param name="CUSTOM_INSTRUCTION_0_EN" value="true" value_type="bool"/>
<efxpt:param name="CUSTOM_INSTRUCTION_1_EN" value="true" value_type="bool"/>
<efxpt:param name="CUSTOM_INSTRUCTION_2_EN" value="true" value_type="bool"/>
<efxpt:param name="CUSTOM_INSTRUCTION_3_EN" value="true" value_type="bool"/>
<efxpt:param name="JTAG_TYPE" value="FPGA" value_type="str"/>
<efxpt:param name="MEM_CLK_SOURCE" value="Clock 0" value_type="str"/>
<efxpt:param name="OCR_FILE_PATH" value="EfxSapphireHpSoc_bootloader/default_bootloader.hex" value_type="str"/>
<efxpt:param name="PIPELINE_SOC_AXI_MEM_INTERFACE_EN" value="false" value_type="bool"/>
<efxpt:param name="SYS_CLK_SOURCE" value="Clock 0" value_type="str"/>
<efxpt:param name="WRITEBUFFER_SOC_AXI_INTERFACE_EN" value="false" value_type="bool"/>
</efxpt:gen_param>
<efxpt:gen_pin>
<efxpt:pin name="axiAInterrupt" type_name="AXIAINTERRUPT" is_bus="false"/>
<efxpt:pin name="axiA_araddr" type_name="AXIA_ARADDR" is_bus="true"/>
<efxpt:pin name="axiA_arburst" type_name="AXIA_ARBURST" is_bus="true"/>
<efxpt:pin name="axiA_arcache" type_name="AXIA_ARCACHE" is_bus="true"/>
<efxpt:pin name="axiA_arlen" type_name="AXIA_ARLEN" is_bus="true"/>
<efxpt:pin name="axiA_arlock" type_name="AXIA_ARLOCK" is_bus="false"/>
<efxpt:pin name="axiA_arprot" type_name="AXIA_ARPROT" is_bus="true"/>
<efxpt:pin name="axiA_arqos" type_name="AXIA_ARQOS" is_bus="true"/>
<efxpt:pin name="axiA_arready" type_name="AXIA_ARREADY" is_bus="false"/>
<efxpt:pin name="axiA_arregion" type_name="AXIA_ARREGION" is_bus="true"/>
<efxpt:pin name="axiA_arsize" type_name="AXIA_ARSIZE" is_bus="true"/>
<efxpt:pin name="axiA_arvalid" type_name="AXIA_ARVALID" is_bus="false"/>
<efxpt:pin name="axiA_awaddr" type_name="AXIA_AWADDR" is_bus="true"/>
<efxpt:pin name="axiA_awburst" type_name="AXIA_AWBURST" is_bus="true"/>
<efxpt:pin name="axiA_awcache" type_name="AXIA_AWCACHE" is_bus="true"/>
<efxpt:pin name="axiA_awlen" type_name="AXIA_AWLEN" is_bus="true"/>
<efxpt:pin name="axiA_awlock" type_name="AXIA_AWLOCK" is_bus="false"/>
<efxpt:pin name="axiA_awprot" type_name="AXIA_AWPROT" is_bus="true"/>
<efxpt:pin name="axiA_awqos" type_name="AXIA_AWQOS" is_bus="true"/>
<efxpt:pin name="axiA_awready" type_name="AXIA_AWREADY" is_bus="false"/>
<efxpt:pin name="axiA_awregion" type_name="AXIA_AWREGION" is_bus="true"/>
<efxpt:pin name="axiA_awsize" type_name="AXIA_AWSIZE" is_bus="true"/>
<efxpt:pin name="axiA_awvalid" type_name="AXIA_AWVALID" is_bus="false"/>
<efxpt:pin name="axiA_bready" type_name="AXIA_BREADY" is_bus="false"/>
<efxpt:pin name="axiA_bresp" type_name="AXIA_BRESP" is_bus="true"/>
<efxpt:pin name="axiA_bvalid" type_name="AXIA_BVALID" is_bus="false"/>
<efxpt:pin name="axiA_rdata" type_name="AXIA_RDATA" is_bus="true"/>
<efxpt:pin name="axiA_rlast" type_name="AXIA_RLAST" is_bus="false"/>
<efxpt:pin name="axiA_rready" type_name="AXIA_RREADY" is_bus="false"/>
<efxpt:pin name="axiA_rresp" type_name="AXIA_RRESP" is_bus="true"/>
<efxpt:pin name="axiA_rvalid" type_name="AXIA_RVALID" is_bus="false"/>
<efxpt:pin name="axiA_wdata" type_name="AXIA_WDATA" is_bus="true"/>
<efxpt:pin name="axiA_wlast" type_name="AXIA_WLAST" is_bus="false"/>
<efxpt:pin name="axiA_wready" type_name="AXIA_WREADY" is_bus="false"/>
<efxpt:pin name="axiA_wstrb" type_name="AXIA_WSTRB" is_bus="true"/>
<efxpt:pin name="axiA_wvalid" type_name="AXIA_WVALID" is_bus="false"/>
<efxpt:pin name="cpu0_customInstruction_cmd_ready" type_name="CPU0_CUSTOMINSTRUCTION_CMD_READY" is_bus="false"/>
<efxpt:pin name="cpu0_customInstruction_cmd_valid" type_name="CPU0_CUSTOMINSTRUCTION_CMD_VALID" is_bus="false"/>
<efxpt:pin name="cpu0_customInstruction_function_id" type_name="CPU0_CUSTOMINSTRUCTION_FUNCTION_ID" is_bus="true"/>
<efxpt:pin name="cpu0_customInstruction_inputs_0" type_name="CPU0_CUSTOMINSTRUCTION_INPUTS_0" is_bus="true"/>
<efxpt:pin name="cpu0_customInstruction_inputs_1" type_name="CPU0_CUSTOMINSTRUCTION_INPUTS_1" is_bus="true"/>
<efxpt:pin name="cpu0_customInstruction_outputs_0" type_name="CPU0_CUSTOMINSTRUCTION_OUTPUTS_0" is_bus="true"/>
<efxpt:pin name="cpu0_customInstruction_rsp_ready" type_name="CPU0_CUSTOMINSTRUCTION_RSP_READY" is_bus="false"/>
<efxpt:pin name="cpu0_customInstruction_rsp_valid" type_name="CPU0_CUSTOMINSTRUCTION_RSP_VALID" is_bus="false"/>
<efxpt:pin name="cpu1_customInstruction_cmd_ready" type_name="CPU1_CUSTOMINSTRUCTION_CMD_READY" is_bus="false"/>
<efxpt:pin name="cpu1_customInstruction_cmd_valid" type_name="CPU1_CUSTOMINSTRUCTION_CMD_VALID" is_bus="false"/>
<efxpt:pin name="cpu1_customInstruction_function_id" type_name="CPU1_CUSTOMINSTRUCTION_FUNCTION_ID" is_bus="true"/>
<efxpt:pin name="cpu1_customInstruction_inputs_0" type_name="CPU1_CUSTOMINSTRUCTION_INPUTS_0" is_bus="true"/>
<efxpt:pin name="cpu1_customInstruction_inputs_1" type_name="CPU1_CUSTOMINSTRUCTION_INPUTS_1" is_bus="true"/>
<efxpt:pin name="cpu1_customInstruction_outputs_0" type_name="CPU1_CUSTOMINSTRUCTION_OUTPUTS_0" is_bus="true"/>
<efxpt:pin name="cpu1_customInstruction_rsp_ready" type_name="CPU1_CUSTOMINSTRUCTION_RSP_READY" is_bus="false"/>
<efxpt:pin name="cpu1_customInstruction_rsp_valid" type_name="CPU1_CUSTOMINSTRUCTION_RSP_VALID" is_bus="false"/>
<efxpt:pin name="cpu2_customInstruction_cmd_ready" type_name="CPU2_CUSTOMINSTRUCTION_CMD_READY" is_bus="false"/>
<efxpt:pin name="cpu2_customInstruction_cmd_valid" type_name="CPU2_CUSTOMINSTRUCTION_CMD_VALID" is_bus="false"/>
<efxpt:pin name="cpu2_customInstruction_function_id" type_name="CPU2_CUSTOMINSTRUCTION_FUNCTION_ID" is_bus="true"/>
<efxpt:pin name="cpu2_customInstruction_inputs_0" type_name="CPU2_CUSTOMINSTRUCTION_INPUTS_0" is_bus="true"/>
<efxpt:pin name="cpu2_customInstruction_inputs_1" type_name="CPU2_CUSTOMINSTRUCTION_INPUTS_1" is_bus="true"/>
<efxpt:pin name="cpu2_customInstruction_outputs_0" type_name="CPU2_CUSTOMINSTRUCTION_OUTPUTS_0" is_bus="true"/>
<efxpt:pin name="cpu2_customInstruction_rsp_ready" type_name="CPU2_CUSTOMINSTRUCTION_RSP_READY" is_bus="false"/>
<efxpt:pin name="cpu2_customInstruction_rsp_valid" type_name="CPU2_CUSTOMINSTRUCTION_RSP_VALID" is_bus="false"/>
<efxpt:pin name="cpu3_customInstruction_cmd_ready" type_name="CPU3_CUSTOMINSTRUCTION_CMD_READY" is_bus="false"/>
<efxpt:pin name="cpu3_customInstruction_cmd_valid" type_name="CPU3_CUSTOMINSTRUCTION_CMD_VALID" is_bus="false"/>
<efxpt:pin name="cpu3_customInstruction_function_id" type_name="CPU3_CUSTOMINSTRUCTION_FUNCTION_ID" is_bus="true"/>
<efxpt:pin name="cpu3_customInstruction_inputs_0" type_name="CPU3_CUSTOMINSTRUCTION_INPUTS_0" is_bus="true"/>
<efxpt:pin name="cpu3_customInstruction_inputs_1" type_name="CPU3_CUSTOMINSTRUCTION_INPUTS_1" is_bus="true"/>
<efxpt:pin name="cpu3_customInstruction_outputs_0" type_name="CPU3_CUSTOMINSTRUCTION_OUTPUTS_0" is_bus="true"/>
<efxpt:pin name="cpu3_customInstruction_rsp_ready" type_name="CPU3_CUSTOMINSTRUCTION_RSP_READY" is_bus="false"/>
<efxpt:pin name="cpu3_customInstruction_rsp_valid" type_name="CPU3_CUSTOMINSTRUCTION_RSP_VALID" is_bus="false"/>
<efxpt:pin name="io_asyncReset" type_name="IO_ASYNCRESET" is_bus="false"/>
<efxpt:pin name="io_cfuClk" type_name="IO_CFUCLK" is_bus="false" is_clk="true" is_clk_invert="false"/>
<efxpt:pin name="io_cfuReset" type_name="IO_CFURESET" is_bus="false"/>
<efxpt:pin name="io_ddrMasters_0_ar_payload_addr" type_name="IO_DDRMASTERS_0_AR_PAYLOAD_ADDR" is_bus="true"/>
<efxpt:pin name="io_ddrMasters_0_ar_payload_burst" type_name="IO_DDRMASTERS_0_AR_PAYLOAD_BURST" is_bus="true"/>
<efxpt:pin name="io_ddrMasters_0_ar_payload_cache" type_name="IO_DDRMASTERS_0_AR_PAYLOAD_CACHE" is_bus="true"/>
<efxpt:pin name="io_ddrMasters_0_ar_payload_id" type_name="IO_DDRMASTERS_0_AR_PAYLOAD_ID" is_bus="true"/>
<efxpt:pin name="io_ddrMasters_0_ar_payload_len" type_name="IO_DDRMASTERS_0_AR_PAYLOAD_LEN" is_bus="true"/>
<efxpt:pin name="io_ddrMasters_0_ar_payload_lock" type_name="IO_DDRMASTERS_0_AR_PAYLOAD_LOCK" is_bus="false"/>
<efxpt:pin name="io_ddrMasters_0_ar_payload_prot" type_name="IO_DDRMASTERS_0_AR_PAYLOAD_PROT" is_bus="true"/>
<efxpt:pin name="io_ddrMasters_0_ar_payload_qos" type_name="IO_DDRMASTERS_0_AR_PAYLOAD_QOS" is_bus="true"/>
<efxpt:pin name="io_ddrMasters_0_ar_payload_region" type_name="IO_DDRMASTERS_0_AR_PAYLOAD_REGION" is_bus="true"/>
<efxpt:pin name="io_ddrMasters_0_ar_payload_size" type_name="IO_DDRMASTERS_0_AR_PAYLOAD_SIZE" is_bus="true"/>
<efxpt:pin name="io_ddrMasters_0_ar_ready" type_name="IO_DDRMASTERS_0_AR_READY" is_bus="false"/>
<efxpt:pin name="io_ddrMasters_0_ar_valid" type_name="IO_DDRMASTERS_0_AR_VALID" is_bus="false"/>
<efxpt:pin name="io_ddrMasters_0_aw_payload_addr" type_name="IO_DDRMASTERS_0_AW_PAYLOAD_ADDR" is_bus="true"/>
<efxpt:pin name="io_ddrMasters_0_aw_payload_allStrb" type_name="IO_DDRMASTERS_0_AW_PAYLOAD_ALLSTRB" is_bus="false"/>
<efxpt:pin name="io_ddrMasters_0_aw_payload_burst" type_name="IO_DDRMASTERS_0_AW_PAYLOAD_BURST" is_bus="true"/>
<efxpt:pin name="io_ddrMasters_0_aw_payload_cache" type_name="IO_DDRMASTERS_0_AW_PAYLOAD_CACHE" is_bus="true"/>
<efxpt:pin name="io_ddrMasters_0_aw_payload_id" type_name="IO_DDRMASTERS_0_AW_PAYLOAD_ID" is_bus="true"/>
<efxpt:pin name="io_ddrMasters_0_aw_payload_len" type_name="IO_DDRMASTERS_0_AW_PAYLOAD_LEN" is_bus="true"/>
<efxpt:pin name="io_ddrMasters_0_aw_payload_lock" type_name="IO_DDRMASTERS_0_AW_PAYLOAD_LOCK" is_bus="false"/>
<efxpt:pin name="io_ddrMasters_0_aw_payload_prot" type_name="IO_DDRMASTERS_0_AW_PAYLOAD_PROT" is_bus="true"/>
<efxpt:pin name="io_ddrMasters_0_aw_payload_qos" type_name="IO_DDRMASTERS_0_AW_PAYLOAD_QOS" is_bus="true"/>
<efxpt:pin name="io_ddrMasters_0_aw_payload_region" type_name="IO_DDRMASTERS_0_AW_PAYLOAD_REGION" is_bus="true"/>
<efxpt:pin name="io_ddrMasters_0_aw_payload_size" type_name="IO_DDRMASTERS_0_AW_PAYLOAD_SIZE" is_bus="true"/>
<efxpt:pin name="io_ddrMasters_0_aw_ready" type_name="IO_DDRMASTERS_0_AW_READY" is_bus="false"/>
<efxpt:pin name="io_ddrMasters_0_aw_valid" type_name="IO_DDRMASTERS_0_AW_VALID" is_bus="false"/>
<efxpt:pin name="io_ddrMasters_0_b_payload_id" type_name="IO_DDRMASTERS_0_B_PAYLOAD_ID" is_bus="true"/>
<efxpt:pin name="io_ddrMasters_0_b_payload_resp" type_name="IO_DDRMASTERS_0_B_PAYLOAD_RESP" is_bus="true"/>
<efxpt:pin name="io_ddrMasters_0_b_ready" type_name="IO_DDRMASTERS_0_B_READY" is_bus="false"/>
<efxpt:pin name="io_ddrMasters_0_b_valid" type_name="IO_DDRMASTERS_0_B_VALID" is_bus="false"/>
<efxpt:pin name="io_ddrMasters_0_clk" type_name="IO_DDRMASTERS_0_CLK" is_bus="false" is_clk="true" is_clk_invert="false"/>
<efxpt:pin name="io_ddrMasters_0_reset" type_name="IO_DDRMASTERS_0_RESET" is_bus="false"/>
<efxpt:pin name="io_ddrMasters_0_r_payload_data" type_name="IO_DDRMASTERS_0_R_PAYLOAD_DATA" is_bus="true"/>
<efxpt:pin name="io_ddrMasters_0_r_payload_id" type_name="IO_DDRMASTERS_0_R_PAYLOAD_ID" is_bus="true"/>
<efxpt:pin name="io_ddrMasters_0_r_payload_last" type_name="IO_DDRMASTERS_0_R_PAYLOAD_LAST" is_bus="false"/>
<efxpt:pin name="io_ddrMasters_0_r_payload_resp" type_name="IO_DDRMASTERS_0_R_PAYLOAD_RESP" is_bus="true"/>
<efxpt:pin name="io_ddrMasters_0_r_ready" type_name="IO_DDRMASTERS_0_R_READY" is_bus="false"/>
<efxpt:pin name="io_ddrMasters_0_r_valid" type_name="IO_DDRMASTERS_0_R_VALID" is_bus="false"/>
<efxpt:pin name="io_ddrMasters_0_w_payload_data" type_name="IO_DDRMASTERS_0_W_PAYLOAD_DATA" is_bus="true"/>
<efxpt:pin name="io_ddrMasters_0_w_payload_last" type_name="IO_DDRMASTERS_0_W_PAYLOAD_LAST" is_bus="false"/>
<efxpt:pin name="io_ddrMasters_0_w_payload_strb" type_name="IO_DDRMASTERS_0_W_PAYLOAD_STRB" is_bus="true"/>
<efxpt:pin name="io_ddrMasters_0_w_ready" type_name="IO_DDRMASTERS_0_W_READY" is_bus="false"/>
<efxpt:pin name="io_ddrMasters_0_w_valid" type_name="IO_DDRMASTERS_0_W_VALID" is_bus="false"/>
<efxpt:pin name="" type_name="IO_JTAG_TCK" is_bus="false" is_clk="true" is_clk_invert="false"/>
<efxpt:pin name="" type_name="IO_JTAG_TDI" is_bus="false"/>
<efxpt:pin name="" type_name="IO_JTAG_TDO" is_bus="false"/>
<efxpt:pin name="" type_name="IO_JTAG_TMS" is_bus="false"/>
<efxpt:pin name="io_peripheralClk" type_name="IO_PERIPHERALCLK" is_bus="false" is_clk="true" is_clk_invert="false"/>
<efxpt:pin name="io_peripheralReset" type_name="IO_PERIPHERALRESET" is_bus="false"/>
<efxpt:pin name="io_systemReset" type_name="IO_SYSTEMRESET" is_bus="false"/>
<efxpt:pin name="jtagCtrl_capture" type_name="JTAGCTRL_CAPTURE" is_bus="false"/>
<efxpt:pin name="jtagCtrl_enable" type_name="JTAGCTRL_ENABLE" is_bus="false"/>
<efxpt:pin name="jtagCtrl_reset" type_name="JTAGCTRL_RESET" is_bus="false"/>
<efxpt:pin name="jtagCtrl_shift" type_name="JTAGCTRL_SHIFT" is_bus="false"/>
<efxpt:pin name="jtagCtrl_tck" type_name="JTAGCTRL_TCK" is_bus="false" is_clk="true" is_clk_invert="false"/>
<efxpt:pin name="jtagCtrl_tdi" type_name="JTAGCTRL_TDI" is_bus="false"/>
<efxpt:pin name="jtagCtrl_tdo" type_name="JTAGCTRL_TDO" is_bus="false"/>
<efxpt:pin name="jtagCtrl_update" type_name="JTAGCTRL_UPDATE" is_bus="false"/>
<efxpt:pin name="" type_name="MEM_SHUTDOWN" is_bus="false"/>
<efxpt:pin name="" type_name="TEST_PCR_CLK" is_bus="false" is_clk="true" is_clk_invert="false"/>
<efxpt:pin name="" type_name="T_ATPG_NMBIST" is_bus="false"/>
<efxpt:pin name="" type_name="T_COMP_EN" is_bus="false"/>
<efxpt:pin name="" type_name="T_COMP_MASK_EN" is_bus="false"/>
<efxpt:pin name="" type_name="T_COMP_MASK_LD" is_bus="false"/>
<efxpt:pin name="" type_name="T_DFT_CLOCK" is_bus="false" is_clk="true" is_clk_invert="false"/>
<efxpt:pin name="" type_name="T_LOS_EN" is_bus="false"/>
<efxpt:pin name="" type_name="T_OPCG_ENABLE" is_bus="false"/>
<efxpt:pin name="" type_name="T_OPCG_LOAD" is_bus="false"/>
<efxpt:pin name="" type_name="T_OPCG_TRIGGER" is_bus="false"/>
<efxpt:pin name="" type_name="T_PMDA_DONE" is_bus="false"/>
<efxpt:pin name="" type_name="T_PMDA_FAIL" is_bus="false"/>
<efxpt:pin name="" type_name="T_PMDA_RESET" is_bus="false"/>
<efxpt:pin name="" type_name="T_PMDA_TCK" is_bus="false" is_clk="true" is_clk_invert="false"/>
<efxpt:pin name="" type_name="T_PMDA_TDI" is_bus="false"/>
<efxpt:pin name="" type_name="T_PMDA_TDO" is_bus="false"/>
<efxpt:pin name="" type_name="T_RSTN" is_bus="false"/>
<efxpt:pin name="" type_name="T_SCANIN" is_bus="true"/>
<efxpt:pin name="" type_name="T_SCANOUT" is_bus="true"/>
<efxpt:pin name="" type_name="T_SCK" is_bus="false" is_clk="true" is_clk_invert="false"/>
<efxpt:pin name="" type_name="T_SE" is_bus="false"/>
<efxpt:pin name="" type_name="T_SE_CG" is_bus="false"/>
<efxpt:pin name="" type_name="T_TM" is_bus="false"/>
<efxpt:pin name="userInterruptA" type_name="USERINTERRUPTA" is_bus="false"/>
<efxpt:pin name="userInterruptB" type_name="USERINTERRUPTB" is_bus="false"/>
<efxpt:pin name="userInterruptC" type_name="USERINTERRUPTC" is_bus="false"/>
<efxpt:pin name="userInterruptD" type_name="USERINTERRUPTD" is_bus="false"/>
<efxpt:pin name="userInterruptE" type_name="USERINTERRUPTE" is_bus="false"/>
<efxpt:pin name="userInterruptF" type_name="USERINTERRUPTF" is_bus="false"/>
<efxpt:pin name="userInterruptG" type_name="USERINTERRUPTG" is_bus="false"/>
<efxpt:pin name="userInterruptH" type_name="USERINTERRUPTH" is_bus="false"/>
<efxpt:pin name="userInterruptI" type_name="USERINTERRUPTI" is_bus="false"/>
<efxpt:pin name="" type_name="USERINTERRUPTJ" is_bus="false"/>
<efxpt:pin name="" type_name="USERINTERRUPTK" is_bus="false"/>
<efxpt:pin name="" type_name="USERINTERRUPTL" is_bus="false"/>
<efxpt:pin name="" type_name="USERINTERRUPTM" is_bus="false"/>
<efxpt:pin name="" type_name="USERINTERRUPTN" is_bus="false"/>
<efxpt:pin name="" type_name="USERINTERRUPTO" is_bus="false"/>
<efxpt:pin name="" type_name="USERINTERRUPTP" is_bus="false"/>
<efxpt:pin name="" type_name="USERINTERRUPTQ" is_bus="false"/>
<efxpt:pin name="" type_name="USERINTERRUPTR" is_bus="false"/>
<efxpt:pin name="" type_name="USERINTERRUPTS" is_bus="false"/>
<efxpt:pin name="" type_name="USERINTERRUPTT" is_bus="false"/>
<efxpt:pin name="" type_name="USERINTERRUPTU" is_bus="false"/>
<efxpt:pin name="" type_name="USERINTERRUPTV" is_bus="false"/>
<efxpt:pin name="" type_name="USERINTERRUPTW" is_bus="false"/>
<efxpt:pin name="" type_name="USERINTERRUPTX" is_bus="false"/>
</efxpt:gen_pin>
</efxpt:soc>
</efxpt:soc_info>
</efxpt:design_db>

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Ti375C529_devkit/Ti375C529_devkit.xml Normal file
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<?xml version="1.0" encoding="UTF-8"?>
<efx:project name="Ti375C529_devkit" description="" sw_version="2026.1.132" xmlns:efx="http://www.efinixinc.com/enf_proj" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xsi:schemaLocation="http://www.efinixinc.com/enf_proj enf_proj.xsd">
<efx:device_info>
<efx:family name="Titanium"/>
<efx:device name="Ti375C529"/>
<efx:timing_model name="C4"/>
</efx:device_info>
<efx:design_info def_veri_version="verilog_2k" def_vhdl_version="vhdl_2008" unified_flow="false" partition_interface_allowed_off_perimeter="true">
<efx:top_module name="top_soc"/>
<efx:design_file name="source/top_soc.v" version="default" library="default"/>
<efx:design_file name="source/tseCore.v" version="default" library="default"/>
<efx:design_file name="source/design_modules.v" version="default" library="default"/>
<efx:design_file name="source/MacTxLso.v" version="default" library="default"/>
<efx:design_file name="source/MacRxCheckSumChecker.v" version="default" library="default"/>
<efx:top_vhdl_arch name=""/>
<efx:msg_config name=""/>
<efx:partition_definitions name=""/>
<efx:partition_interface_assignments name=""/>
</efx:design_info>
<efx:interface_info>
<efx:default_peri_file name="Ti375C529_devkit.peri.xml"/>
<efx:peri_file name="Ti375C529_devkit.peri.xml"/>
</efx:interface_info>
<efx:constraint_info>
<efx:sdc_file name="constraints.sdc"/>
<efx:inter_file name=""/>
</efx:constraint_info>
<efx:sim_info/>
<efx:misc_info/>
<efx:ooc_info/>
<efx:ip_info>
<efx:ip instance_name="EfxSapphireHpSoc_slb" path="ip/EfxSapphireHpSoc_slb/settings.json" ooc="false">
<efx:ip_src_file name="EfxSapphireHpSoc_slb.v"/>
</efx:ip>
<efx:ip instance_name="gSDHC" path="ip/gSDHC/settings.json" ooc="false">
<efx:ip_src_file name="gSDHC.v"/>
</efx:ip>
<efx:ip instance_name="gTSE" path="ip/gTSE/settings.json" ooc="false">
<efx:ip_src_file name="gTSE.sv"/>
</efx:ip>
<efx:ip instance_name="gTSE_1to2_switch" path="ip/gTSE_1to2_switch/settings.json" ooc="false">
<efx:ip_src_file name="gTSE_1to2_switch.v"/>
</efx:ip>
<efx:ip instance_name="gDMA" path="ip/gDMA/settings.json" ooc="false">
<efx:ip_src_file name="gDMA.v"/>
</efx:ip>
<efx:ip instance_name="gTSE_core_fifo_data" path="ip/gTSE_core_fifo_data/settings.json" ooc="false">
<efx:ip_src_file name="gTSE_core_fifo_data.sv"/>
</efx:ip>
<efx:ip instance_name="gTSE_core_fifo_ctrl" path="ip/gTSE_core_fifo_ctrl/settings.json" ooc="false">
<efx:ip_src_file name="gTSE_core_fifo_ctrl.sv"/>
</efx:ip>
<efx:ip instance_name="gAXIM_2to1_switch" path="ip/gAXIM_2to1_switch/settings.json" ooc="false">
<efx:ip_src_file name="gAXIM_2to1_switch.v"/>
</efx:ip>
<efx:ip instance_name="gAXIS_1to3_switch" path="ip/gAXIS_1to3_switch/settings.json" ooc="false">
<efx:ip_src_file name="gAXIS_1to3_switch.v"/>
</efx:ip>
</efx:ip_info>
<efx:synthesis tool_name="efx_map">
<efx:param name="work_dir" value="work_syn" value_type="e_string"/>
<efx:param name="write_efx_verilog" value="on" value_type="e_bool"/>
<efx:param name="allow-const-ram-index" value="0" value_type="e_option"/>
<efx:param name="blackbox-error" value="1" value_type="e_option"/>
<efx:param name="blast_const_operand_adders" value="1" value_type="e_option"/>
<efx:param name="bram_output_regs_packing" value="1" value_type="e_option"/>
<efx:param name="create-onehot-fsms" value="0" value_type="e_option"/>
<efx:param name="fanout-limit" value="0" value_type="e_integer"/>
<efx:param name="hdl-compile-unit" value="1" value_type="e_option"/>
<efx:param name="infer-clk-enable" value="3" value_type="e_option"/>
<efx:param name="infer-sync-set-reset" value="1" value_type="e_option"/>
<efx:param name="max_ram" value="-1" value_type="e_integer"/>
<efx:param name="max_mult" value="-1" value_type="e_integer"/>
<efx:param name="min-sr-fanout" value="0" value_type="e_integer"/>
<efx:param name="min-ce-fanout" value="0" value_type="e_integer"/>
<efx:param name="mode" value="speed" value_type="e_option"/>
<efx:param name="mult-auto-pipeline" value="0" value_type="e_option"/>
<efx:param name="mult-decomp-retime" value="0" value_type="e_option"/>
<efx:param name="operator-sharing" value="0" value_type="e_option"/>
<efx:param name="optimize-adder-tree" value="0" value_type="e_option"/>
<efx:param name="optimize-zero-init-rom" value="1" value_type="e_option"/>
<efx:param name="retiming" value="1" value_type="e_option"/>
<efx:param name="seq_opt" value="1" value_type="e_option"/>
<efx:param name="seq-opt-sync-only" value="0" value_type="e_option"/>
<efx:param name="use-logic-for-small-mem" value="64" value_type="e_integer"/>
<efx:param name="use-logic-for-small-rom" value="64" value_type="e_integer"/>
<efx:param name="dsp-input-regs-packing" value="1" value_type="e_option"/>
<efx:param name="dsp-output-regs-packing" value="1" value_type="e_option"/>
<efx:param name="dsp-mac-packing" value="1" value_type="e_option"/>
<efx:param name="insert-carry-skip" value="0" value_type="e_option"/>
<efx:param name="pack-luts-to-comb4" value="0" value_type="e_option"/>
<efx:param name="include" value="ip/EfxSapphireHpSoc_slb" value_type="e_string"/>
<efx:param name="include" value="ip/gSDHC" value_type="e_string"/>
<efx:param name="include" value="ip/gTSE" value_type="e_string"/>
<efx:param name="include" value="ip/gTSE_1to2_switch" value_type="e_string"/>
<efx:param name="include" value="ip/gDMA" value_type="e_string"/>
<efx:param name="include" value="ip/gTSE_core_fifo_data" value_type="e_string"/>
<efx:param name="include" value="ip/gTSE_core_fifo_ctrl" value_type="e_string"/>
<efx:param name="include" value="ip/gAXIM_2to1_switch" value_type="e_string"/>
<efx:param name="include" value="ip/gAXIS_1to3_switch" value_type="e_string"/>
<efx:param name="bram-push-tco-outreg" value="0" value_type="e_option"/>
<efx:param name="hdl-loop-limit" value="20000" value_type="e_integer"/>
<efx:param name="peri-syn-instantiation" value="0" value_type="e_option"/>
<efx:param name="peri-syn-inference" value="0" value_type="e_option"/>
<efx:param name="max_threads" value="-1" value_type="e_integer"/>
<efx:param name="max-bit-blast-mem-size" value="10240" value_type="e_integer"/>
<efx:param name="ram-decomp-mode" value="0" value_type="e_option"/>
<efx:param name="enable-mark-debug" value="1" value_type="e_option"/>
<efx:param name="suppress_info_msgs" value="off" value_type="e_bool"/>
<efx:param name="suppress_warning_msgs" value="off" value_type="e_bool"/>
</efx:synthesis>
<efx:place_and_route tool_name="efx_pnr">
<efx:param name="work_dir" value="work_pnr" value_type="e_string"/>
<efx:param name="verbose" value="off" value_type="e_bool"/>
<efx:param name="seed" value="1" value_type="e_integer"/>
<efx:param name="placer_effort_level" value="2" value_type="e_option"/>
<efx:param name="max_threads" value="-1" value_type="e_integer"/>
<efx:param name="beneficial_skew" value="on" value_type="e_option"/>
<efx:param name="print_critical_path" value="10" value_type="e_integer"/>
<efx:param name="classic_flow" value="off" value_type="e_noarg"/>
<efx:param name="suppress_info_msgs" value="off" value_type="e_bool"/>
<efx:param name="suppress_warning_msgs" value="off" value_type="e_bool"/>
</efx:place_and_route>
<efx:bitstream_generation tool_name="efx_pgm">
<efx:param name="mode" value="active" value_type="e_option"/>
<efx:param name="width" value="1" value_type="e_option"/>
<efx:param name="enable_roms" value="smart" value_type="e_option"/>
<efx:param name="spi_low_power_mode" value="on" value_type="e_bool"/>
<efx:param name="io_weak_pullup" value="on" value_type="e_bool"/>
<efx:param name="oscillator_clock_divider" value="DIV8" value_type="e_option"/>
<efx:param name="bitstream_compression" value="on" value_type="e_bool"/>
<efx:param name="enable_external_master_clock" value="off" value_type="e_bool"/>
<efx:param name="active_capture_clk_edge" value="negedge" value_type="e_option"/>
<efx:param name="jtag_usercode" value="0xFFFFFFFF" value_type="e_string"/>
<efx:param name="release_tri_then_reset" value="on" value_type="e_bool"/>
<efx:param name="four_byte_addressing" value="off" value_type="e_bool"/>
<efx:param name="generate_bit" value="on" value_type="e_bool"/>
<efx:param name="generate_bitbin" value="off" value_type="e_bool"/>
<efx:param name="generate_hex" value="on" value_type="e_bool"/>
<efx:param name="generate_hexbin" value="off" value_type="e_bool"/>
<efx:param name="cold_boot" value="off" value_type="e_bool"/>
<efx:param name="cascade" value="off" value_type="e_option"/>
</efx:bitstream_generation>
<efx:debugger>
<efx:param name="work_dir" value="work_dbg" value_type="e_string"/>
<efx:param name="auto_instantiation" value="off" value_type="e_bool"/>
<efx:param name="profile" value="NONE" value_type="e_string"/>
</efx:debugger>
<efx:security>
<efx:param name="randomize_iv_value" value="on" value_type="e_bool"/>
<efx:param name="enable_bitstream_encrypt" value="off" value_type="e_bool"/>
<efx:param name="enable_bitstream_auth" value="off" value_type="e_bool"/>
<efx:param name="encryption_key_file" value="NONE" value_type="e_string"/>
<efx:param name="auth_key_file" value="NONE" value_type="e_string"/>
</efx:security>
</efx:project>

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Ti375C529_devkit/constraints.sdc Normal file
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# Auto-generated by Interface Designer
#
# WARNING: Any manual changes made to this file will be lost when generating constraints.
# Efinity Interface Designer SDC
# Version: 2024.M.98
# Date: 2024-04-13 10:16
# Copyright (C) 2013 - 2024 Efinix Inc. All rights reserved.
# Device: Ti375C529
# Project: Ti375C529_devkit
# Timing Model: C4 (preliminary)
# NOTE: The timing data is not final
# PLL Constraints
#################
create_clock -period 10.0000 io_sysFbClk
create_clock -period 5.0000 io_peripheralClk
create_clock -period 4.0000 io_ddrMasters_0_clk
create_clock -period 8.0000 io_cfuClk
create_clock -period 10.0000 sd_base_clk
create_clock -period 8.0000 rgmii_rxc
create_clock -waveform {2.0000 6.0000} -period 8.0000 io_tseClk_90
create_clock -period 8.0000 io_tseClk
set_clock_groups -exclusive -group {rgmii_rxc io_tseClk_90 io_tseClk} -group {sd_base_clk} -group {io_cfuClk} -group {io_peripheralClk} -group {io_ddrMasters_0_clk}
# GPIO Constraints
####################
set_output_delay -clock sd_base_clk -reference_pin [get_ports {sd_base_clk~CLKOUT~347~2}] -max 0.079 [get_ports {sd_clk_hi}]
set_output_delay -clock sd_base_clk -reference_pin [get_ports {sd_base_clk~CLKOUT~347~2}] -min -0.045 [get_ports {sd_clk_hi}]
# set_input_delay -clock <CLOCK> [-reference_pin <clkout_pad>] -max <MAX CALCULATION> [get_ports {io_gpio_sw_n}]
# set_input_delay -clock <CLOCK> [-reference_pin <clkout_pad>] -min <MIN CALCULATION> [get_ports {io_gpio_sw_n}]
# set_input_delay -clock <CLOCK> [-reference_pin <clkout_pad>] -max <MAX CALCULATION> [get_ports {system_uart_0_io_rxd}]
# set_input_delay -clock <CLOCK> [-reference_pin <clkout_pad>] -min <MIN CALCULATION> [get_ports {system_uart_0_io_rxd}]
# set_output_delay -clock <CLOCK> [-reference_pin <clkout_pad>] -max <MAX CALCULATION> [get_ports {system_uart_0_io_txd}]
# set_output_delay -clock <CLOCK> [-reference_pin <clkout_pad>] -min <MIN CALCULATION> [get_ports {system_uart_0_io_txd}]
# set_input_delay -clock <CLOCK> [-reference_pin <clkout_pad>] -max <MAX CALCULATION> [get_ports {system_gpio_0_io_read[1]}]
# set_input_delay -clock <CLOCK> [-reference_pin <clkout_pad>] -min <MIN CALCULATION> [get_ports {system_gpio_0_io_read[1]}]
# set_output_delay -clock <CLOCK> [-reference_pin <clkout_pad>] -max <MAX CALCULATION> [get_ports {system_gpio_0_io_write[1]}]
# set_output_delay -clock <CLOCK> [-reference_pin <clkout_pad>] -min <MIN CALCULATION> [get_ports {system_gpio_0_io_write[1]}]
# set_output_delay -clock <CLOCK> [-reference_pin <clkout_pad>] -max <MAX CALCULATION> [get_ports {system_gpio_0_io_writeEnable[1]}]
# set_output_delay -clock <CLOCK> [-reference_pin <clkout_pad>] -min <MIN CALCULATION> [get_ports {system_gpio_0_io_writeEnable[1]}]
# set_input_delay -clock <CLOCK> [-reference_pin <clkout_pad>] -max <MAX CALCULATION> [get_ports {system_gpio_0_io_read[2]}]
# set_input_delay -clock <CLOCK> [-reference_pin <clkout_pad>] -min <MIN CALCULATION> [get_ports {system_gpio_0_io_read[2]}]
# set_output_delay -clock <CLOCK> [-reference_pin <clkout_pad>] -max <MAX CALCULATION> [get_ports {system_gpio_0_io_write[2]}]
# set_output_delay -clock <CLOCK> [-reference_pin <clkout_pad>] -min <MIN CALCULATION> [get_ports {system_gpio_0_io_write[2]}]
# set_output_delay -clock <CLOCK> [-reference_pin <clkout_pad>] -max <MAX CALCULATION> [get_ports {system_gpio_0_io_writeEnable[2]}]
# set_output_delay -clock <CLOCK> [-reference_pin <clkout_pad>] -min <MIN CALCULATION> [get_ports {system_gpio_0_io_writeEnable[2]}]
# set_input_delay -clock <CLOCK> [-reference_pin <clkout_pad>] -max <MAX CALCULATION> [get_ports {system_i2c_0_io_scl_read}]
# set_input_delay -clock <CLOCK> [-reference_pin <clkout_pad>] -min <MIN CALCULATION> [get_ports {system_i2c_0_io_scl_read}]
# set_output_delay -clock <CLOCK> [-reference_pin <clkout_pad>] -max <MAX CALCULATION> [get_ports {system_i2c_0_io_scl_write}]
# set_output_delay -clock <CLOCK> [-reference_pin <clkout_pad>] -min <MIN CALCULATION> [get_ports {system_i2c_0_io_scl_write}]
# set_output_delay -clock <CLOCK> [-reference_pin <clkout_pad>] -max <MAX CALCULATION> [get_ports {system_i2c_0_io_scl_writeEnable}]
# set_output_delay -clock <CLOCK> [-reference_pin <clkout_pad>] -min <MIN CALCULATION> [get_ports {system_i2c_0_io_scl_writeEnable}]
# set_input_delay -clock <CLOCK> [-reference_pin <clkout_pad>] -max <MAX CALCULATION> [get_ports {system_i2c_0_io_sda_read}]
# set_input_delay -clock <CLOCK> [-reference_pin <clkout_pad>] -min <MIN CALCULATION> [get_ports {system_i2c_0_io_sda_read}]
# set_output_delay -clock <CLOCK> [-reference_pin <clkout_pad>] -max <MAX CALCULATION> [get_ports {system_i2c_0_io_sda_write}]
# set_output_delay -clock <CLOCK> [-reference_pin <clkout_pad>] -min <MIN CALCULATION> [get_ports {system_i2c_0_io_sda_write}]
# set_output_delay -clock <CLOCK> [-reference_pin <clkout_pad>] -max <MAX CALCULATION> [get_ports {system_i2c_0_io_sda_writeEnable}]
# set_output_delay -clock <CLOCK> [-reference_pin <clkout_pad>] -min <MIN CALCULATION> [get_ports {system_i2c_0_io_sda_writeEnable}]
# JTAG Constraints
####################
create_clock -period 100 [get_ports {jtagCtrl_tck}]
set_output_delay -clock jtagCtrl_tck -max 0.117 [get_ports {ut_jtagCtrl_tdo}]
set_output_delay -clock jtagCtrl_tck -min -0.075 [get_ports {ut_jtagCtrl_tdo}]
set_input_delay -clock_fall -clock jtagCtrl_tck -max 0.280 [get_ports {ut_jtagCtrl_capture}]
set_input_delay -clock_fall -clock jtagCtrl_tck -min 0.187 [get_ports {ut_jtagCtrl_capture}]
set_input_delay -clock_fall -clock jtagCtrl_tck -max 0.280 [get_ports {ut_jtagCtrl_reset}]
set_input_delay -clock_fall -clock jtagCtrl_tck -min 0.187 [get_ports {ut_jtagCtrl_reset}]
set_input_delay -clock_fall -clock jtagCtrl_tck -max 0.243 [get_ports {ut_jtagCtrl_enable}]
set_input_delay -clock_fall -clock jtagCtrl_tck -min 0.162 [get_ports {ut_jtagCtrl_enable}]
set_input_delay -clock_fall -clock jtagCtrl_tck -max 0.280 [get_ports {ut_jtagCtrl_update}]
set_input_delay -clock_fall -clock jtagCtrl_tck -min 0.187 [get_ports {ut_jtagCtrl_update}]
set_input_delay -clock_fall -clock jtagCtrl_tck -max 0.337 [get_ports {ut_jtagCtrl_shift}]
set_input_delay -clock_fall -clock jtagCtrl_tck -min 0.225 [get_ports {ut_jtagCtrl_shift}]
# JTAG Constraints (extra... not used by current Efinity debug tools)
# Create separate clock groups for JTAG clocks. Remove DRCK clock from the list below if it is not defined.
# set_clock_groups -asynchronous -group {jtagCtrl_tck}
# HSIO GPIO Constraints
#########################
set_input_delay -clock rgmii_rxc -reference_pin [get_ports {rgmii_rxc~CLKOUT~391~964}] -max 0.414 [get_ports {rgmii_rx_ctl_LO rgmii_rx_ctl_HI}]
set_input_delay -clock rgmii_rxc -reference_pin [get_ports {rgmii_rxc~CLKOUT~391~964}] -min 0.276 [get_ports {rgmii_rx_ctl_LO rgmii_rx_ctl_HI}]
# set_input_delay -clock <CLOCK> [-reference_pin <clkout_pad>] -max <MAX CALCULATION> [get_ports {rgmii_rxc_phy}]
# set_input_delay -clock <CLOCK> [-reference_pin <clkout_pad>] -min <MIN CALCULATION> [get_ports {rgmii_rxc_phy}]
# set_input_delay -clock <CLOCK> [-reference_pin <clkout_pad>] -max <MAX CALCULATION> [get_ports {rgmii_rxc_slow}]
# set_input_delay -clock <CLOCK> [-reference_pin <clkout_pad>] -min <MIN CALCULATION> [get_ports {rgmii_rxc_slow}]
set_input_delay -clock rgmii_rxc -reference_pin [get_ports {rgmii_rxc~CLKOUT~395~964}] -max 0.414 [get_ports {rgmii_rxd_LO[0] rgmii_rxd_HI[0]}]
set_input_delay -clock rgmii_rxc -reference_pin [get_ports {rgmii_rxc~CLKOUT~395~964}] -min 0.276 [get_ports {rgmii_rxd_LO[0] rgmii_rxd_HI[0]}]
set_input_delay -clock rgmii_rxc -reference_pin [get_ports {rgmii_rxc~CLKOUT~397~964}] -max 0.414 [get_ports {rgmii_rxd_LO[1] rgmii_rxd_HI[1]}]
set_input_delay -clock rgmii_rxc -reference_pin [get_ports {rgmii_rxc~CLKOUT~397~964}] -min 0.276 [get_ports {rgmii_rxd_LO[1] rgmii_rxd_HI[1]}]
set_input_delay -clock rgmii_rxc -reference_pin [get_ports {rgmii_rxc~CLKOUT~408~964}] -max 0.414 [get_ports {rgmii_rxd_LO[2] rgmii_rxd_HI[2]}]
set_input_delay -clock rgmii_rxc -reference_pin [get_ports {rgmii_rxc~CLKOUT~408~964}] -min 0.276 [get_ports {rgmii_rxd_LO[2] rgmii_rxd_HI[2]}]
set_input_delay -clock rgmii_rxc -reference_pin [get_ports {rgmii_rxc~CLKOUT~412~963}] -max 0.414 [get_ports {rgmii_rxd_LO[3] rgmii_rxd_HI[3]}]
set_input_delay -clock rgmii_rxc -reference_pin [get_ports {rgmii_rxc~CLKOUT~412~963}] -min 0.276 [get_ports {rgmii_rxd_LO[3] rgmii_rxd_HI[3]}]
# set_input_delay -clock <CLOCK> [-reference_pin <clkout_pad>] -max <MAX CALCULATION> [get_ports {sd_cd_n}]
# set_input_delay -clock <CLOCK> [-reference_pin <clkout_pad>] -min <MIN CALCULATION> [get_ports {sd_cd_n}]
# set_output_delay -clock <CLOCK> [-reference_pin <clkout_pad>] -max <MAX CALCULATION> [get_ports {io_ddrMasters_memCheck_pass}]
# set_output_delay -clock <CLOCK> [-reference_pin <clkout_pad>] -min <MIN CALCULATION> [get_ports {io_ddrMasters_memCheck_pass}]
# set_output_delay -clock <CLOCK> [-reference_pin <clkout_pad>] -max <MAX CALCULATION> [get_ports {phy_mdc}]
# set_output_delay -clock <CLOCK> [-reference_pin <clkout_pad>] -min <MIN CALCULATION> [get_ports {phy_mdc}]
set_output_delay -clock io_tseClk -reference_pin [get_ports {io_tseClk~CLKOUT~352~963}] -max 0.263 [get_ports {rgmii_tx_ctl_LO rgmii_tx_ctl_HI}]
set_output_delay -clock io_tseClk -reference_pin [get_ports {io_tseClk~CLKOUT~352~963}] -min -0.140 [get_ports {rgmii_tx_ctl_LO rgmii_tx_ctl_HI}]
set_output_delay -clock io_tseClk_90 -reference_pin [get_ports {io_tseClk_90~CLKOUT~359~964}] -max 0.263 [get_ports {rgmii_txc_LO rgmii_txc_HI}]
set_output_delay -clock io_tseClk_90 -reference_pin [get_ports {io_tseClk_90~CLKOUT~359~964}] -min -0.140 [get_ports {rgmii_txc_LO rgmii_txc_HI}]
set_output_delay -clock io_tseClk -reference_pin [get_ports {io_tseClk~CLKOUT~358~963}] -max 0.263 [get_ports {rgmii_txd_LO[0] rgmii_txd_HI[0]}]
set_output_delay -clock io_tseClk -reference_pin [get_ports {io_tseClk~CLKOUT~358~963}] -min -0.140 [get_ports {rgmii_txd_LO[0] rgmii_txd_HI[0]}]
set_output_delay -clock io_tseClk -reference_pin [get_ports {io_tseClk~CLKOUT~364~963}] -max 0.263 [get_ports {rgmii_txd_LO[1] rgmii_txd_HI[1]}]
set_output_delay -clock io_tseClk -reference_pin [get_ports {io_tseClk~CLKOUT~364~963}] -min -0.140 [get_ports {rgmii_txd_LO[1] rgmii_txd_HI[1]}]
set_output_delay -clock io_tseClk -reference_pin [get_ports {io_tseClk~CLKOUT~365~964}] -max 0.263 [get_ports {rgmii_txd_LO[2] rgmii_txd_HI[2]}]
set_output_delay -clock io_tseClk -reference_pin [get_ports {io_tseClk~CLKOUT~365~964}] -min -0.140 [get_ports {rgmii_txd_LO[2] rgmii_txd_HI[2]}]
set_output_delay -clock io_tseClk -reference_pin [get_ports {io_tseClk~CLKOUT~376~964}] -max 0.263 [get_ports {rgmii_txd_LO[3] rgmii_txd_HI[3]}]
set_output_delay -clock io_tseClk -reference_pin [get_ports {io_tseClk~CLKOUT~376~964}] -min -0.140 [get_ports {rgmii_txd_LO[3] rgmii_txd_HI[3]}]
set_output_delay -clock io_peripheralClk -reference_pin [get_ports {io_peripheralClk~CLKOUT~418~2}] -max 0.263 [get_ports {system_spi_0_io_sclk_write}]
set_output_delay -clock io_peripheralClk -reference_pin [get_ports {io_peripheralClk~CLKOUT~418~2}] -min -0.140 [get_ports {system_spi_0_io_sclk_write}]
set_output_delay -clock io_peripheralClk -reference_pin [get_ports {io_peripheralClk~CLKOUT~407~2}] -max 0.263 [get_ports {system_spi_0_io_ss[0]}]
set_output_delay -clock io_peripheralClk -reference_pin [get_ports {io_peripheralClk~CLKOUT~407~2}] -min -0.140 [get_ports {system_spi_0_io_ss[0]}]
set_input_delay -clock io_tseClk -reference_pin [get_ports {io_tseClk~CLKOUT~381~964}] -max 0.414 [get_ports {phy_mdi}]
set_input_delay -clock io_tseClk -reference_pin [get_ports {io_tseClk~CLKOUT~381~964}] -min 0.276 [get_ports {phy_mdi}]
set_output_delay -clock io_tseClk -reference_pin [get_ports {io_tseClk~CLKOUT~384~964}] -max 0.263 [get_ports {phy_mdo}]
set_output_delay -clock io_tseClk -reference_pin [get_ports {io_tseClk~CLKOUT~384~964}] -min -0.140 [get_ports {phy_mdo}]
set_output_delay -clock io_tseClk -reference_pin [get_ports {io_tseClk~CLKOUT~384~964}] -max 0.263 [get_ports {phy_mdo_en}]
set_output_delay -clock io_tseClk -reference_pin [get_ports {io_tseClk~CLKOUT~384~964}] -min -0.140 [get_ports {phy_mdo_en}]
# set_input_delay -clock <CLOCK> [-reference_pin <clkout_pad>] -max <MAX CALCULATION> [get_ports {system_gpio_0_io_read[0]}]
# set_input_delay -clock <CLOCK> [-reference_pin <clkout_pad>] -min <MIN CALCULATION> [get_ports {system_gpio_0_io_read[0]}]
# set_output_delay -clock <CLOCK> [-reference_pin <clkout_pad>] -max <MAX CALCULATION> [get_ports {system_gpio_0_io_write[0]}]
# set_output_delay -clock <CLOCK> [-reference_pin <clkout_pad>] -min <MIN CALCULATION> [get_ports {system_gpio_0_io_write[0]}]
# set_output_delay -clock <CLOCK> [-reference_pin <clkout_pad>] -max <MAX CALCULATION> [get_ports {system_gpio_0_io_writeEnable[0]}]
# set_output_delay -clock <CLOCK> [-reference_pin <clkout_pad>] -min <MIN CALCULATION> [get_ports {system_gpio_0_io_writeEnable[0]}]
# set_input_delay -clock <CLOCK> [-reference_pin <clkout_pad>] -max <MAX CALCULATION> [get_ports {system_gpio_0_io_read[3]}]
# set_input_delay -clock <CLOCK> [-reference_pin <clkout_pad>] -min <MIN CALCULATION> [get_ports {system_gpio_0_io_read[3]}]
# set_output_delay -clock <CLOCK> [-reference_pin <clkout_pad>] -max <MAX CALCULATION> [get_ports {system_gpio_0_io_write[3]}]
# set_output_delay -clock <CLOCK> [-reference_pin <clkout_pad>] -min <MIN CALCULATION> [get_ports {system_gpio_0_io_write[3]}]
# set_output_delay -clock <CLOCK> [-reference_pin <clkout_pad>] -max <MAX CALCULATION> [get_ports {system_gpio_0_io_writeEnable[3]}]
# set_output_delay -clock <CLOCK> [-reference_pin <clkout_pad>] -min <MIN CALCULATION> [get_ports {system_gpio_0_io_writeEnable[3]}]
set_input_delay -clock io_peripheralClk -reference_pin [get_ports {io_peripheralClk~CLKOUT~418~1}] -max 0.414 [get_ports {system_spi_0_io_data_0_read}]
set_input_delay -clock io_peripheralClk -reference_pin [get_ports {io_peripheralClk~CLKOUT~418~1}] -min 0.276 [get_ports {system_spi_0_io_data_0_read}]
set_output_delay -clock io_peripheralClk -reference_pin [get_ports {io_peripheralClk~CLKOUT~422~2}] -max 0.263 [get_ports {system_spi_0_io_data_0_write}]
set_output_delay -clock io_peripheralClk -reference_pin [get_ports {io_peripheralClk~CLKOUT~422~2}] -min -0.140 [get_ports {system_spi_0_io_data_0_write}]
set_output_delay -clock io_peripheralClk -reference_pin [get_ports {io_peripheralClk~CLKOUT~422~2}] -max 0.263 [get_ports {system_spi_0_io_data_0_writeEnable}]
set_output_delay -clock io_peripheralClk -reference_pin [get_ports {io_peripheralClk~CLKOUT~422~2}] -min -0.140 [get_ports {system_spi_0_io_data_0_writeEnable}]
set_input_delay -clock io_peripheralClk -reference_pin [get_ports {io_peripheralClk~CLKOUT~425~1}] -max 0.414 [get_ports {system_spi_0_io_data_1_read}]
set_input_delay -clock io_peripheralClk -reference_pin [get_ports {io_peripheralClk~CLKOUT~425~1}] -min 0.276 [get_ports {system_spi_0_io_data_1_read}]
set_output_delay -clock io_peripheralClk -reference_pin [get_ports {io_peripheralClk~CLKOUT~420~1}] -max 0.263 [get_ports {system_spi_0_io_data_1_write}]
set_output_delay -clock io_peripheralClk -reference_pin [get_ports {io_peripheralClk~CLKOUT~420~1}] -min -0.140 [get_ports {system_spi_0_io_data_1_write}]
set_output_delay -clock io_peripheralClk -reference_pin [get_ports {io_peripheralClk~CLKOUT~420~1}] -max 0.263 [get_ports {system_spi_0_io_data_1_writeEnable}]
set_output_delay -clock io_peripheralClk -reference_pin [get_ports {io_peripheralClk~CLKOUT~420~1}] -min -0.140 [get_ports {system_spi_0_io_data_1_writeEnable}]
# QCRV32 Constraints
#######################
set_input_delay -clock io_ddrMasters_0_clk -reference_pin [get_ports {io_ddrMasters_0_clk~CLKOUT~38~2}] -max 0.701 [get_ports {io_ddrMasters_0_reset}]
set_input_delay -clock io_ddrMasters_0_clk -reference_pin [get_ports {io_ddrMasters_0_clk~CLKOUT~38~2}] -min 0.340 [get_ports {io_ddrMasters_0_reset}]
set_output_delay -clock io_ddrMasters_0_clk -reference_pin [get_ports {io_ddrMasters_0_clk~CLKOUT~38~2}] -max 0.196 [get_ports {io_ddrMasters_0_ar_payload_addr[*]}]
set_output_delay -clock io_ddrMasters_0_clk -reference_pin [get_ports {io_ddrMasters_0_clk~CLKOUT~38~2}] -min -0.071 [get_ports {io_ddrMasters_0_ar_payload_addr[*]}]
set_output_delay -clock io_ddrMasters_0_clk -reference_pin [get_ports {io_ddrMasters_0_clk~CLKOUT~38~2}] -max 0.217 [get_ports {io_ddrMasters_0_ar_payload_burst[*]}]
set_output_delay -clock io_ddrMasters_0_clk -reference_pin [get_ports {io_ddrMasters_0_clk~CLKOUT~38~2}] -min -0.034 [get_ports {io_ddrMasters_0_ar_payload_burst[*]}]
set_output_delay -clock io_ddrMasters_0_clk -reference_pin [get_ports {io_ddrMasters_0_clk~CLKOUT~38~2}] -max 0.222 [get_ports {io_ddrMasters_0_ar_payload_cache[*]}]
set_output_delay -clock io_ddrMasters_0_clk -reference_pin [get_ports {io_ddrMasters_0_clk~CLKOUT~38~2}] -min 0.020 [get_ports {io_ddrMasters_0_ar_payload_cache[*]}]
set_output_delay -clock io_ddrMasters_0_clk -reference_pin [get_ports {io_ddrMasters_0_clk~CLKOUT~38~2}] -max 0.247 [get_ports {io_ddrMasters_0_ar_payload_id[*]}]
set_output_delay -clock io_ddrMasters_0_clk -reference_pin [get_ports {io_ddrMasters_0_clk~CLKOUT~38~2}] -min -0.038 [get_ports {io_ddrMasters_0_ar_payload_id[*]}]
set_output_delay -clock io_ddrMasters_0_clk -reference_pin [get_ports {io_ddrMasters_0_clk~CLKOUT~38~2}] -max 0.251 [get_ports {io_ddrMasters_0_ar_payload_len[*]}]
set_output_delay -clock io_ddrMasters_0_clk -reference_pin [get_ports {io_ddrMasters_0_clk~CLKOUT~38~2}] -min -0.008 [get_ports {io_ddrMasters_0_ar_payload_len[*]}]
set_output_delay -clock io_ddrMasters_0_clk -reference_pin [get_ports {io_ddrMasters_0_clk~CLKOUT~38~2}] -max 0.226 [get_ports {io_ddrMasters_0_ar_payload_lock}]
set_output_delay -clock io_ddrMasters_0_clk -reference_pin [get_ports {io_ddrMasters_0_clk~CLKOUT~38~2}] -min 0.054 [get_ports {io_ddrMasters_0_ar_payload_lock}]
set_output_delay -clock io_ddrMasters_0_clk -reference_pin [get_ports {io_ddrMasters_0_clk~CLKOUT~38~2}] -max 0.265 [get_ports {io_ddrMasters_0_ar_payload_prot[*]}]
set_output_delay -clock io_ddrMasters_0_clk -reference_pin [get_ports {io_ddrMasters_0_clk~CLKOUT~38~2}] -min 0.006 [get_ports {io_ddrMasters_0_ar_payload_prot[*]}]
set_output_delay -clock io_ddrMasters_0_clk -reference_pin [get_ports {io_ddrMasters_0_clk~CLKOUT~38~2}] -max 0.191 [get_ports {io_ddrMasters_0_ar_payload_qos[*]}]
set_output_delay -clock io_ddrMasters_0_clk -reference_pin [get_ports {io_ddrMasters_0_clk~CLKOUT~38~2}] -min 0.013 [get_ports {io_ddrMasters_0_ar_payload_qos[*]}]
set_output_delay -clock io_ddrMasters_0_clk -reference_pin [get_ports {io_ddrMasters_0_clk~CLKOUT~38~2}] -max 0.259 [get_ports {io_ddrMasters_0_ar_payload_region[*]}]
set_output_delay -clock io_ddrMasters_0_clk -reference_pin [get_ports {io_ddrMasters_0_clk~CLKOUT~38~2}] -min 0.018 [get_ports {io_ddrMasters_0_ar_payload_region[*]}]
set_output_delay -clock io_ddrMasters_0_clk -reference_pin [get_ports {io_ddrMasters_0_clk~CLKOUT~38~2}] -max 0.219 [get_ports {io_ddrMasters_0_ar_payload_size[*]}]
set_output_delay -clock io_ddrMasters_0_clk -reference_pin [get_ports {io_ddrMasters_0_clk~CLKOUT~38~2}] -min -0.007 [get_ports {io_ddrMasters_0_ar_payload_size[*]}]
set_input_delay -clock io_ddrMasters_0_clk -reference_pin [get_ports {io_ddrMasters_0_clk~CLKOUT~38~2}] -max 1.064 [get_ports {io_ddrMasters_0_ar_ready}]
set_input_delay -clock io_ddrMasters_0_clk -reference_pin [get_ports {io_ddrMasters_0_clk~CLKOUT~38~2}] -min 0.544 [get_ports {io_ddrMasters_0_ar_ready}]
set_output_delay -clock io_ddrMasters_0_clk -reference_pin [get_ports {io_ddrMasters_0_clk~CLKOUT~38~2}] -max 0.025 [get_ports {io_ddrMasters_0_ar_valid}]
set_output_delay -clock io_ddrMasters_0_clk -reference_pin [get_ports {io_ddrMasters_0_clk~CLKOUT~38~2}] -min -0.051 [get_ports {io_ddrMasters_0_ar_valid}]
set_input_delay -clock io_ddrMasters_0_clk -reference_pin [get_ports {io_ddrMasters_0_clk~CLKOUT~38~2}] -max 1.031 [get_ports {io_ddrMasters_0_r_payload_data[*]}]
set_input_delay -clock io_ddrMasters_0_clk -reference_pin [get_ports {io_ddrMasters_0_clk~CLKOUT~38~2}] -min 0.347 [get_ports {io_ddrMasters_0_r_payload_data[*]}]
set_input_delay -clock io_ddrMasters_0_clk -reference_pin [get_ports {io_ddrMasters_0_clk~CLKOUT~38~2}] -max 0.844 [get_ports {io_ddrMasters_0_r_payload_last}]
set_input_delay -clock io_ddrMasters_0_clk -reference_pin [get_ports {io_ddrMasters_0_clk~CLKOUT~38~2}] -min 0.387 [get_ports {io_ddrMasters_0_r_payload_last}]
set_output_delay -clock io_ddrMasters_0_clk -reference_pin [get_ports {io_ddrMasters_0_clk~CLKOUT~38~2}] -max 0.426 [get_ports {io_ddrMasters_0_r_ready}]
set_output_delay -clock io_ddrMasters_0_clk -reference_pin [get_ports {io_ddrMasters_0_clk~CLKOUT~38~2}] -min 0.095 [get_ports {io_ddrMasters_0_r_ready}]
set_input_delay -clock io_ddrMasters_0_clk -reference_pin [get_ports {io_ddrMasters_0_clk~CLKOUT~38~2}] -max 0.965 [get_ports {io_ddrMasters_0_r_valid}]
set_input_delay -clock io_ddrMasters_0_clk -reference_pin [get_ports {io_ddrMasters_0_clk~CLKOUT~38~2}] -min 0.508 [get_ports {io_ddrMasters_0_r_valid}]
set_output_delay -clock io_ddrMasters_0_clk -reference_pin [get_ports {io_ddrMasters_0_clk~CLKOUT~38~2}] -max 0.372 [get_ports {io_ddrMasters_0_aw_payload_addr[*]}]
set_output_delay -clock io_ddrMasters_0_clk -reference_pin [get_ports {io_ddrMasters_0_clk~CLKOUT~38~2}] -min 0.005 [get_ports {io_ddrMasters_0_aw_payload_addr[*]}]
set_output_delay -clock io_ddrMasters_0_clk -reference_pin [get_ports {io_ddrMasters_0_clk~CLKOUT~38~2}] -max 0.296 [get_ports {io_ddrMasters_0_aw_payload_allStrb}]
set_output_delay -clock io_ddrMasters_0_clk -reference_pin [get_ports {io_ddrMasters_0_clk~CLKOUT~38~2}] -min -0.016 [get_ports {io_ddrMasters_0_aw_payload_allStrb}]
set_output_delay -clock io_ddrMasters_0_clk -reference_pin [get_ports {io_ddrMasters_0_clk~CLKOUT~38~2}] -max 0.217 [get_ports {io_ddrMasters_0_aw_payload_burst[*]}]
set_output_delay -clock io_ddrMasters_0_clk -reference_pin [get_ports {io_ddrMasters_0_clk~CLKOUT~38~2}] -min 0.002 [get_ports {io_ddrMasters_0_aw_payload_burst[*]}]
set_output_delay -clock io_ddrMasters_0_clk -reference_pin [get_ports {io_ddrMasters_0_clk~CLKOUT~38~2}] -max 0.217 [get_ports {io_ddrMasters_0_aw_payload_cache[*]}]
set_output_delay -clock io_ddrMasters_0_clk -reference_pin [get_ports {io_ddrMasters_0_clk~CLKOUT~38~2}] -min -0.027 [get_ports {io_ddrMasters_0_aw_payload_cache[*]}]
set_output_delay -clock io_ddrMasters_0_clk -reference_pin [get_ports {io_ddrMasters_0_clk~CLKOUT~38~2}] -max 0.238 [get_ports {io_ddrMasters_0_aw_payload_id[*]}]
set_output_delay -clock io_ddrMasters_0_clk -reference_pin [get_ports {io_ddrMasters_0_clk~CLKOUT~38~2}] -min -0.001 [get_ports {io_ddrMasters_0_aw_payload_id[*]}]
set_output_delay -clock io_ddrMasters_0_clk -reference_pin [get_ports {io_ddrMasters_0_clk~CLKOUT~38~2}] -max 0.280 [get_ports {io_ddrMasters_0_aw_payload_len[*]}]
set_output_delay -clock io_ddrMasters_0_clk -reference_pin [get_ports {io_ddrMasters_0_clk~CLKOUT~38~2}] -min -0.003 [get_ports {io_ddrMasters_0_aw_payload_len[*]}]
set_output_delay -clock io_ddrMasters_0_clk -reference_pin [get_ports {io_ddrMasters_0_clk~CLKOUT~38~2}] -max 0.205 [get_ports {io_ddrMasters_0_aw_payload_lock}]
set_output_delay -clock io_ddrMasters_0_clk -reference_pin [get_ports {io_ddrMasters_0_clk~CLKOUT~38~2}] -min -0.022 [get_ports {io_ddrMasters_0_aw_payload_lock}]
set_output_delay -clock io_ddrMasters_0_clk -reference_pin [get_ports {io_ddrMasters_0_clk~CLKOUT~38~2}] -max 0.178 [get_ports {io_ddrMasters_0_aw_payload_prot[*]}]
set_output_delay -clock io_ddrMasters_0_clk -reference_pin [get_ports {io_ddrMasters_0_clk~CLKOUT~38~2}] -min -0.039 [get_ports {io_ddrMasters_0_aw_payload_prot[*]}]
set_output_delay -clock io_ddrMasters_0_clk -reference_pin [get_ports {io_ddrMasters_0_clk~CLKOUT~38~2}] -max 0.243 [get_ports {io_ddrMasters_0_aw_payload_qos[*]}]
set_output_delay -clock io_ddrMasters_0_clk -reference_pin [get_ports {io_ddrMasters_0_clk~CLKOUT~38~2}] -min -0.053 [get_ports {io_ddrMasters_0_aw_payload_qos[*]}]
set_output_delay -clock io_ddrMasters_0_clk -reference_pin [get_ports {io_ddrMasters_0_clk~CLKOUT~38~2}] -max 0.253 [get_ports {io_ddrMasters_0_aw_payload_region[*]}]
set_output_delay -clock io_ddrMasters_0_clk -reference_pin [get_ports {io_ddrMasters_0_clk~CLKOUT~38~2}] -min 0.008 [get_ports {io_ddrMasters_0_aw_payload_region[*]}]
set_output_delay -clock io_ddrMasters_0_clk -reference_pin [get_ports {io_ddrMasters_0_clk~CLKOUT~38~2}] -max 0.263 [get_ports {io_ddrMasters_0_aw_payload_size[*]}]
set_output_delay -clock io_ddrMasters_0_clk -reference_pin [get_ports {io_ddrMasters_0_clk~CLKOUT~38~2}] -min -0.007 [get_ports {io_ddrMasters_0_aw_payload_size[*]}]
set_input_delay -clock io_ddrMasters_0_clk -reference_pin [get_ports {io_ddrMasters_0_clk~CLKOUT~38~2}] -max 1.213 [get_ports {io_ddrMasters_0_aw_ready}]
set_input_delay -clock io_ddrMasters_0_clk -reference_pin [get_ports {io_ddrMasters_0_clk~CLKOUT~38~2}] -min 0.610 [get_ports {io_ddrMasters_0_aw_ready}]
set_output_delay -clock io_ddrMasters_0_clk -reference_pin [get_ports {io_ddrMasters_0_clk~CLKOUT~38~2}] -max 0.294 [get_ports {io_ddrMasters_0_aw_valid}]
set_output_delay -clock io_ddrMasters_0_clk -reference_pin [get_ports {io_ddrMasters_0_clk~CLKOUT~38~2}] -min 0.058 [get_ports {io_ddrMasters_0_aw_valid}]
set_output_delay -clock io_ddrMasters_0_clk -reference_pin [get_ports {io_ddrMasters_0_clk~CLKOUT~38~2}] -max 0.289 [get_ports {io_ddrMasters_0_w_payload_data[*]}]
set_output_delay -clock io_ddrMasters_0_clk -reference_pin [get_ports {io_ddrMasters_0_clk~CLKOUT~38~2}] -min -0.105 [get_ports {io_ddrMasters_0_w_payload_data[*]}]
set_output_delay -clock io_ddrMasters_0_clk -reference_pin [get_ports {io_ddrMasters_0_clk~CLKOUT~38~2}] -max 0.042 [get_ports {io_ddrMasters_0_w_payload_last}]
set_output_delay -clock io_ddrMasters_0_clk -reference_pin [get_ports {io_ddrMasters_0_clk~CLKOUT~38~2}] -min -0.053 [get_ports {io_ddrMasters_0_w_payload_last}]
set_output_delay -clock io_ddrMasters_0_clk -reference_pin [get_ports {io_ddrMasters_0_clk~CLKOUT~38~2}] -max 0.130 [get_ports {io_ddrMasters_0_w_payload_strb[*]}]
set_output_delay -clock io_ddrMasters_0_clk -reference_pin [get_ports {io_ddrMasters_0_clk~CLKOUT~38~2}] -min -0.070 [get_ports {io_ddrMasters_0_w_payload_strb[*]}]
set_input_delay -clock io_ddrMasters_0_clk -reference_pin [get_ports {io_ddrMasters_0_clk~CLKOUT~38~2}] -max 1.193 [get_ports {io_ddrMasters_0_w_ready}]
set_input_delay -clock io_ddrMasters_0_clk -reference_pin [get_ports {io_ddrMasters_0_clk~CLKOUT~38~2}] -min 0.616 [get_ports {io_ddrMasters_0_w_ready}]
set_output_delay -clock io_ddrMasters_0_clk -reference_pin [get_ports {io_ddrMasters_0_clk~CLKOUT~38~2}] -max 0.118 [get_ports {io_ddrMasters_0_w_valid}]
set_output_delay -clock io_ddrMasters_0_clk -reference_pin [get_ports {io_ddrMasters_0_clk~CLKOUT~38~2}] -min -0.038 [get_ports {io_ddrMasters_0_w_valid}]
set_output_delay -clock io_ddrMasters_0_clk -reference_pin [get_ports {io_ddrMasters_0_clk~CLKOUT~38~2}] -max 0.196 [get_ports {io_ddrMasters_0_b_ready}]
set_output_delay -clock io_ddrMasters_0_clk -reference_pin [get_ports {io_ddrMasters_0_clk~CLKOUT~38~2}] -min -0.012 [get_ports {io_ddrMasters_0_b_ready}]
set_input_delay -clock io_ddrMasters_0_clk -reference_pin [get_ports {io_ddrMasters_0_clk~CLKOUT~38~2}] -max 0.991 [get_ports {io_ddrMasters_0_b_valid}]
set_input_delay -clock io_ddrMasters_0_clk -reference_pin [get_ports {io_ddrMasters_0_clk~CLKOUT~38~2}] -min 0.514 [get_ports {io_ddrMasters_0_b_valid}]
set_output_delay -clock io_peripheralClk -reference_pin [get_ports {io_peripheralClk~CLKOUT~42~2}] -max 0.766 [get_ports {axiAInterrupt}]
set_output_delay -clock io_peripheralClk -reference_pin [get_ports {io_peripheralClk~CLKOUT~42~2}] -min 0.322 [get_ports {axiAInterrupt}]
set_input_delay -clock io_peripheralClk -reference_pin [get_ports {io_peripheralClk~CLKOUT~42~2}] -max 1.089 [get_ports {axiA_araddr[*]}]
set_input_delay -clock io_peripheralClk -reference_pin [get_ports {io_peripheralClk~CLKOUT~42~2}] -min 0.425 [get_ports {axiA_araddr[*]}]
set_input_delay -clock io_peripheralClk -reference_pin [get_ports {io_peripheralClk~CLKOUT~42~2}] -max 1.134 [get_ports {axiA_arlen[*]}]
set_input_delay -clock io_peripheralClk -reference_pin [get_ports {io_peripheralClk~CLKOUT~42~2}] -min 0.484 [get_ports {axiA_arlen[*]}]
set_output_delay -clock io_peripheralClk -reference_pin [get_ports {io_peripheralClk~CLKOUT~42~2}] -max 0.285 [get_ports {axiA_arready}]
set_output_delay -clock io_peripheralClk -reference_pin [get_ports {io_peripheralClk~CLKOUT~42~2}] -min 0.074 [get_ports {axiA_arready}]
set_input_delay -clock io_peripheralClk -reference_pin [get_ports {io_peripheralClk~CLKOUT~42~2}] -max 0.824 [get_ports {axiA_arvalid}]
set_input_delay -clock io_peripheralClk -reference_pin [get_ports {io_peripheralClk~CLKOUT~42~2}] -min 0.444 [get_ports {axiA_arvalid}]
set_output_delay -clock io_peripheralClk -reference_pin [get_ports {io_peripheralClk~CLKOUT~42~2}] -max 0.660 [get_ports {axiA_rdata[*]}]
set_output_delay -clock io_peripheralClk -reference_pin [get_ports {io_peripheralClk~CLKOUT~42~2}] -min 0.018 [get_ports {axiA_rdata[*]}]
set_output_delay -clock io_peripheralClk -reference_pin [get_ports {io_peripheralClk~CLKOUT~42~2}] -max 0.384 [get_ports {axiA_rlast}]
set_output_delay -clock io_peripheralClk -reference_pin [get_ports {io_peripheralClk~CLKOUT~42~2}] -min 0.068 [get_ports {axiA_rlast}]
set_input_delay -clock io_peripheralClk -reference_pin [get_ports {io_peripheralClk~CLKOUT~42~2}] -max 1.305 [get_ports {axiA_rready}]
set_input_delay -clock io_peripheralClk -reference_pin [get_ports {io_peripheralClk~CLKOUT~42~2}] -min 0.647 [get_ports {axiA_rready}]
set_output_delay -clock io_peripheralClk -reference_pin [get_ports {io_peripheralClk~CLKOUT~42~2}] -max 0.460 [get_ports {axiA_rresp[*]}]
set_output_delay -clock io_peripheralClk -reference_pin [get_ports {io_peripheralClk~CLKOUT~42~2}] -min 0.113 [get_ports {axiA_rresp[*]}]
set_output_delay -clock io_peripheralClk -reference_pin [get_ports {io_peripheralClk~CLKOUT~42~2}] -max 0.344 [get_ports {axiA_rvalid}]
set_output_delay -clock io_peripheralClk -reference_pin [get_ports {io_peripheralClk~CLKOUT~42~2}] -min 0.071 [get_ports {axiA_rvalid}]
set_input_delay -clock io_peripheralClk -reference_pin [get_ports {io_peripheralClk~CLKOUT~42~2}] -max 0.710 [get_ports {axiA_awaddr[*]}]
set_input_delay -clock io_peripheralClk -reference_pin [get_ports {io_peripheralClk~CLKOUT~42~2}] -min 0.344 [get_ports {axiA_awaddr[*]}]
set_input_delay -clock io_peripheralClk -reference_pin [get_ports {io_peripheralClk~CLKOUT~42~2}] -max 0.753 [get_ports {axiA_awlen[*]}]
set_input_delay -clock io_peripheralClk -reference_pin [get_ports {io_peripheralClk~CLKOUT~42~2}] -min 0.363 [get_ports {axiA_awlen[*]}]
set_output_delay -clock io_peripheralClk -reference_pin [get_ports {io_peripheralClk~CLKOUT~42~2}] -max 0.156 [get_ports {axiA_awready}]
set_output_delay -clock io_peripheralClk -reference_pin [get_ports {io_peripheralClk~CLKOUT~42~2}] -min -0.017 [get_ports {axiA_awready}]
set_input_delay -clock io_peripheralClk -reference_pin [get_ports {io_peripheralClk~CLKOUT~42~2}] -max 0.674 [get_ports {axiA_awvalid}]
set_input_delay -clock io_peripheralClk -reference_pin [get_ports {io_peripheralClk~CLKOUT~42~2}] -min 0.354 [get_ports {axiA_awvalid}]
set_input_delay -clock io_peripheralClk -reference_pin [get_ports {io_peripheralClk~CLKOUT~42~2}] -max 1.000 [get_ports {axiA_wdata[*]}]
set_input_delay -clock io_peripheralClk -reference_pin [get_ports {io_peripheralClk~CLKOUT~42~2}] -min 0.373 [get_ports {axiA_wdata[*]}]
set_input_delay -clock io_peripheralClk -reference_pin [get_ports {io_peripheralClk~CLKOUT~42~2}] -max 0.933 [get_ports {axiA_wlast}]
set_input_delay -clock io_peripheralClk -reference_pin [get_ports {io_peripheralClk~CLKOUT~42~2}] -min 0.494 [get_ports {axiA_wlast}]
set_output_delay -clock io_peripheralClk -reference_pin [get_ports {io_peripheralClk~CLKOUT~42~2}] -max 0.155 [get_ports {axiA_wready}]
set_output_delay -clock io_peripheralClk -reference_pin [get_ports {io_peripheralClk~CLKOUT~42~2}] -min -0.018 [get_ports {axiA_wready}]
set_input_delay -clock io_peripheralClk -reference_pin [get_ports {io_peripheralClk~CLKOUT~42~2}] -max 1.021 [get_ports {axiA_wstrb[*]}]
set_input_delay -clock io_peripheralClk -reference_pin [get_ports {io_peripheralClk~CLKOUT~42~2}] -min 0.491 [get_ports {axiA_wstrb[*]}]
set_input_delay -clock io_peripheralClk -reference_pin [get_ports {io_peripheralClk~CLKOUT~42~2}] -max 0.799 [get_ports {axiA_wvalid}]
set_input_delay -clock io_peripheralClk -reference_pin [get_ports {io_peripheralClk~CLKOUT~42~2}] -min 0.414 [get_ports {axiA_wvalid}]
set_input_delay -clock io_peripheralClk -reference_pin [get_ports {io_peripheralClk~CLKOUT~42~2}] -max 0.944 [get_ports {axiA_bready}]
set_input_delay -clock io_peripheralClk -reference_pin [get_ports {io_peripheralClk~CLKOUT~42~2}] -min 0.494 [get_ports {axiA_bready}]
set_output_delay -clock io_peripheralClk -reference_pin [get_ports {io_peripheralClk~CLKOUT~42~2}] -max 0.315 [get_ports {axiA_bresp[*]}]
set_output_delay -clock io_peripheralClk -reference_pin [get_ports {io_peripheralClk~CLKOUT~42~2}] -min 0.064 [get_ports {axiA_bresp[*]}]
set_output_delay -clock io_peripheralClk -reference_pin [get_ports {io_peripheralClk~CLKOUT~42~2}] -max 0.251 [get_ports {axiA_bvalid}]
set_output_delay -clock io_peripheralClk -reference_pin [get_ports {io_peripheralClk~CLKOUT~42~2}] -min 0.052 [get_ports {axiA_bvalid}]
set_input_delay -clock io_peripheralClk -reference_pin [get_ports {io_peripheralClk~CLKOUT~42~2}] -max 0.730 [get_ports {io_peripheralReset}]
set_input_delay -clock io_peripheralClk -reference_pin [get_ports {io_peripheralClk~CLKOUT~42~2}] -min 0.386 [get_ports {io_peripheralReset}]
set_output_delay -clock io_cfuClk -reference_pin [get_ports {io_cfuClk~CLKOUT~3~1}] -max 0.777 [get_ports {cpu0_customInstruction_cmd_ready}]
set_output_delay -clock io_cfuClk -reference_pin [get_ports {io_cfuClk~CLKOUT~3~1}] -min 0.246 [get_ports {cpu0_customInstruction_cmd_ready}]
set_input_delay -clock io_cfuClk -reference_pin [get_ports {io_cfuClk~CLKOUT~3~1}] -max 1.488 [get_ports {cpu0_customInstruction_cmd_valid}]
set_input_delay -clock io_cfuClk -reference_pin [get_ports {io_cfuClk~CLKOUT~3~1}] -min 0.776 [get_ports {cpu0_customInstruction_cmd_valid}]
set_input_delay -clock io_cfuClk -reference_pin [get_ports {io_cfuClk~CLKOUT~3~1}] -max 1.500 [get_ports {cpu0_customInstruction_function_id[*]}]
set_input_delay -clock io_cfuClk -reference_pin [get_ports {io_cfuClk~CLKOUT~3~1}] -min 0.637 [get_ports {cpu0_customInstruction_function_id[*]}]
set_input_delay -clock io_cfuClk -reference_pin [get_ports {io_cfuClk~CLKOUT~3~1}] -max 1.545 [get_ports {cpu0_customInstruction_inputs_0[*]}]
set_input_delay -clock io_cfuClk -reference_pin [get_ports {io_cfuClk~CLKOUT~3~1}] -min 0.612 [get_ports {cpu0_customInstruction_inputs_0[*]}]
set_input_delay -clock io_cfuClk -reference_pin [get_ports {io_cfuClk~CLKOUT~3~1}] -max 1.428 [get_ports {cpu0_customInstruction_inputs_1[*]}]
set_input_delay -clock io_cfuClk -reference_pin [get_ports {io_cfuClk~CLKOUT~3~1}] -min 0.625 [get_ports {cpu0_customInstruction_inputs_1[*]}]
set_output_delay -clock io_cfuClk -reference_pin [get_ports {io_cfuClk~CLKOUT~3~1}] -max 0.844 [get_ports {cpu0_customInstruction_outputs_0[*]}]
set_output_delay -clock io_cfuClk -reference_pin [get_ports {io_cfuClk~CLKOUT~3~1}] -min 0.147 [get_ports {cpu0_customInstruction_outputs_0[*]}]
set_input_delay -clock io_cfuClk -reference_pin [get_ports {io_cfuClk~CLKOUT~3~1}] -max 1.401 [get_ports {cpu0_customInstruction_rsp_ready}]
set_input_delay -clock io_cfuClk -reference_pin [get_ports {io_cfuClk~CLKOUT~3~1}] -min 0.746 [get_ports {cpu0_customInstruction_rsp_ready}]
set_output_delay -clock io_cfuClk -reference_pin [get_ports {io_cfuClk~CLKOUT~3~1}] -max 0.864 [get_ports {cpu0_customInstruction_rsp_valid}]
set_output_delay -clock io_cfuClk -reference_pin [get_ports {io_cfuClk~CLKOUT~3~1}] -min 0.251 [get_ports {cpu0_customInstruction_rsp_valid}]
set_output_delay -clock io_cfuClk -reference_pin [get_ports {io_cfuClk~CLKOUT~3~1}] -max 0.947 [get_ports {cpu1_customInstruction_cmd_ready}]
set_output_delay -clock io_cfuClk -reference_pin [get_ports {io_cfuClk~CLKOUT~3~1}] -min 0.300 [get_ports {cpu1_customInstruction_cmd_ready}]
set_input_delay -clock io_cfuClk -reference_pin [get_ports {io_cfuClk~CLKOUT~3~1}] -max 1.580 [get_ports {cpu1_customInstruction_cmd_valid}]
set_input_delay -clock io_cfuClk -reference_pin [get_ports {io_cfuClk~CLKOUT~3~1}] -min 0.804 [get_ports {cpu1_customInstruction_cmd_valid}]
set_input_delay -clock io_cfuClk -reference_pin [get_ports {io_cfuClk~CLKOUT~3~1}] -max 1.849 [get_ports {cpu1_customInstruction_function_id[*]}]
set_input_delay -clock io_cfuClk -reference_pin [get_ports {io_cfuClk~CLKOUT~3~1}] -min 0.720 [get_ports {cpu1_customInstruction_function_id[*]}]
set_input_delay -clock io_cfuClk -reference_pin [get_ports {io_cfuClk~CLKOUT~3~1}] -max 1.956 [get_ports {cpu1_customInstruction_inputs_0[*]}]
set_input_delay -clock io_cfuClk -reference_pin [get_ports {io_cfuClk~CLKOUT~3~1}] -min 0.752 [get_ports {cpu1_customInstruction_inputs_0[*]}]
set_input_delay -clock io_cfuClk -reference_pin [get_ports {io_cfuClk~CLKOUT~3~1}] -max 1.810 [get_ports {cpu1_customInstruction_inputs_1[*]}]
set_input_delay -clock io_cfuClk -reference_pin [get_ports {io_cfuClk~CLKOUT~3~1}] -min 0.748 [get_ports {cpu1_customInstruction_inputs_1[*]}]
set_output_delay -clock io_cfuClk -reference_pin [get_ports {io_cfuClk~CLKOUT~3~1}] -max 1.052 [get_ports {cpu1_customInstruction_outputs_0[*]}]
set_output_delay -clock io_cfuClk -reference_pin [get_ports {io_cfuClk~CLKOUT~3~1}] -min 0.169 [get_ports {cpu1_customInstruction_outputs_0[*]}]
set_input_delay -clock io_cfuClk -reference_pin [get_ports {io_cfuClk~CLKOUT~3~1}] -max 1.643 [get_ports {cpu1_customInstruction_rsp_ready}]
set_input_delay -clock io_cfuClk -reference_pin [get_ports {io_cfuClk~CLKOUT~3~1}] -min 0.869 [get_ports {cpu1_customInstruction_rsp_ready}]
set_output_delay -clock io_cfuClk -reference_pin [get_ports {io_cfuClk~CLKOUT~3~1}] -max 0.800 [get_ports {cpu1_customInstruction_rsp_valid}]
set_output_delay -clock io_cfuClk -reference_pin [get_ports {io_cfuClk~CLKOUT~3~1}] -min 0.278 [get_ports {cpu1_customInstruction_rsp_valid}]
set_output_delay -clock io_cfuClk -reference_pin [get_ports {io_cfuClk~CLKOUT~3~1}] -max 0.863 [get_ports {cpu2_customInstruction_cmd_ready}]
set_output_delay -clock io_cfuClk -reference_pin [get_ports {io_cfuClk~CLKOUT~3~1}] -min 0.325 [get_ports {cpu2_customInstruction_cmd_ready}]
set_input_delay -clock io_cfuClk -reference_pin [get_ports {io_cfuClk~CLKOUT~3~1}] -max 1.757 [get_ports {cpu2_customInstruction_cmd_valid}]
set_input_delay -clock io_cfuClk -reference_pin [get_ports {io_cfuClk~CLKOUT~3~1}] -min 0.841 [get_ports {cpu2_customInstruction_cmd_valid}]
set_input_delay -clock io_cfuClk -reference_pin [get_ports {io_cfuClk~CLKOUT~3~1}] -max 1.667 [get_ports {cpu2_customInstruction_function_id[*]}]
set_input_delay -clock io_cfuClk -reference_pin [get_ports {io_cfuClk~CLKOUT~3~1}] -min 0.801 [get_ports {cpu2_customInstruction_function_id[*]}]
set_input_delay -clock io_cfuClk -reference_pin [get_ports {io_cfuClk~CLKOUT~3~1}] -max 1.848 [get_ports {cpu2_customInstruction_inputs_0[*]}]
set_input_delay -clock io_cfuClk -reference_pin [get_ports {io_cfuClk~CLKOUT~3~1}] -min 0.750 [get_ports {cpu2_customInstruction_inputs_0[*]}]
set_input_delay -clock io_cfuClk -reference_pin [get_ports {io_cfuClk~CLKOUT~3~1}] -max 1.750 [get_ports {cpu2_customInstruction_inputs_1[*]}]
set_input_delay -clock io_cfuClk -reference_pin [get_ports {io_cfuClk~CLKOUT~3~1}] -min 0.762 [get_ports {cpu2_customInstruction_inputs_1[*]}]
set_output_delay -clock io_cfuClk -reference_pin [get_ports {io_cfuClk~CLKOUT~3~1}] -max 0.950 [get_ports {cpu2_customInstruction_outputs_0[*]}]
set_output_delay -clock io_cfuClk -reference_pin [get_ports {io_cfuClk~CLKOUT~3~1}] -min 0.234 [get_ports {cpu2_customInstruction_outputs_0[*]}]
set_input_delay -clock io_cfuClk -reference_pin [get_ports {io_cfuClk~CLKOUT~3~1}] -max 1.745 [get_ports {cpu2_customInstruction_rsp_ready}]
set_input_delay -clock io_cfuClk -reference_pin [get_ports {io_cfuClk~CLKOUT~3~1}] -min 0.931 [get_ports {cpu2_customInstruction_rsp_ready}]
set_output_delay -clock io_cfuClk -reference_pin [get_ports {io_cfuClk~CLKOUT~3~1}] -max 0.726 [get_ports {cpu2_customInstruction_rsp_valid}]
set_output_delay -clock io_cfuClk -reference_pin [get_ports {io_cfuClk~CLKOUT~3~1}] -min 0.277 [get_ports {cpu2_customInstruction_rsp_valid}]
set_output_delay -clock io_cfuClk -reference_pin [get_ports {io_cfuClk~CLKOUT~3~1}] -max 0.730 [get_ports {cpu3_customInstruction_cmd_ready}]
set_output_delay -clock io_cfuClk -reference_pin [get_ports {io_cfuClk~CLKOUT~3~1}] -min 0.297 [get_ports {cpu3_customInstruction_cmd_ready}]
set_input_delay -clock io_cfuClk -reference_pin [get_ports {io_cfuClk~CLKOUT~3~1}] -max 1.529 [get_ports {cpu3_customInstruction_cmd_valid}]
set_input_delay -clock io_cfuClk -reference_pin [get_ports {io_cfuClk~CLKOUT~3~1}] -min 0.830 [get_ports {cpu3_customInstruction_cmd_valid}]
set_input_delay -clock io_cfuClk -reference_pin [get_ports {io_cfuClk~CLKOUT~3~1}] -max 1.677 [get_ports {cpu3_customInstruction_function_id[*]}]
set_input_delay -clock io_cfuClk -reference_pin [get_ports {io_cfuClk~CLKOUT~3~1}] -min 0.788 [get_ports {cpu3_customInstruction_function_id[*]}]
set_input_delay -clock io_cfuClk -reference_pin [get_ports {io_cfuClk~CLKOUT~3~1}] -max 1.677 [get_ports {cpu3_customInstruction_inputs_0[*]}]
set_input_delay -clock io_cfuClk -reference_pin [get_ports {io_cfuClk~CLKOUT~3~1}] -min 0.770 [get_ports {cpu3_customInstruction_inputs_0[*]}]
set_input_delay -clock io_cfuClk -reference_pin [get_ports {io_cfuClk~CLKOUT~3~1}] -max 1.741 [get_ports {cpu3_customInstruction_inputs_1[*]}]
set_input_delay -clock io_cfuClk -reference_pin [get_ports {io_cfuClk~CLKOUT~3~1}] -min 0.769 [get_ports {cpu3_customInstruction_inputs_1[*]}]
set_output_delay -clock io_cfuClk -reference_pin [get_ports {io_cfuClk~CLKOUT~3~1}] -max 1.074 [get_ports {cpu3_customInstruction_outputs_0[*]}]
set_output_delay -clock io_cfuClk -reference_pin [get_ports {io_cfuClk~CLKOUT~3~1}] -min 0.200 [get_ports {cpu3_customInstruction_outputs_0[*]}]
set_input_delay -clock io_cfuClk -reference_pin [get_ports {io_cfuClk~CLKOUT~3~1}] -max 1.685 [get_ports {cpu3_customInstruction_rsp_ready}]
set_input_delay -clock io_cfuClk -reference_pin [get_ports {io_cfuClk~CLKOUT~3~1}] -min 0.913 [get_ports {cpu3_customInstruction_rsp_ready}]
set_output_delay -clock io_cfuClk -reference_pin [get_ports {io_cfuClk~CLKOUT~3~1}] -max 0.756 [get_ports {cpu3_customInstruction_rsp_valid}]
set_output_delay -clock io_cfuClk -reference_pin [get_ports {io_cfuClk~CLKOUT~3~1}] -min 0.319 [get_ports {cpu3_customInstruction_rsp_valid}]
set_output_delay -clock jtagCtrl_tck -reference_pin [get_ports {jtagCtrl_tck~CLKOUT~44~1}] -max 1.058 [get_ports {jtagCtrl_capture}]
set_output_delay -clock jtagCtrl_tck -reference_pin [get_ports {jtagCtrl_tck~CLKOUT~44~1}] -min 0.420 [get_ports {jtagCtrl_capture}]
set_output_delay -clock jtagCtrl_tck -reference_pin [get_ports {jtagCtrl_tck~CLKOUT~44~1}] -max 1.423 [get_ports {jtagCtrl_enable}]
set_output_delay -clock jtagCtrl_tck -reference_pin [get_ports {jtagCtrl_tck~CLKOUT~44~1}] -min 0.374 [get_ports {jtagCtrl_enable}]
set_output_delay -clock jtagCtrl_tck -reference_pin [get_ports {jtagCtrl_tck~CLKOUT~44~1}] -max 1.313 [get_ports {jtagCtrl_reset}]
set_output_delay -clock jtagCtrl_tck -reference_pin [get_ports {jtagCtrl_tck~CLKOUT~44~1}] -min 0.436 [get_ports {jtagCtrl_reset}]
set_output_delay -clock jtagCtrl_tck -reference_pin [get_ports {jtagCtrl_tck~CLKOUT~44~1}] -max 1.379 [get_ports {jtagCtrl_shift}]
set_output_delay -clock jtagCtrl_tck -reference_pin [get_ports {jtagCtrl_tck~CLKOUT~44~1}] -min 0.399 [get_ports {jtagCtrl_shift}]
set_output_delay -clock jtagCtrl_tck -reference_pin [get_ports {jtagCtrl_tck~CLKOUT~44~1}] -max 0.687 [get_ports {jtagCtrl_tdi}]
set_output_delay -clock jtagCtrl_tck -reference_pin [get_ports {jtagCtrl_tck~CLKOUT~44~1}] -min 0.304 [get_ports {jtagCtrl_tdi}]
set_input_delay -clock jtagCtrl_tck -reference_pin [get_ports {jtagCtrl_tck~CLKOUT~44~1}] -max 2.055 [get_ports {jtagCtrl_tdo}]
set_input_delay -clock jtagCtrl_tck -reference_pin [get_ports {jtagCtrl_tck~CLKOUT~44~1}] -min 0.906 [get_ports {jtagCtrl_tdo}]
set_output_delay -clock jtagCtrl_tck -reference_pin [get_ports {jtagCtrl_tck~CLKOUT~44~1}] -max 1.351 [get_ports {jtagCtrl_update}]
set_output_delay -clock jtagCtrl_tck -reference_pin [get_ports {jtagCtrl_tck~CLKOUT~44~1}] -min 0.425 [get_ports {jtagCtrl_update}]
# Clock Latency Constraints
############################
# set_clock_latency -source -setup <board_max + 1.177> [get_ports {io_sysFbClk}]
# set_clock_latency -source -hold <board_min + 0.785> [get_ports {io_sysFbClk}]
# set_clock_latency -source -setup <board_max + 1.177> [get_ports {io_systemClk}]
# set_clock_latency -source -hold <board_min + 0.785> [get_ports {io_systemClk}]
# set_clock_latency -source -setup <board_max + 1.177> [get_ports {io_memoryClk}]
# set_clock_latency -source -hold <board_min + 0.785> [get_ports {io_memoryClk}]
# set_clock_latency -source -setup <board_max + 0.828> [get_ports {io_memFbClk}]
# set_clock_latency -source -hold <board_min + 0.552> [get_ports {io_memFbClk}]
# set_clock_latency -source -setup <board_max + 0.828> [get_ports {io_peripheralClk}]
# set_clock_latency -source -hold <board_min + 0.552> [get_ports {io_peripheralClk}]
# set_clock_latency -source -setup <board_max + 0.828> [get_ports {io_ddrMasters_0_clk}]
# set_clock_latency -source -hold <board_min + 0.552> [get_ports {io_ddrMasters_0_clk}]
# set_clock_latency -source -setup <board_max + 0.828> [get_ports {io_cfuClk}]
# set_clock_latency -source -hold <board_min + 0.552> [get_ports {io_cfuClk}]

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// =============================================================================
// Generated by efx_ipmgr
// Version: 2026.1.132
// IP Version: 1.23.0
// =============================================================================
////////////////////////////////////////////////////////////////////////////////
// Copyright (C) 2013-2026 Efinix Inc. All rights reserved.
//
// This document contains proprietary information which is
// protected by copyright. All rights are reserved. This notice
// refers to original work by Efinix, Inc. which may be derivitive
// of other work distributed under license of the authors. In the
// case of derivative work, nothing in this notice overrides the
// original author's license agreement. Where applicable, the
// original license agreement is included in it's original
// unmodified form immediately below this header.
//
// WARRANTY DISCLAIMER.
// THE DESIGN, CODE, OR INFORMATION ARE PROVIDED “AS IS” AND
// EFINIX MAKES NO WARRANTIES, EXPRESS OR IMPLIED WITH
// RESPECT THERETO, AND EXPRESSLY DISCLAIMS ANY IMPLIED WARRANTIES,
// INCLUDING, WITHOUT LIMITATION, THE IMPLIED WARRANTIES OF
// MERCHANTABILITY, NON-INFRINGEMENT AND FITNESS FOR A PARTICULAR
// PURPOSE. SOME STATES DO NOT ALLOW EXCLUSIONS OF AN IMPLIED
// WARRANTY, SO THIS DISCLAIMER MAY NOT APPLY TO LICENSEE.
//
// LIMITATION OF LIABILITY.
// NOTWITHSTANDING ANYTHING TO THE CONTRARY, EXCEPT FOR BODILY
// INJURY, EFINIX SHALL NOT BE LIABLE WITH RESPECT TO ANY SUBJECT
// MATTER OF THIS AGREEMENT UNDER TORT, CONTRACT, STRICT LIABILITY
// OR ANY OTHER LEGAL OR EQUITABLE THEORY (I) FOR ANY INDIRECT,
// SPECIAL, INCIDENTAL, EXEMPLARY OR CONSEQUENTIAL DAMAGES OF ANY
// CHARACTER INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF
// GOODWILL, DATA OR PROFIT, WORK STOPPAGE, OR COMPUTER FAILURE OR
// MALFUNCTION, OR IN ANY EVENT (II) FOR ANY AMOUNT IN EXCESS, IN
// THE AGGREGATE, OF THE FEE PAID BY LICENSEE TO EFINIX HEREUNDER
// (OR, IF THE FEE HAS BEEN WAIVED, $100), EVEN IF EFINIX SHALL HAVE
// BEEN INFORMED OF THE POSSIBILITY OF SUCH DAMAGES. SOME STATES DO
// NOT ALLOW THE EXCLUSION OR LIMITATION OF INCIDENTAL OR
// CONSEQUENTIAL DAMAGES, SO THIS LIMITATION AND EXCLUSION MAY NOT
// APPLY TO LICENSEE.
//
////////////////////////////////////////////////////////////////////////////////
localparam PERI_FREQ = 200;

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// =============================================================================
// Generated by efx_ipmgr
// Version: 2026.1.132
// IP Version: 1.23.0
// =============================================================================
////////////////////////////////////////////////////////////////////////////////
// Copyright (C) 2013-2026 Efinix Inc. All rights reserved.
//
// This document contains proprietary information which is
// protected by copyright. All rights are reserved. This notice
// refers to original work by Efinix, Inc. which may be derivitive
// of other work distributed under license of the authors. In the
// case of derivative work, nothing in this notice overrides the
// original author's license agreement. Where applicable, the
// original license agreement is included in it's original
// unmodified form immediately below this header.
//
// WARRANTY DISCLAIMER.
// THE DESIGN, CODE, OR INFORMATION ARE PROVIDED “AS IS” AND
// EFINIX MAKES NO WARRANTIES, EXPRESS OR IMPLIED WITH
// RESPECT THERETO, AND EXPRESSLY DISCLAIMS ANY IMPLIED WARRANTIES,
// INCLUDING, WITHOUT LIMITATION, THE IMPLIED WARRANTIES OF
// MERCHANTABILITY, NON-INFRINGEMENT AND FITNESS FOR A PARTICULAR
// PURPOSE. SOME STATES DO NOT ALLOW EXCLUSIONS OF AN IMPLIED
// WARRANTY, SO THIS DISCLAIMER MAY NOT APPLY TO LICENSEE.
//
// LIMITATION OF LIABILITY.
// NOTWITHSTANDING ANYTHING TO THE CONTRARY, EXCEPT FOR BODILY
// INJURY, EFINIX SHALL NOT BE LIABLE WITH RESPECT TO ANY SUBJECT
// MATTER OF THIS AGREEMENT UNDER TORT, CONTRACT, STRICT LIABILITY
// OR ANY OTHER LEGAL OR EQUITABLE THEORY (I) FOR ANY INDIRECT,
// SPECIAL, INCIDENTAL, EXEMPLARY OR CONSEQUENTIAL DAMAGES OF ANY
// CHARACTER INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF
// GOODWILL, DATA OR PROFIT, WORK STOPPAGE, OR COMPUTER FAILURE OR
// MALFUNCTION, OR IN ANY EVENT (II) FOR ANY AMOUNT IN EXCESS, IN
// THE AGGREGATE, OF THE FEE PAID BY LICENSEE TO EFINIX HEREUNDER
// (OR, IF THE FEE HAS BEEN WAIVED, $100), EVEN IF EFINIX SHALL HAVE
// BEEN INFORMED OF THE POSSIBILITY OF SUCH DAMAGES. SOME STATES DO
// NOT ALLOW THE EXCLUSION OR LIMITATION OF INCIDENTAL OR
// CONSEQUENTIAL DAMAGES, SO THIS LIMITATION AND EXCLUSION MAY NOT
// APPLY TO LICENSEE.
//
////////////////////////////////////////////////////////////////////////////////
EfxSapphireHpSoc_slb u_EfxSapphireHpSoc_slb
(
.io_peripheralClk ( io_peripheralClk ),
.io_peripheralReset ( io_peripheralReset ),
.io_asyncReset ( io_asyncReset ),
.io_gpio_sw_n ( io_gpio_sw_n ),
.pll_peripheral_locked ( pll_peripheral_locked ),
.pll_system_locked ( pll_system_locked ),
.jtagCtrl_capture ( jtagCtrl_capture ),
.jtagCtrl_enable ( jtagCtrl_enable ),
.jtagCtrl_reset ( jtagCtrl_reset ),
.jtagCtrl_shift ( jtagCtrl_shift ),
.jtagCtrl_tdi ( jtagCtrl_tdi ),
.jtagCtrl_tdo ( jtagCtrl_tdo ),
.jtagCtrl_update ( jtagCtrl_update ),
.ut_jtagCtrl_capture ( ut_jtagCtrl_capture ),
.ut_jtagCtrl_enable ( ut_jtagCtrl_enable ),
.ut_jtagCtrl_reset ( ut_jtagCtrl_reset ),
.ut_jtagCtrl_shift ( ut_jtagCtrl_shift ),
.ut_jtagCtrl_tdi ( ut_jtagCtrl_tdi ),
.ut_jtagCtrl_tdo ( ut_jtagCtrl_tdo ),
.ut_jtagCtrl_update ( ut_jtagCtrl_update ),
.system_spi_0_io_data_0_read ( system_spi_0_io_data_0_read ),
.system_spi_0_io_data_0_write ( system_spi_0_io_data_0_write ),
.system_spi_0_io_data_0_writeEnable ( system_spi_0_io_data_0_writeEnable ),
.system_spi_0_io_data_1_read ( system_spi_0_io_data_1_read ),
.system_spi_0_io_data_1_write ( system_spi_0_io_data_1_write ),
.system_spi_0_io_data_1_writeEnable ( system_spi_0_io_data_1_writeEnable ),
.system_spi_0_io_data_2_read ( system_spi_0_io_data_2_read ),
.system_spi_0_io_data_2_write ( system_spi_0_io_data_2_write ),
.system_spi_0_io_data_2_writeEnable ( system_spi_0_io_data_2_writeEnable ),
.system_spi_0_io_data_3_read ( system_spi_0_io_data_3_read ),
.system_spi_0_io_data_3_write ( system_spi_0_io_data_3_write ),
.system_spi_0_io_data_3_writeEnable ( system_spi_0_io_data_3_writeEnable ),
.system_spi_0_io_sclk_write ( system_spi_0_io_sclk_write ),
.system_spi_0_io_ss ( system_spi_0_io_ss ),
.system_uart_0_io_rxd ( system_uart_0_io_rxd ),
.system_uart_0_io_txd ( system_uart_0_io_txd ),
.system_i2c_0_io_scl_read ( system_i2c_0_io_scl_read ),
.system_i2c_0_io_scl_write ( system_i2c_0_io_scl_write ),
.system_i2c_0_io_sda_read ( system_i2c_0_io_sda_read ),
.system_gpio_0_io_read ( system_gpio_0_io_read ),
.system_gpio_0_io_write ( system_gpio_0_io_write ),
.system_gpio_0_io_writeEnable ( system_gpio_0_io_writeEnable ),
.cfg_done ( cfg_done ),
.cfg_start ( cfg_start ),
.cfg_sel ( cfg_sel ),
.cfg_reset ( cfg_reset ),
.axiAInterrupt ( axiAInterrupt ),
.axiA_awaddr ( axiA_awaddr ),
.axiA_awlen ( axiA_awlen ),
.axiA_awsize ( axiA_awsize ),
.axiA_awburst ( axiA_awburst ),
.axiA_awlock ( axiA_awlock ),
.axiA_awcache ( axiA_awcache ),
.axiA_awprot ( axiA_awprot ),
.axiA_awqos ( axiA_awqos ),
.axiA_awregion ( axiA_awregion ),
.axiA_awvalid ( axiA_awvalid ),
.axiA_awready ( axiA_awready ),
.axiA_wdata ( axiA_wdata ),
.axiA_wstrb ( axiA_wstrb ),
.axiA_wvalid ( axiA_wvalid ),
.axiA_wlast ( axiA_wlast ),
.axiA_wready ( axiA_wready ),
.axiA_bresp ( axiA_bresp ),
.axiA_bvalid ( axiA_bvalid ),
.axiA_bready ( axiA_bready ),
.axiA_araddr ( axiA_araddr ),
.axiA_arlen ( axiA_arlen ),
.axiA_arsize ( axiA_arsize ),
.axiA_arburst ( axiA_arburst ),
.axiA_arlock ( axiA_arlock ),
.axiA_arcache ( axiA_arcache ),
.axiA_arprot ( axiA_arprot ),
.axiA_arqos ( axiA_arqos ),
.axiA_arregion ( axiA_arregion ),
.axiA_arvalid ( axiA_arvalid ),
.axiA_arready ( axiA_arready ),
.axiA_rdata ( axiA_rdata ),
.axiA_rresp ( axiA_rresp ),
.axiA_rlast ( axiA_rlast ),
.axiA_rvalid ( axiA_rvalid ),
.axiA_rready ( axiA_rready ),
.userInterruptA ( userInterruptA ),
.userInterruptB ( userInterruptB ),
.userInterruptC ( userInterruptC ),
.userInterruptD ( userInterruptD ),
.userInterruptE ( userInterruptE ),
.userInterruptF ( userInterruptF ),
.io_apbSlave_0_PADDR ( io_apbSlave_0_PADDR ),
.io_apbSlave_0_PENABLE ( io_apbSlave_0_PENABLE ),
.io_apbSlave_0_PRDATA ( io_apbSlave_0_PRDATA ),
.io_apbSlave_0_PREADY ( io_apbSlave_0_PREADY ),
.io_apbSlave_0_PSEL ( io_apbSlave_0_PSEL ),
.io_apbSlave_0_PSLVERROR ( io_apbSlave_0_PSLVERROR ),
.io_apbSlave_0_PWDATA ( io_apbSlave_0_PWDATA ),
.io_apbSlave_0_PWRITE ( io_apbSlave_0_PWRITE ),
.system_i2c_0_io_sda_write ( system_i2c_0_io_sda_write ),
.system_i2c_0_io_sda_writeEnable ( system_i2c_0_io_sda_writeEnable ),
.system_i2c_0_io_scl_writeEnable ( system_i2c_0_io_scl_writeEnable ),
.system_watchdog_hardPanic_reset ( system_watchdog_hardPanic_reset )
);

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--------------------------------------------------------------------------------
-- Copyright (C) 2013-2026 Efinix Inc. All rights reserved.
--
-- This document contains proprietary information which is
-- protected by copyright. All rights are reserved. This notice
-- refers to original work by Efinix, Inc. which may be derivitive
-- of other work distributed under license of the authors. In the
-- case of derivative work, nothing in this notice overrides the
-- original author's license agreement. Where applicable, the
-- original license agreement is included in it's original
-- unmodified form immediately below this header.
--
-- WARRANTY DISCLAIMER.
-- THE DESIGN, CODE, OR INFORMATION ARE PROVIDED “AS IS” AND
-- EFINIX MAKES NO WARRANTIES, EXPRESS OR IMPLIED WITH
-- RESPECT THERETO, AND EXPRESSLY DISCLAIMS ANY IMPLIED WARRANTIES,
-- INCLUDING, WITHOUT LIMITATION, THE IMPLIED WARRANTIES OF
-- MERCHANTABILITY, NON-INFRINGEMENT AND FITNESS FOR A PARTICULAR
-- PURPOSE. SOME STATES DO NOT ALLOW EXCLUSIONS OF AN IMPLIED
-- WARRANTY, SO THIS DISCLAIMER MAY NOT APPLY TO LICENSEE.
--
-- LIMITATION OF LIABILITY.
-- NOTWITHSTANDING ANYTHING TO THE CONTRARY, EXCEPT FOR BODILY
-- INJURY, EFINIX SHALL NOT BE LIABLE WITH RESPECT TO ANY SUBJECT
-- MATTER OF THIS AGREEMENT UNDER TORT, CONTRACT, STRICT LIABILITY
-- OR ANY OTHER LEGAL OR EQUITABLE THEORY (I) FOR ANY INDIRECT,
-- SPECIAL, INCIDENTAL, EXEMPLARY OR CONSEQUENTIAL DAMAGES OF ANY
-- CHARACTER INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF
-- GOODWILL, DATA OR PROFIT, WORK STOPPAGE, OR COMPUTER FAILURE OR
-- MALFUNCTION, OR IN ANY EVENT (II) FOR ANY AMOUNT IN EXCESS, IN
-- THE AGGREGATE, OF THE FEE PAID BY LICENSEE TO EFINIX HEREUNDER
-- (OR, IF THE FEE HAS BEEN WAIVED, $100), EVEN IF EFINIX SHALL HAVE
-- BEEN INFORMED OF THE POSSIBILITY OF SUCH DAMAGES. SOME STATES DO
-- NOT ALLOW THE EXCLUSION OR LIMITATION OF INCIDENTAL OR
-- CONSEQUENTIAL DAMAGES, SO THIS LIMITATION AND EXCLUSION MAY NOT
-- APPLY TO LICENSEE.
--
--------------------------------------------------------------------------------
------------- Begin Cut here for COMPONENT Declaration ------
component EfxSapphireHpSoc_slb is
port (
io_peripheralClk : in std_logic;
io_peripheralReset : in std_logic;
io_asyncReset : out std_logic;
io_gpio_sw_n : in std_logic;
pll_peripheral_locked : in std_logic;
pll_system_locked : in std_logic;
jtagCtrl_capture : out std_logic;
jtagCtrl_enable : out std_logic;
jtagCtrl_reset : out std_logic;
jtagCtrl_shift : out std_logic;
jtagCtrl_tdi : out std_logic;
jtagCtrl_tdo : in std_logic;
jtagCtrl_update : out std_logic;
ut_jtagCtrl_capture : in std_logic;
ut_jtagCtrl_enable : in std_logic;
ut_jtagCtrl_reset : in std_logic;
ut_jtagCtrl_shift : in std_logic;
ut_jtagCtrl_tdi : in std_logic;
ut_jtagCtrl_tdo : out std_logic;
ut_jtagCtrl_update : in std_logic;
system_spi_0_io_data_0_read : in std_logic;
system_spi_0_io_data_0_write : out std_logic;
system_spi_0_io_data_0_writeEnable : out std_logic;
system_spi_0_io_data_1_read : in std_logic;
system_spi_0_io_data_1_write : out std_logic;
system_spi_0_io_data_1_writeEnable : out std_logic;
system_spi_0_io_data_2_read : in std_logic;
system_spi_0_io_data_2_write : out std_logic;
system_spi_0_io_data_2_writeEnable : out std_logic;
system_spi_0_io_data_3_read : in std_logic;
system_spi_0_io_data_3_write : out std_logic;
system_spi_0_io_data_3_writeEnable : out std_logic;
system_spi_0_io_sclk_write : out std_logic;
system_spi_0_io_ss : out std_logic_vector(3 downto 0);
system_uart_0_io_rxd : in std_logic;
system_uart_0_io_txd : out std_logic;
system_i2c_0_io_scl_read : in std_logic;
system_i2c_0_io_scl_write : out std_logic;
system_i2c_0_io_sda_read : in std_logic;
system_gpio_0_io_read : in std_logic_vector(3 downto 0);
system_gpio_0_io_write : out std_logic_vector(3 downto 0);
system_gpio_0_io_writeEnable : out std_logic_vector(3 downto 0);
cfg_done : in std_logic;
cfg_start : out std_logic;
cfg_sel : out std_logic;
cfg_reset : out std_logic;
axiAInterrupt : out std_logic;
axiA_awaddr : in std_logic_vector(31 downto 0);
axiA_awlen : in std_logic_vector(7 downto 0);
axiA_awsize : in std_logic_vector(2 downto 0);
axiA_awburst : in std_logic_vector(1 downto 0);
axiA_awlock : in std_logic;
axiA_awcache : in std_logic_vector(3 downto 0);
axiA_awprot : in std_logic_vector(2 downto 0);
axiA_awqos : in std_logic_vector(3 downto 0);
axiA_awregion : in std_logic_vector(3 downto 0);
axiA_awvalid : in std_logic;
axiA_awready : out std_logic;
axiA_wdata : in std_logic_vector(31 downto 0);
axiA_wstrb : in std_logic_vector(3 downto 0);
axiA_wvalid : in std_logic;
axiA_wlast : in std_logic;
axiA_wready : out std_logic;
axiA_bresp : out std_logic_vector(1 downto 0);
axiA_bvalid : out std_logic;
axiA_bready : in std_logic;
axiA_araddr : in std_logic_vector(31 downto 0);
axiA_arlen : in std_logic_vector(7 downto 0);
axiA_arsize : in std_logic_vector(2 downto 0);
axiA_arburst : in std_logic_vector(1 downto 0);
axiA_arlock : in std_logic;
axiA_arcache : in std_logic_vector(3 downto 0);
axiA_arprot : in std_logic_vector(2 downto 0);
axiA_arqos : in std_logic_vector(3 downto 0);
axiA_arregion : in std_logic_vector(3 downto 0);
axiA_arvalid : in std_logic;
axiA_arready : out std_logic;
axiA_rdata : out std_logic_vector(31 downto 0);
axiA_rresp : out std_logic_vector(1 downto 0);
axiA_rlast : out std_logic;
axiA_rvalid : out std_logic;
axiA_rready : in std_logic;
userInterruptA : out std_logic;
userInterruptB : out std_logic;
userInterruptC : out std_logic;
userInterruptD : out std_logic;
userInterruptE : out std_logic;
userInterruptF : out std_logic;
io_apbSlave_0_PADDR : out std_logic_vector(31 downto 0);
io_apbSlave_0_PENABLE : out std_logic;
io_apbSlave_0_PRDATA : in std_logic_vector(31 downto 0);
io_apbSlave_0_PREADY : in std_logic;
io_apbSlave_0_PSEL : out std_logic;
io_apbSlave_0_PSLVERROR : in std_logic;
io_apbSlave_0_PWDATA : out std_logic_vector(31 downto 0);
io_apbSlave_0_PWRITE : out std_logic;
system_i2c_0_io_sda_write : out std_logic;
system_i2c_0_io_sda_writeEnable : out std_logic;
system_i2c_0_io_scl_writeEnable : out std_logic;
system_watchdog_hardPanic_reset : out std_logic
);
end component EfxSapphireHpSoc_slb;
---------------------- End COMPONENT Declaration ------------
------------- Begin Cut here for INSTANTIATION Template -----
u_EfxSapphireHpSoc_slb : EfxSapphireHpSoc_slb
port map (
io_peripheralClk => io_peripheralClk,
io_peripheralReset => io_peripheralReset,
io_asyncReset => io_asyncReset,
io_gpio_sw_n => io_gpio_sw_n,
pll_peripheral_locked => pll_peripheral_locked,
pll_system_locked => pll_system_locked,
jtagCtrl_capture => jtagCtrl_capture,
jtagCtrl_enable => jtagCtrl_enable,
jtagCtrl_reset => jtagCtrl_reset,
jtagCtrl_shift => jtagCtrl_shift,
jtagCtrl_tdi => jtagCtrl_tdi,
jtagCtrl_tdo => jtagCtrl_tdo,
jtagCtrl_update => jtagCtrl_update,
ut_jtagCtrl_capture => ut_jtagCtrl_capture,
ut_jtagCtrl_enable => ut_jtagCtrl_enable,
ut_jtagCtrl_reset => ut_jtagCtrl_reset,
ut_jtagCtrl_shift => ut_jtagCtrl_shift,
ut_jtagCtrl_tdi => ut_jtagCtrl_tdi,
ut_jtagCtrl_tdo => ut_jtagCtrl_tdo,
ut_jtagCtrl_update => ut_jtagCtrl_update,
system_spi_0_io_data_0_read => system_spi_0_io_data_0_read,
system_spi_0_io_data_0_write => system_spi_0_io_data_0_write,
system_spi_0_io_data_0_writeEnable => system_spi_0_io_data_0_writeEnable,
system_spi_0_io_data_1_read => system_spi_0_io_data_1_read,
system_spi_0_io_data_1_write => system_spi_0_io_data_1_write,
system_spi_0_io_data_1_writeEnable => system_spi_0_io_data_1_writeEnable,
system_spi_0_io_data_2_read => system_spi_0_io_data_2_read,
system_spi_0_io_data_2_write => system_spi_0_io_data_2_write,
system_spi_0_io_data_2_writeEnable => system_spi_0_io_data_2_writeEnable,
system_spi_0_io_data_3_read => system_spi_0_io_data_3_read,
system_spi_0_io_data_3_write => system_spi_0_io_data_3_write,
system_spi_0_io_data_3_writeEnable => system_spi_0_io_data_3_writeEnable,
system_spi_0_io_sclk_write => system_spi_0_io_sclk_write,
system_spi_0_io_ss => system_spi_0_io_ss,
system_uart_0_io_rxd => system_uart_0_io_rxd,
system_uart_0_io_txd => system_uart_0_io_txd,
system_i2c_0_io_scl_read => system_i2c_0_io_scl_read,
system_i2c_0_io_scl_write => system_i2c_0_io_scl_write,
system_i2c_0_io_sda_read => system_i2c_0_io_sda_read,
system_gpio_0_io_read => system_gpio_0_io_read,
system_gpio_0_io_write => system_gpio_0_io_write,
system_gpio_0_io_writeEnable => system_gpio_0_io_writeEnable,
cfg_done => cfg_done,
cfg_start => cfg_start,
cfg_sel => cfg_sel,
cfg_reset => cfg_reset,
axiAInterrupt => axiAInterrupt,
axiA_awaddr => axiA_awaddr,
axiA_awlen => axiA_awlen,
axiA_awsize => axiA_awsize,
axiA_awburst => axiA_awburst,
axiA_awlock => axiA_awlock,
axiA_awcache => axiA_awcache,
axiA_awprot => axiA_awprot,
axiA_awqos => axiA_awqos,
axiA_awregion => axiA_awregion,
axiA_awvalid => axiA_awvalid,
axiA_awready => axiA_awready,
axiA_wdata => axiA_wdata,
axiA_wstrb => axiA_wstrb,
axiA_wvalid => axiA_wvalid,
axiA_wlast => axiA_wlast,
axiA_wready => axiA_wready,
axiA_bresp => axiA_bresp,
axiA_bvalid => axiA_bvalid,
axiA_bready => axiA_bready,
axiA_araddr => axiA_araddr,
axiA_arlen => axiA_arlen,
axiA_arsize => axiA_arsize,
axiA_arburst => axiA_arburst,
axiA_arlock => axiA_arlock,
axiA_arcache => axiA_arcache,
axiA_arprot => axiA_arprot,
axiA_arqos => axiA_arqos,
axiA_arregion => axiA_arregion,
axiA_arvalid => axiA_arvalid,
axiA_arready => axiA_arready,
axiA_rdata => axiA_rdata,
axiA_rresp => axiA_rresp,
axiA_rlast => axiA_rlast,
axiA_rvalid => axiA_rvalid,
axiA_rready => axiA_rready,
userInterruptA => userInterruptA,
userInterruptB => userInterruptB,
userInterruptC => userInterruptC,
userInterruptD => userInterruptD,
userInterruptE => userInterruptE,
userInterruptF => userInterruptF,
io_apbSlave_0_PADDR => io_apbSlave_0_PADDR,
io_apbSlave_0_PENABLE => io_apbSlave_0_PENABLE,
io_apbSlave_0_PRDATA => io_apbSlave_0_PRDATA,
io_apbSlave_0_PREADY => io_apbSlave_0_PREADY,
io_apbSlave_0_PSEL => io_apbSlave_0_PSEL,
io_apbSlave_0_PSLVERROR => io_apbSlave_0_PSLVERROR,
io_apbSlave_0_PWDATA => io_apbSlave_0_PWDATA,
io_apbSlave_0_PWRITE => io_apbSlave_0_PWRITE,
system_i2c_0_io_sda_write => system_i2c_0_io_sda_write,
system_i2c_0_io_sda_writeEnable => system_i2c_0_io_sda_writeEnable,
system_i2c_0_io_scl_writeEnable => system_i2c_0_io_scl_writeEnable,
system_watchdog_hardPanic_reset => system_watchdog_hardPanic_reset
);
------------------------ End INSTANTIATION Template ---------

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module EfxSapphireHpSoc_wrapper (
output system_uart_0_io_txd,
input system_uart_0_io_rxd,
input io_cfuClk,
input io_cfuReset,
output userInterruptC,
input [3:0] system_gpio_0_io_read,
output [3:0] system_gpio_0_io_write,
output [3:0] system_gpio_0_io_writeEnable,
input cpu1_customInstruction_cmd_valid,
output cpu1_customInstruction_cmd_ready,
input [9:0] cpu1_customInstruction_function_id,
input [31:0] cpu1_customInstruction_inputs_0,
input [31:0] cpu1_customInstruction_inputs_1,
output cpu1_customInstruction_rsp_valid,
input cpu1_customInstruction_rsp_ready,
output [31:0] cpu1_customInstruction_outputs_0,
output system_watchdog_hardPanic_reset,
output jtagCtrl_tdi,
input jtagCtrl_tdo,
output jtagCtrl_enable,
output jtagCtrl_capture,
output jtagCtrl_shift,
output jtagCtrl_update,
output jtagCtrl_reset,
input ut_jtagCtrl_tdi,
output ut_jtagCtrl_tdo,
input ut_jtagCtrl_enable,
input ut_jtagCtrl_capture,
input ut_jtagCtrl_shift,
input ut_jtagCtrl_update,
input ut_jtagCtrl_reset,
output system_i2c_0_io_sda_writeEnable,
output system_i2c_0_io_sda_write,
input system_i2c_0_io_sda_read,
output system_i2c_0_io_scl_writeEnable,
output system_i2c_0_io_scl_write,
input system_i2c_0_io_scl_read,
output userInterruptD,
input cpu0_customInstruction_cmd_valid,
output cpu0_customInstruction_cmd_ready,
input [9:0] cpu0_customInstruction_function_id,
input [31:0] cpu0_customInstruction_inputs_0,
input [31:0] cpu0_customInstruction_inputs_1,
output cpu0_customInstruction_rsp_valid,
input cpu0_customInstruction_rsp_ready,
output [31:0] cpu0_customInstruction_outputs_0,
output system_spi_0_io_sclk_write,
output system_spi_0_io_data_0_writeEnable,
input system_spi_0_io_data_0_read,
output system_spi_0_io_data_0_write,
output system_spi_0_io_data_1_writeEnable,
input system_spi_0_io_data_1_read,
output system_spi_0_io_data_1_write,
output system_spi_0_io_data_2_writeEnable,
input system_spi_0_io_data_2_read,
output system_spi_0_io_data_2_write,
output system_spi_0_io_data_3_writeEnable,
input system_spi_0_io_data_3_read,
output system_spi_0_io_data_3_write,
output [3:0] system_spi_0_io_ss,
output userInterruptF,
output userInterruptG,
output userInterruptE,
output userInterruptI,
output userInterruptH,
input cpu2_customInstruction_cmd_valid,
output cpu2_customInstruction_cmd_ready,
input [9:0] cpu2_customInstruction_function_id,
input [31:0] cpu2_customInstruction_inputs_0,
input [31:0] cpu2_customInstruction_inputs_1,
output cpu2_customInstruction_rsp_valid,
input cpu2_customInstruction_rsp_ready,
output [31:0] cpu2_customInstruction_outputs_0,
input cpu3_customInstruction_cmd_valid,
output cpu3_customInstruction_cmd_ready,
input [9:0] cpu3_customInstruction_function_id,
input [31:0] cpu3_customInstruction_inputs_0,
input [31:0] cpu3_customInstruction_inputs_1,
output cpu3_customInstruction_rsp_valid,
input cpu3_customInstruction_rsp_ready,
output [31:0] cpu3_customInstruction_outputs_0,
output userInterruptB,
output userInterruptA,
output io_ddrMasters_0_aw_valid,
input io_ddrMasters_0_aw_ready,
output [31:0] io_ddrMasters_0_aw_payload_addr,
output [3:0] io_ddrMasters_0_aw_payload_id,
output [3:0] io_ddrMasters_0_aw_payload_region,
output [7:0] io_ddrMasters_0_aw_payload_len,
output [2:0] io_ddrMasters_0_aw_payload_size,
output [1:0] io_ddrMasters_0_aw_payload_burst,
output io_ddrMasters_0_aw_payload_lock,
output [3:0] io_ddrMasters_0_aw_payload_cache,
output [3:0] io_ddrMasters_0_aw_payload_qos,
output [2:0] io_ddrMasters_0_aw_payload_prot,
output io_ddrMasters_0_aw_payload_allStrb,
output io_ddrMasters_0_w_valid,
input io_ddrMasters_0_w_ready,
output [127:0] io_ddrMasters_0_w_payload_data,
output [15:0] io_ddrMasters_0_w_payload_strb,
output io_ddrMasters_0_w_payload_last,
input io_ddrMasters_0_b_valid,
output io_ddrMasters_0_b_ready,
input [3:0] io_ddrMasters_0_b_payload_id,
input [1:0] io_ddrMasters_0_b_payload_resp,
output io_ddrMasters_0_ar_valid,
input io_ddrMasters_0_ar_ready,
output [31:0] io_ddrMasters_0_ar_payload_addr,
output [3:0] io_ddrMasters_0_ar_payload_id,
output [3:0] io_ddrMasters_0_ar_payload_region,
output [7:0] io_ddrMasters_0_ar_payload_len,
output [2:0] io_ddrMasters_0_ar_payload_size,
output [1:0] io_ddrMasters_0_ar_payload_burst,
output io_ddrMasters_0_ar_payload_lock,
output [3:0] io_ddrMasters_0_ar_payload_cache,
output [3:0] io_ddrMasters_0_ar_payload_qos,
output [2:0] io_ddrMasters_0_ar_payload_prot,
input io_ddrMasters_0_r_valid,
output io_ddrMasters_0_r_ready,
input [127:0] io_ddrMasters_0_r_payload_data,
input [3:0] io_ddrMasters_0_r_payload_id,
input [1:0] io_ddrMasters_0_r_payload_resp,
input io_ddrMasters_0_r_payload_last,
input io_ddrMasters_0_clk,
input io_ddrMasters_0_reset,
input [31:0] axiA_awaddr,
input [7:0] axiA_awlen,
input [2:0] axiA_awsize,
input [1:0] axiA_awburst,
input axiA_awlock,
input [3:0] axiA_awcache,
input [2:0] axiA_awprot,
input [3:0] axiA_awqos,
input [3:0] axiA_awregion,
input axiA_awvalid,
output axiA_awready,
input [31:0] axiA_wdata,
input [3:0] axiA_wstrb,
input axiA_wvalid,
input axiA_wlast,
output axiA_wready,
output [1:0] axiA_bresp,
output axiA_bvalid,
input axiA_bready,
input [31:0] axiA_araddr,
input [7:0] axiA_arlen,
input [2:0] axiA_arsize,
input [1:0] axiA_arburst,
input axiA_arlock,
input [3:0] axiA_arcache,
input [2:0] axiA_arprot,
input [3:0] axiA_arqos,
input [3:0] axiA_arregion,
input axiA_arvalid,
output axiA_arready,
output [31:0] axiA_rdata,
output [1:0] axiA_rresp,
output axiA_rlast,
output axiA_rvalid,
input axiA_rready,
output axiAInterrupt,
input cfg_done,
output cfg_start,
output cfg_sel,
output cfg_reset,
input io_peripheralClk,
input io_peripheralReset,
output io_asyncReset,
input io_gpio_sw_n,
input pll_peripheral_locked,
input pll_system_locked
);
wire [15:0] io_apbSlave_0_PADDR;
wire io_apbSlave_0_PSEL;
wire io_apbSlave_0_PENABLE;
wire io_apbSlave_0_PREADY;
wire io_apbSlave_0_PWRITE;
wire [31:0] io_apbSlave_0_PWDATA;
wire [31:0] io_apbSlave_0_PRDATA;
wire io_apbSlave_0_PSLVERROR;
assign userInterruptG = 1'b0; //USER TO MODIFY
assign userInterruptH = 1'b0; //USER TO MODIFY
assign userInterruptI = 1'b0; //USER TO MODIFY
/**/
/* INFO: USER TO MODIFY CODES BELOW */
/* INFO: REFER EXAMPLE DESIGN FOR IMPLEMENTATION DETAILS */
/**/
assign io_apbSlave_0_PREADY = 1'b1;
assign io_apbSlave_0_PRDATA = 32'd0;
//io_apbSlave_0_PADDR;
//io_apbSlave_0_PSEL;
//io_apbSlave_0_PENABLE;
//io_apbSlave_0_PWRITE;
//io_apbSlave_0_PWDATA;
//io_apbSlave_0_PSLVERROR;
/**/
/* INFO: USER TO MODIFY CODES BELOW */
/* INFO: REFER EXAMPLE DESIGN FOR IMPLEMENTATION DETAILS */
/**/
assign cpu1_customInstruction_cmd_ready = 1'b1;
assign cpu1_customInstruction_rsp_valid = 1'b0;
assign cpu1_customInstruction_outputs_0 = 32'd0;
//io_cfuClk
//io_cfyReset
//cpu1_customInstruction_rsp_ready
//cpu1_customInstruction_cmd_valid
//cpu1_customInstruction_function_id
//cpu1_customInstruction_inputs_0
//cpu1_customInstruction_inputs_1
/**/
/* INFO: USER TO MODIFY CODES BELOW */
/* INFO: REFER EXAMPLE DESIGN FOR IMPLEMENTATION DETAILS */
/**/
assign cpu3_customInstruction_cmd_ready = 1'b1;
assign cpu3_customInstruction_rsp_valid = 1'b0;
assign cpu3_customInstruction_outputs_0 = 32'd0;
//io_cfuClk
//io_cfyReset
//cpu3_customInstruction_rsp_ready
//cpu3_customInstruction_cmd_valid
//cpu3_customInstruction_function_id
//cpu3_customInstruction_inputs_0
//cpu3_customInstruction_inputs_1
/**/
/* INFO: USER TO MODIFY CODES BELOW */
/* INFO: REFER EXAMPLE DESIGN FOR IMPLEMENTATION DETAILS */
/**/
assign io_ddrMasters_0_aw_payload_addr = 32'd0;
assign io_ddrMasters_0_aw_payload_id = 4'd0;
assign io_ddrMasters_0_aw_payload_region = 4'd0;
assign io_ddrMasters_0_aw_payload_len = 8'd0;
assign io_ddrMasters_0_aw_payload_size = 3'd0;
assign io_ddrMasters_0_aw_payload_burst = 2'd0;
assign io_ddrMasters_0_aw_payload_lock = 1'b0;
assign io_ddrMasters_0_aw_payload_cache = 4'd0;
assign io_ddrMasters_0_aw_payload_qos = 4'd0;
assign io_ddrMasters_0_aw_payload_prot = 3'd0;
assign io_ddrMasters_0_aw_payload_allStrb = 1'b0;
assign io_ddrMasters_0_w_valid = 1'b0;
//io_ddrMasters_0_w_ready
assign io_ddrMasters_0_w_payload_data = 128'd0;
assign io_ddrMasters_0_w_payload_strb = 16'd0;
assign io_ddrMasters_0_w_payload_last = 1'b0;
//io_ddrMasters_0_b_valid
assign io_ddrMasters_0_b_ready = 1'b1;
//io_ddrMasters_0_b_payload_id
//io_ddrMasters_0_b_payload_resp
assign io_ddrMasters_0_ar_valid = 1'b0;
//io_ddrMasters_0_ar_ready
assign io_ddrMasters_0_ar_payload_addr = 32'd0;
assign io_ddrMasters_0_ar_payload_id = 4'd0;
assign io_ddrMasters_0_ar_payload_region = 4'd0;
assign io_ddrMasters_0_ar_payload_len = 8'd0;
assign io_ddrMasters_0_ar_payload_size = 3'd0;
assign io_ddrMasters_0_ar_payload_burst = 2'd0;
assign io_ddrMasters_0_ar_payload_lock = 1'b0;
assign io_ddrMasters_0_ar_payload_cache = 4'd0;
assign io_ddrMasters_0_ar_payload_qos = 4'd0;
assign io_ddrMasters_0_ar_payload_pro = 3'd0;
//io_ddrMasters_0_r_valid
assign io_ddrMasters_0_r_ready = 1'b1;
//io_ddrMasters_0_r_payload_data
//io_ddrMasters_0_r_payload_id
//io_ddrMasters_0_r_payload_resp
//io_ddrMasters_0_r_payload_last
/**/
/* INFO: USER TO MODIFY CODES BELOW */
/* INFO: REFER EXAMPLE DESIGN FOR IMPLEMENTATION DETAILS */
/**/
assign cpu0_customInstruction_cmd_ready = 1'b1;
assign cpu0_customInstruction_rsp_valid = 1'b0;
assign cpu0_customInstruction_outputs_0 = 32'd0;
//io_cfuClk
//io_cfyReset
//cpu0_customInstruction_rsp_ready
//cpu0_customInstruction_cmd_valid
//cpu0_customInstruction_function_id
//cpu0_customInstruction_inputs_0
//cpu0_customInstruction_inputs_1
/**/
/* INFO: USER TO MODIFY CODES BELOW */
/* INFO: REFER EXAMPLE DESIGN FOR IMPLEMENTATION DETAILS */
/**/
assign cpu2_customInstruction_cmd_ready = 1'b1;
assign cpu2_customInstruction_rsp_valid = 1'b0;
assign cpu2_customInstruction_outputs_0 = 32'd0;
//io_cfuClk
//io_cfyReset
//cpu2_customInstruction_rsp_ready
//cpu2_customInstruction_cmd_valid
//cpu2_customInstruction_function_id
//cpu2_customInstruction_inputs_0
//cpu2_customInstruction_inputs_1
//axi4 bridge to various I/O
EfxSapphireHpSoc_slb u_top_peripherals(
.userInterruptA(userInterruptA),
.jtagCtrl_tdi(jtagCtrl_tdi),
.jtagCtrl_tdo(jtagCtrl_tdo),
.jtagCtrl_enable(jtagCtrl_enable),
.jtagCtrl_capture(jtagCtrl_capture),
.jtagCtrl_shift(jtagCtrl_shift),
.jtagCtrl_update(jtagCtrl_update),
.jtagCtrl_reset(jtagCtrl_reset),
.ut_jtagCtrl_tdi(ut_jtagCtrl_tdi),
.ut_jtagCtrl_tdo(ut_jtagCtrl_tdo),
.ut_jtagCtrl_enable(ut_jtagCtrl_enable),
.ut_jtagCtrl_capture(ut_jtagCtrl_capture),
.ut_jtagCtrl_shift(ut_jtagCtrl_shift),
.ut_jtagCtrl_update(ut_jtagCtrl_update),
.ut_jtagCtrl_reset(ut_jtagCtrl_reset),
.userInterruptE(userInterruptE),
.userInterruptF(userInterruptF),
.userInterruptB(userInterruptB),
.io_apbSlave_0_PADDR(io_apbSlave_0_PADDR),
.io_apbSlave_0_PSEL(io_apbSlave_0_PSEL),
.io_apbSlave_0_PENABLE(io_apbSlave_0_PENABLE),
.io_apbSlave_0_PREADY(io_apbSlave_0_PREADY),
.io_apbSlave_0_PWRITE(io_apbSlave_0_PWRITE),
.io_apbSlave_0_PWDATA(io_apbSlave_0_PWDATA),
.io_apbSlave_0_PRDATA(io_apbSlave_0_PRDATA),
.io_apbSlave_0_PSLVERROR(io_apbSlave_0_PSLVERROR),
.system_watchdog_hardPanic_reset(system_watchdog_hardPanic_reset),
.system_spi_0_io_sclk_write(system_spi_0_io_sclk_write),
.system_spi_0_io_data_0_writeEnable(system_spi_0_io_data_0_writeEnable),
.system_spi_0_io_data_0_read(system_spi_0_io_data_0_read),
.system_spi_0_io_data_0_write(system_spi_0_io_data_0_write),
.system_spi_0_io_data_1_writeEnable(system_spi_0_io_data_1_writeEnable),
.system_spi_0_io_data_1_read(system_spi_0_io_data_1_read),
.system_spi_0_io_data_1_write(system_spi_0_io_data_1_write),
.system_spi_0_io_data_2_writeEnable(system_spi_0_io_data_2_writeEnable),
.system_spi_0_io_data_2_read(system_spi_0_io_data_2_read),
.system_spi_0_io_data_2_write(system_spi_0_io_data_2_write),
.system_spi_0_io_data_3_writeEnable(system_spi_0_io_data_3_writeEnable),
.system_spi_0_io_data_3_read(system_spi_0_io_data_3_read),
.system_spi_0_io_data_3_write(system_spi_0_io_data_3_write),
.system_spi_0_io_ss(system_spi_0_io_ss),
.system_uart_0_io_txd(system_uart_0_io_txd),
.system_uart_0_io_rxd(system_uart_0_io_rxd),
.userInterruptC(userInterruptC),
.system_gpio_0_io_read(system_gpio_0_io_read),
.system_gpio_0_io_write(system_gpio_0_io_write),
.system_gpio_0_io_writeEnable(system_gpio_0_io_writeEnable),
.userInterruptD(userInterruptD),
.system_i2c_0_io_sda_writeEnable(system_i2c_0_io_sda_writeEnable),
.system_i2c_0_io_sda_write(system_i2c_0_io_sda_write),
.system_i2c_0_io_sda_read(system_i2c_0_io_sda_read),
.system_i2c_0_io_scl_writeEnable(system_i2c_0_io_scl_writeEnable),
.system_i2c_0_io_scl_write(system_i2c_0_io_scl_write),
.system_i2c_0_io_scl_read(system_i2c_0_io_scl_read),
.axiA_awvalid(axiA_awvalid),
.axiA_awready(axiA_awready),
.axiA_awaddr(axiA_awaddr),
.axiA_awlen(axiA_awlen),
.axiA_awsize(axiA_awsize),
.axiA_awcache(axiA_awcache),
.axiA_awprot(axiA_awprot),
.axiA_wvalid(axiA_wvalid),
.axiA_wready(axiA_wready),
.axiA_wdata(axiA_wdata),
.axiA_wstrb(axiA_wstrb),
.axiA_wlast(axiA_wlast),
.axiA_bvalid(axiA_bvalid),
.axiA_bready(axiA_bready),
.axiA_bresp(axiA_bresp),
.axiA_arvalid(axiA_arvalid),
.axiA_arready(axiA_arready),
.axiA_araddr(axiA_araddr),
.axiA_arlen(axiA_arlen),
.axiA_arsize(axiA_arsize),
.axiA_arcache(axiA_arcache),
.axiA_arprot(axiA_arprot),
.axiA_rvalid(axiA_rvalid),
.axiA_rready(axiA_rready),
.axiA_rdata(axiA_rdata),
.axiA_rresp(axiA_rresp),
.axiA_rlast(axiA_rlast),
.axiAInterrupt(axiAInterrupt),
.cfg_done(cfg_done),
.cfg_start(cfg_start),
.cfg_sel(cfg_sel),
.cfg_reset(cfg_reset),
.io_peripheralClk(io_peripheralClk),
.io_peripheralReset(io_peripheralReset),
.io_asyncReset(io_asyncReset),
.io_gpio_sw_n(io_gpio_sw_n),
.pll_peripheral_locked(pll_peripheral_locked),
.pll_system_locked(pll_system_locked)
);
endmodule

224
Ti375C529_devkit/ip/EfxSapphireHpSoc_slb/hard_ip_args.ini Normal file
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[parameters]
pll_soc_sys_clk_name = soc_pll_sys_clk
hidden_min_freq = 0
pll_soc_sys_clk_ref_freq_hidden = 100
pll_soc_sys_clk_ref_freq = 100
pll_soc_sys_clkout1_freq = 1000
pll_soc_sys_clkout1_phase = 0
pll_soc_sys_clkout2_freq = 250
pll_soc_sys_clkout2_phase = 0
pll_soc_mem_clk_name = soc_pll_peri_clk
pll_soc_mem_clk_ref_freq = 25
pll_soc_mem_clkout1_freq = 250
pll_soc_mem_clkout1_phase = 0
pll_soc_mem_clkout2_freq = 250
pll_soc_mem_clkout2_phase = 0
pll_lpddr4_name = soc_ddr_pll
pll_lpddr4_ref_freq = 25
pll_lpddr4_clkout0_freq = 100
pll_lpddr4_clkout0_phase = 0
pll_lpddr4_clkout3_freq = 533
pll_lpddr4_clkout3_phase = 0
ddr_data_width = 32
ddr_memory_density = 8G
ddr_memory_type = LPDDR4x
ddr_physical_rank = 1
ddr_pin_name = soc_ddr_inst1
gpio_bus_name = system_gpio_0
hard_jtag_inst_name = soc_jtag_inst1
uart0_gpio_inst_name = system_uart_0
spi0_gpio_inst_name = system_spi_0
i2c0_gpio_inst_name = system_i2c_0
jtag_gpio_inst_name = io_jtag
soc_pin_name = qcrv32_inst1
intf_axim = 1
intf_ci_0 = 1
intf_ci_1 = 1
intf_ci_2 = 1
intf_ci_3 = 1
co_debug = 0
intf_jtag_type = 0
intf_uintr = 9
peri_spi_0 = 1
peri_spi_1 = 0
peri_spi_2 = 0
peri_i2c_0 = 1
peri_i2c_1 = 0
peri_i2c_2 = 0
peri_gpio_0 = 1
peri_gpio_1 = 0
peri_wdt_0 = 1
peri_apb_0 = 1
peri_apb_1 = 0
peri_apb_2 = 0
peri_apb_3 = 0
peri_apb_4 = 0
peri_gen = 1
peri_uart_0 = 1
peri_uart_1 = 0
peri_uart_2 = 0
peri_gpio_0_width = 4
peri_gpio_1_width = 4
peri_apb_0_size = 65536
peri_apb_1_size = 4096
peri_apb_2_size = 4096
peri_apb_3_size = 4096
peri_apb_4_size = 4096
peri_freq = 200
app_overwrite = 0
app_overwrite_path =
peri_count = 6
peri_tcount = 6
intf_jtag_tap_sel = 8
intf_axis = 1
peri_pin_assign = 1
pll_soc_mem_resource = PLL_TR0
sys_freq = 1000
sys_freq_hidden = 1000
pll_soc_sys_clkout3_freq = 250
pll_soc_sys_clkout3_phase = 0
pll_soc_mem_clkout3_freq = 250
pll_soc_mem_clkout3_phase = 0
pll_soc_mem_clkout4_freq = 200
pll_soc_mem_clkout4_phase = 0
pll_soc_sys_resource = PLL_BL0
pll_lpddr4_resource = PLL_BL2
pll_res_assign = 0
pll_soc_sys_clkout0_freq = 100
pll_soc_sys_clkout0_phase = 0
pll_soc_mem_clkout0_freq = 100
pll_soc_mem_clkout0_phase = 0
pll_lpddr4_clkout1_freq = 33
pll_lpddr4_clkout1_phase = 0
mem_freq = 250
axim_freq = 250
cfu_freq = 125
ddr_freq = 800
pll_res_assign_2 = 0
ddr_res_assign = 0
peri_res_assign = 0
pll_soc_sys_ext_clk_src = 1
pll_soc_mem_ext_clk_src = 0
peri_sdhc = 0
peri_tsemac = 0
sw_ftdi_ch_num = 6011
sw_app_size = 2044
sw_app_size_custom = 0
sw_stack_size = 8
sw_stack_size_custom = 0
sw_board = Ti375C529 Development Kit
sw_board_custom =
sw_ftdi_target_ch = 1
sw_ftdi_ch_num_soft = 6011
sw_ftdi_target_ch_soft = 0
sw_frtos_app_size = 16380
sw_frtos_app_size_custom = 0
sw_frtos_stack_size = 4
sw_frtos_stack_size_custom = 0
package_type = 529
family_type = TITANIUM
axi_pipeline = 0
axi_write_buffer = 0
[ports]
io_peripheralclk = io_peripheralClk
io_peripheralreset = io_peripheralReset
io_asyncreset = io_asyncReset
io_gpio_sw_n = io_gpio_sw_n
pll_peripheral_locked = pll_peripheral_locked
pll_system_locked = pll_system_locked
jtagctrl_capture = jtagCtrl_capture
jtagctrl_enable = jtagCtrl_enable
jtagctrl_reset = jtagCtrl_reset
jtagctrl_shift = jtagCtrl_shift
jtagctrl_tdi = jtagCtrl_tdi
jtagctrl_tdo = jtagCtrl_tdo
jtagctrl_update = jtagCtrl_update
ut_jtagctrl_capture = ut_jtagCtrl_capture
ut_jtagctrl_enable = ut_jtagCtrl_enable
ut_jtagctrl_reset = ut_jtagCtrl_reset
ut_jtagctrl_shift = ut_jtagCtrl_shift
ut_jtagctrl_tdi = ut_jtagCtrl_tdi
ut_jtagctrl_tdo = ut_jtagCtrl_tdo
ut_jtagctrl_update = ut_jtagCtrl_update
system_spi_0_io_data_0_read = system_spi_0_io_data_0_read
system_spi_0_io_data_0_write = system_spi_0_io_data_0_write
system_spi_0_io_data_0_writeenable = system_spi_0_io_data_0_writeEnable
system_spi_0_io_data_1_read = system_spi_0_io_data_1_read
system_spi_0_io_data_1_write = system_spi_0_io_data_1_write
system_spi_0_io_data_1_writeenable = system_spi_0_io_data_1_writeEnable
system_spi_0_io_data_2_read = system_spi_0_io_data_2_read
system_spi_0_io_data_2_write = system_spi_0_io_data_2_write
system_spi_0_io_data_2_writeenable = system_spi_0_io_data_2_writeEnable
system_spi_0_io_data_3_read = system_spi_0_io_data_3_read
system_spi_0_io_data_3_write = system_spi_0_io_data_3_write
system_spi_0_io_data_3_writeenable = system_spi_0_io_data_3_writeEnable
system_spi_0_io_sclk_write = system_spi_0_io_sclk_write
system_spi_0_io_ss = system_spi_0_io_ss
system_uart_0_io_rxd = system_uart_0_io_rxd
system_uart_0_io_txd = system_uart_0_io_txd
system_i2c_0_io_scl_read = system_i2c_0_io_scl_read
system_i2c_0_io_scl_write = system_i2c_0_io_scl_write
system_i2c_0_io_sda_read = system_i2c_0_io_sda_read
system_gpio_0_io_read = system_gpio_0_io_read
system_gpio_0_io_write = system_gpio_0_io_write
system_gpio_0_io_writeenable = system_gpio_0_io_writeEnable
cfg_done = cfg_done
cfg_start = cfg_start
cfg_sel = cfg_sel
cfg_reset = cfg_reset
axiainterrupt = axiAInterrupt
axia_awaddr = axiA_awaddr
axia_awlen = axiA_awlen
axia_awsize = axiA_awsize
axia_awburst = axiA_awburst
axia_awlock = axiA_awlock
axia_awcache = axiA_awcache
axia_awprot = axiA_awprot
axia_awqos = axiA_awqos
axia_awregion = axiA_awregion
axia_awvalid = axiA_awvalid
axia_awready = axiA_awready
axia_wdata = axiA_wdata
axia_wstrb = axiA_wstrb
axia_wvalid = axiA_wvalid
axia_wlast = axiA_wlast
axia_wready = axiA_wready
axia_bresp = axiA_bresp
axia_bvalid = axiA_bvalid
axia_bready = axiA_bready
axia_araddr = axiA_araddr
axia_arlen = axiA_arlen
axia_arsize = axiA_arsize
axia_arburst = axiA_arburst
axia_arlock = axiA_arlock
axia_arcache = axiA_arcache
axia_arprot = axiA_arprot
axia_arqos = axiA_arqos
axia_arregion = axiA_arregion
axia_arvalid = axiA_arvalid
axia_arready = axiA_arready
axia_rdata = axiA_rdata
axia_rresp = axiA_rresp
axia_rlast = axiA_rlast
axia_rvalid = axiA_rvalid
axia_rready = axiA_rready
userinterrupta = userInterruptA
userinterruptb = userInterruptB
userinterruptc = userInterruptC
userinterruptd = userInterruptD
userinterrupte = userInterruptE
userinterruptf = userInterruptF
io_apbslave_0_paddr = io_apbSlave_0_PADDR
io_apbslave_0_penable = io_apbSlave_0_PENABLE
io_apbslave_0_prdata = io_apbSlave_0_PRDATA
io_apbslave_0_pready = io_apbSlave_0_PREADY
io_apbslave_0_psel = io_apbSlave_0_PSEL
io_apbslave_0_pslverror = io_apbSlave_0_PSLVERROR
io_apbslave_0_pwdata = io_apbSlave_0_PWDATA
io_apbslave_0_pwrite = io_apbSlave_0_PWRITE
system_i2c_0_io_sda_write = system_i2c_0_io_sda_write
system_i2c_0_io_sda_writeenable = system_i2c_0_io_sda_writeEnable
system_i2c_0_io_scl_writeenable = system_i2c_0_io_scl_writeEnable
system_watchdog_hardpanic_reset = system_watchdog_hardPanic_reset

BIN
Ti375C529_devkit/ip/EfxSapphireHpSoc_slb/ipm/component.pickle Normal file
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BIN
Ti375C529_devkit/ip/EfxSapphireHpSoc_slb/ipm/graph.pickle Normal file
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20
Ti375C529_devkit/ip/EfxSapphireHpSoc_slb/ipm_pt_map.json Normal file
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@@ -0,0 +1,20 @@
{
"PLL": {},
"GPIO": {
"UART": [],
"SPI": [],
"I2C": [],
"JTAG": [],
"GPIO": []
},
"SOC": {
"SOC_PIN_NAME": {
"SOC_PIN_NAME": "qcrv32_inst1"
}
},
"JTAG": {
"HARD_JTAG_INST_NAME": {
"HARD_JTAG_INST_NAME": "soc_jtag_inst1"
}
}
}

134
Ti375C529_devkit/ip/EfxSapphireHpSoc_slb/settings.json Normal file
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@@ -0,0 +1,134 @@
{
"args": [
"-o",
"EfxSapphireHpSoc_slb",
"--base_path",
"ip",
"--vlnv",
{
"vendor": "efinixinc.com",
"library": "soc",
"name": "efx_hard_soc",
"version": "1.23.0"
}
],
"conf": {
"PLL_SOC_SYS_CLK_NAME": "\"soc_pll_sys_clk\"",
"PLL_SOC_SYS_CLK_REF_FREQ_HIDDEN": "\"100\"",
"PLL_SOC_SYS_CLK_REF_FREQ": "\"100\"",
"PLL_SOC_SYS_CLKOUT1_PHASE": "\"0\"",
"PLL_SOC_SYS_CLKOUT2_PHASE": "\"0\"",
"PLL_SOC_MEM_CLK_NAME": "\"soc_pll_peri_clk\"",
"PLL_SOC_MEM_CLK_REF_FREQ": "\"25\"",
"PLL_SOC_MEM_CLKOUT1_FREQ": "\"250\"",
"PLL_SOC_MEM_CLKOUT1_PHASE": "\"0\"",
"PLL_SOC_MEM_CLKOUT2_FREQ": "\"250\"",
"PLL_SOC_MEM_CLKOUT2_PHASE": "\"0\"",
"PLL_LPDDR4_NAME": "\"soc_ddr_pll\"",
"PLL_LPDDR4_REF_FREQ": "\"25\"",
"PLL_LPDDR4_CLKOUT0_FREQ": "\"100\"",
"PLL_LPDDR4_CLKOUT0_PHASE": "\"0\"",
"PLL_LPDDR4_CLKOUT3_FREQ": "\"533\"",
"PLL_LPDDR4_CLKOUT3_PHASE": "\"0\"",
"DDR_DATA_WIDTH": "32",
"DDR_MEMORY_DENSITY": "\"8G\"",
"DDR_MEMORY_TYPE": "\"LPDDR4x\"",
"DDR_PHYSICAL_RANK": "1",
"DDR_PIN_NAME": "\"soc_ddr_inst1\"",
"INTF_AXIM": "1'b1",
"INTF_CI_0": "1'b1",
"INTF_CI_1": "1'b1",
"INTF_CI_2": "1'b1",
"INTF_CI_3": "1'b1",
"CO_DEBUG": "1'b0",
"INTF_JTAG_TYPE": "0",
"INTF_UINTR": "9",
"PERI_SPI_0": "1'b1",
"PERI_SPI_1": "1'b0",
"PERI_SPI_2": "1'b0",
"PERI_I2C_0": "1'b1",
"PERI_I2C_1": "1'b0",
"PERI_I2C_2": "1'b0",
"PERI_GPIO_0": "1'b1",
"PERI_GPIO_1": "1'b0",
"PERI_WDT_0": "1'b1",
"PERI_APB_0": "1'b1",
"PERI_APB_1": "1'b0",
"PERI_APB_2": "1'b0",
"PERI_APB_3": "1'b0",
"PERI_APB_4": "1'b0",
"PERI_GEN": "1'b1",
"PERI_UART_0": "1'b1",
"PERI_UART_1": "1'b0",
"PERI_UART_2": "1'b0",
"PERI_GPIO_0_WIDTH": "4",
"PERI_GPIO_1_WIDTH": "4",
"PERI_APB_0_SIZE": "65536",
"PERI_APB_1_SIZE": "4096",
"PERI_APB_2_SIZE": "4096",
"PERI_APB_3_SIZE": "4096",
"PERI_APB_4_SIZE": "4096",
"PERI_FREQ": "200",
"APP_OVERWRITE": "1'b0",
"APP_OVERWRITE_PATH": "\"''\"",
"INTF_JTAG_TAP_SEL": "8",
"INTF_AXIS": "1'b1",
"PERI_PIN_ASSIGN": "1'b1",
"PLL_SOC_MEM_RESOURCE": "\"PLL_TR0\"",
"SYS_FREQ": "1000",
"SYS_FREQ_HIDDEN": "1000",
"PLL_SOC_SYS_CLKOUT3_FREQ": "\"250\"",
"PLL_SOC_SYS_CLKOUT3_PHASE": "\"0\"",
"PLL_SOC_MEM_CLKOUT3_FREQ": "\"250\"",
"PLL_SOC_MEM_CLKOUT3_PHASE": "\"0\"",
"PLL_SOC_MEM_CLKOUT4_PHASE": "\"0\"",
"PLL_SOC_SYS_RESOURCE": "\"PLL_BL0\"",
"PLL_LPDDR4_RESOURCE": "\"PLL_BL2\"",
"PLL_RES_ASSIGN": "1'b0",
"PLL_SOC_SYS_CLKOUT0_FREQ": "\"100\"",
"PLL_SOC_SYS_CLKOUT0_PHASE": "\"0\"",
"PLL_SOC_MEM_CLKOUT0_FREQ": "\"100\"",
"PLL_SOC_MEM_CLKOUT0_PHASE": "\"0\"",
"PLL_LPDDR4_CLKOUT1_FREQ": "\"33\"",
"PLL_LPDDR4_CLKOUT1_PHASE": "\"0\"",
"MEM_FREQ": "250",
"AXIM_FREQ": "250",
"CFU_FREQ": "125",
"DDR_FREQ": "800",
"PLL_RES_ASSIGN_2": "1'b0",
"DDR_RES_ASSIGN": "1'b0",
"PERI_RES_ASSIGN": "1'b0",
"PLL_SOC_SYS_EXT_CLK_SRC": "1",
"PLL_SOC_MEM_EXT_CLK_SRC": "0",
"PERI_SDHC": "1'b0",
"PERI_TSEMAC": "1'b0",
"SW_FTDI_CH_NUM": "6011",
"SW_APP_SIZE": "2044",
"SW_APP_SIZE_CUSTOM": "0",
"SW_STACK_SIZE": "8",
"SW_STACK_SIZE_CUSTOM": "0",
"SW_BOARD": "\"Ti375C529 Development Kit\"",
"SW_BOARD_CUSTOM": "\"\"",
"SW_FTDI_TARGET_CH": "1",
"SW_FTDI_CH_NUM_SOFT": "6011",
"SW_FTDI_TARGET_CH_SOFT": "0",
"SW_FRTOS_APP_SIZE": "16380",
"SW_FRTOS_APP_SIZE_CUSTOM": "0",
"SW_FRTOS_STACK_SIZE": "4",
"SW_FRTOS_STACK_SIZE_CUSTOM": "0",
"PACKAGE_TYPE": "\"529\"",
"FAMILY_TYPE": "\"TITANIUM\"",
"AXI_PIPELINE": "1'b0",
"AXI_WRITE_BUFFER": "1'b0"
},
"output": {
"external_script_Peripheral_Generator": [],
"external_source_source": [],
"external_script_PT_Configuration": [],
"external_script_Peripheral_Post_Script": [],
"external_script_Embedded_SW": []
},
"ooc_synthesis": {},
"sw_version": "2026.1.132",
"external_path_option": "RELATIVE_PATH"
}

8069
Ti375C529_devkit/ip/EfxSapphireHpSoc_slb/source/Axi4PeripheralTop.v Normal file
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8
Ti375C529_devkit/ip/EfxSapphireHpSoc_slb/source/peri_config Normal file
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--apbSlave name=io_apbSlave_0,address=0x100000,size=65536
--uart name=system_uart_0_io,address=0x10000,interruptId=0
--peripheralFrequency 200000000
--PeripheralClock true
--i2c name=system_i2c_0_io,address=0x20000,interruptId=6
--watchdog name=system_watchdog,address=0x50000,interruptId=13,prescalerWidth=24,counters=2,countersWidth=16
--spi name=system_spi_0_io,address=0x30000,interruptId=3,width=8,ssCount=4
--gpio name=system_gpio_0_io,address=0x40000,width=4,interrupts="0->9;1->10"

2
Ti375C529_devkit/ip/gAXIM_2to1_switch/axi_interconnect.vh Normal file
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@@ -0,0 +1,2 @@
localparam M_BASE_ADDR = {32'h41000000,32'h40000000,32'h30000000,32'h20000000,32'h11100000,32'h11000000,32'h10000000,32'h0};
localparam M_ADDR_WIDTH = {32'd20,32'd24,32'd28,32'd28,32'd20,32'd12,32'd24,32'd32};

1361
Ti375C529_devkit/ip/gAXIM_2to1_switch/gAXIM_2to1_switch.v Normal file
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53
Ti375C529_devkit/ip/gAXIM_2to1_switch/gAXIM_2to1_switch_define.vh Normal file
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@@ -0,0 +1,53 @@
// =============================================================================
// Generated by efx_ipmgr
// Version: 2026.1.132
// IP Version: 5.6
// =============================================================================
////////////////////////////////////////////////////////////////////////////////
// Copyright (C) 2013-2026 Efinix Inc. All rights reserved.
//
// This document contains proprietary information which is
// protected by copyright. All rights are reserved. This notice
// refers to original work by Efinix, Inc. which may be derivitive
// of other work distributed under license of the authors. In the
// case of derivative work, nothing in this notice overrides the
// original author's license agreement. Where applicable, the
// original license agreement is included in it's original
// unmodified form immediately below this header.
//
// WARRANTY DISCLAIMER.
// THE DESIGN, CODE, OR INFORMATION ARE PROVIDED “AS IS” AND
// EFINIX MAKES NO WARRANTIES, EXPRESS OR IMPLIED WITH
// RESPECT THERETO, AND EXPRESSLY DISCLAIMS ANY IMPLIED WARRANTIES,
// INCLUDING, WITHOUT LIMITATION, THE IMPLIED WARRANTIES OF
// MERCHANTABILITY, NON-INFRINGEMENT AND FITNESS FOR A PARTICULAR
// PURPOSE. SOME STATES DO NOT ALLOW EXCLUSIONS OF AN IMPLIED
// WARRANTY, SO THIS DISCLAIMER MAY NOT APPLY TO LICENSEE.
//
// LIMITATION OF LIABILITY.
// NOTWITHSTANDING ANYTHING TO THE CONTRARY, EXCEPT FOR BODILY
// INJURY, EFINIX SHALL NOT BE LIABLE WITH RESPECT TO ANY SUBJECT
// MATTER OF THIS AGREEMENT UNDER TORT, CONTRACT, STRICT LIABILITY
// OR ANY OTHER LEGAL OR EQUITABLE THEORY (I) FOR ANY INDIRECT,
// SPECIAL, INCIDENTAL, EXEMPLARY OR CONSEQUENTIAL DAMAGES OF ANY
// CHARACTER INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF
// GOODWILL, DATA OR PROFIT, WORK STOPPAGE, OR COMPUTER FAILURE OR
// MALFUNCTION, OR IN ANY EVENT (II) FOR ANY AMOUNT IN EXCESS, IN
// THE AGGREGATE, OF THE FEE PAID BY LICENSEE TO EFINIX HEREUNDER
// (OR, IF THE FEE HAS BEEN WAIVED, $100), EVEN IF EFINIX SHALL HAVE
// BEEN INFORMED OF THE POSSIBILITY OF SUCH DAMAGES. SOME STATES DO
// NOT ALLOW THE EXCLUSION OR LIMITATION OF INCIDENTAL OR
// CONSEQUENTIAL DAMAGES, SO THIS LIMITATION AND EXCLUSION MAY NOT
// APPLY TO LICENSEE.
//
////////////////////////////////////////////////////////////////////////////////
localparam ARB_MODE = "ROUND_ROBIN_1";
localparam S_PORTS = 2;
localparam DATA_WIDTH = 128;
localparam ADDR_WIDTH = 32;
localparam M_PORTS = 1;
localparam ID_WIDTH = 8;
localparam USER_WIDTH = 3;
localparam PROTOCOL = "AXI4";

137
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// =============================================================================
// Generated by efx_ipmgr
// Version: 2026.1.132
// IP Version: 5.6
// =============================================================================
////////////////////////////////////////////////////////////////////////////////
// Copyright (C) 2013-2026 Efinix Inc. All rights reserved.
//
// This document contains proprietary information which is
// protected by copyright. All rights are reserved. This notice
// refers to original work by Efinix, Inc. which may be derivitive
// of other work distributed under license of the authors. In the
// case of derivative work, nothing in this notice overrides the
// original author's license agreement. Where applicable, the
// original license agreement is included in it's original
// unmodified form immediately below this header.
//
// WARRANTY DISCLAIMER.
// THE DESIGN, CODE, OR INFORMATION ARE PROVIDED “AS IS” AND
// EFINIX MAKES NO WARRANTIES, EXPRESS OR IMPLIED WITH
// RESPECT THERETO, AND EXPRESSLY DISCLAIMS ANY IMPLIED WARRANTIES,
// INCLUDING, WITHOUT LIMITATION, THE IMPLIED WARRANTIES OF
// MERCHANTABILITY, NON-INFRINGEMENT AND FITNESS FOR A PARTICULAR
// PURPOSE. SOME STATES DO NOT ALLOW EXCLUSIONS OF AN IMPLIED
// WARRANTY, SO THIS DISCLAIMER MAY NOT APPLY TO LICENSEE.
//
// LIMITATION OF LIABILITY.
// NOTWITHSTANDING ANYTHING TO THE CONTRARY, EXCEPT FOR BODILY
// INJURY, EFINIX SHALL NOT BE LIABLE WITH RESPECT TO ANY SUBJECT
// MATTER OF THIS AGREEMENT UNDER TORT, CONTRACT, STRICT LIABILITY
// OR ANY OTHER LEGAL OR EQUITABLE THEORY (I) FOR ANY INDIRECT,
// SPECIAL, INCIDENTAL, EXEMPLARY OR CONSEQUENTIAL DAMAGES OF ANY
// CHARACTER INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF
// GOODWILL, DATA OR PROFIT, WORK STOPPAGE, OR COMPUTER FAILURE OR
// MALFUNCTION, OR IN ANY EVENT (II) FOR ANY AMOUNT IN EXCESS, IN
// THE AGGREGATE, OF THE FEE PAID BY LICENSEE TO EFINIX HEREUNDER
// (OR, IF THE FEE HAS BEEN WAIVED, $100), EVEN IF EFINIX SHALL HAVE
// BEEN INFORMED OF THE POSSIBILITY OF SUCH DAMAGES. SOME STATES DO
// NOT ALLOW THE EXCLUSION OR LIMITATION OF INCIDENTAL OR
// CONSEQUENTIAL DAMAGES, SO THIS LIMITATION AND EXCLUSION MAY NOT
// APPLY TO LICENSEE.
//
////////////////////////////////////////////////////////////////////////////////
gAXIM_2to1_switch u_gAXIM_2to1_switch
(
.rst_n ( rst_n ),
.clk ( clk ),
.s_axi_awvalid ( s_axi_awvalid ),
.s_axi_awaddr ( s_axi_awaddr ),
.s_axi_awlock ( s_axi_awlock ),
.s_axi_awready ( s_axi_awready ),
.s_axi_arvalid ( s_axi_arvalid ),
.s_axi_araddr ( s_axi_araddr ),
.s_axi_arlock ( s_axi_arlock ),
.s_axi_arready ( s_axi_arready ),
.s_axi_wvalid ( s_axi_wvalid ),
.s_axi_wlast ( s_axi_wlast ),
.s_axi_wid ( s_axi_wid ),
.s_axi_bready ( s_axi_bready ),
.s_axi_bresp ( s_axi_bresp ),
.s_axi_rready ( s_axi_rready ),
.s_axi_bid ( s_axi_bid ),
.s_axi_rid ( s_axi_rid ),
.s_axi_wdata ( s_axi_wdata ),
.s_axi_rdata ( s_axi_rdata ),
.s_axi_rresp ( s_axi_rresp ),
.s_axi_bvalid ( s_axi_bvalid ),
.s_axi_rvalid ( s_axi_rvalid ),
.s_axi_rlast ( s_axi_rlast ),
.s_axi_wstrb ( s_axi_wstrb ),
.m_axi_awvalid ( m_axi_awvalid ),
.m_axi_awaddr ( m_axi_awaddr ),
.m_axi_awlock ( m_axi_awlock ),
.m_axi_awready ( m_axi_awready ),
.m_axi_arvalid ( m_axi_arvalid ),
.m_axi_araddr ( m_axi_araddr ),
.m_axi_arlock ( m_axi_arlock ),
.m_axi_arready ( m_axi_arready ),
.m_axi_wvalid ( m_axi_wvalid ),
.m_axi_wlast ( m_axi_wlast ),
.m_axi_bready ( m_axi_bready ),
.m_axi_bresp ( m_axi_bresp ),
.m_axi_rready ( m_axi_rready ),
.m_axi_bid ( m_axi_bid ),
.m_axi_rid ( m_axi_rid ),
.m_axi_wdata ( m_axi_wdata ),
.m_axi_rdata ( m_axi_rdata ),
.m_axi_rresp ( m_axi_rresp ),
.m_axi_bvalid ( m_axi_bvalid ),
.m_axi_rvalid ( m_axi_rvalid ),
.m_axi_rlast ( m_axi_rlast ),
.m_axi_wstrb ( m_axi_wstrb ),
.m_axi_wready ( m_axi_wready ),
.s_axi_wready ( s_axi_wready ),
.s_axi_awprot ( s_axi_awprot ),
.s_axi_awcache ( s_axi_awcache ),
.s_axi_awqos ( s_axi_awqos ),
.s_axi_awuser ( s_axi_awuser ),
.s_axi_arqos ( s_axi_arqos ),
.s_axi_arcache ( s_axi_arcache ),
.m_axi_awprot ( m_axi_awprot ),
.s_axi_arid ( s_axi_arid ),
.s_axi_arsize ( s_axi_arsize ),
.s_axi_arlen ( s_axi_arlen ),
.s_axi_arburst ( s_axi_arburst ),
.s_axi_arprot ( s_axi_arprot ),
.s_axi_awid ( s_axi_awid ),
.s_axi_awburst ( s_axi_awburst ),
.s_axi_awlen ( s_axi_awlen ),
.s_axi_awsize ( s_axi_awsize ),
.m_axi_awid ( m_axi_awid ),
.m_axi_awburst ( m_axi_awburst ),
.m_axi_awlen ( m_axi_awlen ),
.m_axi_awsize ( m_axi_awsize ),
.m_axi_awcache ( m_axi_awcache ),
.m_axi_awqos ( m_axi_awqos ),
.m_axi_awuser ( m_axi_awuser ),
.m_axi_arprot ( m_axi_arprot ),
.m_axi_arburst ( m_axi_arburst ),
.m_axi_arlen ( m_axi_arlen ),
.m_axi_arsize ( m_axi_arsize ),
.m_axi_arcache ( m_axi_arcache ),
.m_axi_arqos ( m_axi_arqos ),
.m_axi_aruser ( m_axi_aruser ),
.m_axi_awregion ( m_axi_awregion ),
.m_axi_arregion ( m_axi_arregion ),
.m_axi_arid ( m_axi_arid ),
.m_axi_wuser ( m_axi_wuser ),
.m_axi_ruser ( m_axi_ruser ),
.m_axi_buser ( m_axi_buser ),
.s_axi_aruser ( s_axi_aruser ),
.s_axi_wuser ( s_axi_wuser ),
.s_axi_buser ( s_axi_buser ),
.s_axi_ruser ( s_axi_ruser )
);

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--------------------------------------------------------------------------------
-- Copyright (C) 2013-2026 Efinix Inc. All rights reserved.
--
-- This document contains proprietary information which is
-- protected by copyright. All rights are reserved. This notice
-- refers to original work by Efinix, Inc. which may be derivitive
-- of other work distributed under license of the authors. In the
-- case of derivative work, nothing in this notice overrides the
-- original author's license agreement. Where applicable, the
-- original license agreement is included in it's original
-- unmodified form immediately below this header.
--
-- WARRANTY DISCLAIMER.
-- THE DESIGN, CODE, OR INFORMATION ARE PROVIDED “AS IS” AND
-- EFINIX MAKES NO WARRANTIES, EXPRESS OR IMPLIED WITH
-- RESPECT THERETO, AND EXPRESSLY DISCLAIMS ANY IMPLIED WARRANTIES,
-- INCLUDING, WITHOUT LIMITATION, THE IMPLIED WARRANTIES OF
-- MERCHANTABILITY, NON-INFRINGEMENT AND FITNESS FOR A PARTICULAR
-- PURPOSE. SOME STATES DO NOT ALLOW EXCLUSIONS OF AN IMPLIED
-- WARRANTY, SO THIS DISCLAIMER MAY NOT APPLY TO LICENSEE.
--
-- LIMITATION OF LIABILITY.
-- NOTWITHSTANDING ANYTHING TO THE CONTRARY, EXCEPT FOR BODILY
-- INJURY, EFINIX SHALL NOT BE LIABLE WITH RESPECT TO ANY SUBJECT
-- MATTER OF THIS AGREEMENT UNDER TORT, CONTRACT, STRICT LIABILITY
-- OR ANY OTHER LEGAL OR EQUITABLE THEORY (I) FOR ANY INDIRECT,
-- SPECIAL, INCIDENTAL, EXEMPLARY OR CONSEQUENTIAL DAMAGES OF ANY
-- CHARACTER INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF
-- GOODWILL, DATA OR PROFIT, WORK STOPPAGE, OR COMPUTER FAILURE OR
-- MALFUNCTION, OR IN ANY EVENT (II) FOR ANY AMOUNT IN EXCESS, IN
-- THE AGGREGATE, OF THE FEE PAID BY LICENSEE TO EFINIX HEREUNDER
-- (OR, IF THE FEE HAS BEEN WAIVED, $100), EVEN IF EFINIX SHALL HAVE
-- BEEN INFORMED OF THE POSSIBILITY OF SUCH DAMAGES. SOME STATES DO
-- NOT ALLOW THE EXCLUSION OR LIMITATION OF INCIDENTAL OR
-- CONSEQUENTIAL DAMAGES, SO THIS LIMITATION AND EXCLUSION MAY NOT
-- APPLY TO LICENSEE.
--
--------------------------------------------------------------------------------
------------- Begin Cut here for COMPONENT Declaration ------
component gAXIM_2to1_switch is
port (
rst_n : in std_logic;
clk : in std_logic;
s_axi_awvalid : in std_logic_vector(1 downto 0);
s_axi_awaddr : in std_logic_vector(63 downto 0);
s_axi_awlock : in std_logic_vector(3 downto 0);
s_axi_awready : out std_logic_vector(1 downto 0);
s_axi_arvalid : in std_logic_vector(1 downto 0);
s_axi_araddr : in std_logic_vector(63 downto 0);
s_axi_arlock : in std_logic_vector(3 downto 0);
s_axi_arready : out std_logic_vector(1 downto 0);
s_axi_wvalid : in std_logic_vector(1 downto 0);
s_axi_wlast : in std_logic_vector(1 downto 0);
s_axi_wid : in std_logic_vector(15 downto 0);
s_axi_bready : in std_logic_vector(1 downto 0);
s_axi_bresp : out std_logic_vector(3 downto 0);
s_axi_rready : in std_logic_vector(1 downto 0);
s_axi_bid : out std_logic_vector(15 downto 0);
s_axi_rid : out std_logic_vector(15 downto 0);
s_axi_wdata : in std_logic_vector(255 downto 0);
s_axi_rdata : out std_logic_vector(255 downto 0);
s_axi_rresp : out std_logic_vector(3 downto 0);
s_axi_bvalid : out std_logic_vector(1 downto 0);
s_axi_rvalid : out std_logic_vector(1 downto 0);
s_axi_rlast : out std_logic_vector(1 downto 0);
s_axi_wstrb : in std_logic_vector(31 downto 0);
m_axi_awvalid : out std_logic_vector(0 to 0);
m_axi_awaddr : out std_logic_vector(31 downto 0);
m_axi_awlock : out std_logic_vector(1 downto 0);
m_axi_awready : in std_logic_vector(0 to 0);
m_axi_arvalid : out std_logic_vector(0 to 0);
m_axi_araddr : out std_logic_vector(31 downto 0);
m_axi_arlock : out std_logic_vector(1 downto 0);
m_axi_arready : in std_logic_vector(0 to 0);
m_axi_wvalid : out std_logic_vector(0 to 0);
m_axi_wlast : out std_logic_vector(0 to 0);
m_axi_bready : out std_logic_vector(0 to 0);
m_axi_bresp : in std_logic_vector(1 downto 0);
m_axi_rready : out std_logic_vector(0 to 0);
m_axi_bid : in std_logic_vector(7 downto 0);
m_axi_rid : in std_logic_vector(7 downto 0);
m_axi_wdata : out std_logic_vector(127 downto 0);
m_axi_rdata : in std_logic_vector(127 downto 0);
m_axi_rresp : in std_logic_vector(1 downto 0);
m_axi_bvalid : in std_logic_vector(0 to 0);
m_axi_rvalid : in std_logic_vector(0 to 0);
m_axi_rlast : in std_logic_vector(0 to 0);
m_axi_wstrb : out std_logic_vector(15 downto 0);
m_axi_wready : in std_logic_vector(0 to 0);
s_axi_wready : out std_logic_vector(1 downto 0);
s_axi_awprot : in std_logic_vector(5 downto 0);
s_axi_awcache : in std_logic_vector(7 downto 0);
s_axi_awqos : in std_logic_vector(7 downto 0);
s_axi_awuser : in std_logic_vector(5 downto 0);
s_axi_arqos : in std_logic_vector(7 downto 0);
s_axi_arcache : in std_logic_vector(7 downto 0);
m_axi_awprot : out std_logic_vector(2 downto 0);
s_axi_arid : in std_logic_vector(15 downto 0);
s_axi_arsize : in std_logic_vector(5 downto 0);
s_axi_arlen : in std_logic_vector(15 downto 0);
s_axi_arburst : in std_logic_vector(3 downto 0);
s_axi_arprot : in std_logic_vector(5 downto 0);
s_axi_awid : in std_logic_vector(15 downto 0);
s_axi_awburst : in std_logic_vector(3 downto 0);
s_axi_awlen : in std_logic_vector(15 downto 0);
s_axi_awsize : in std_logic_vector(5 downto 0);
m_axi_awid : out std_logic_vector(7 downto 0);
m_axi_awburst : out std_logic_vector(1 downto 0);
m_axi_awlen : out std_logic_vector(7 downto 0);
m_axi_awsize : out std_logic_vector(2 downto 0);
m_axi_awcache : out std_logic_vector(3 downto 0);
m_axi_awqos : out std_logic_vector(3 downto 0);
m_axi_awuser : out std_logic_vector(2 downto 0);
m_axi_arprot : out std_logic_vector(2 downto 0);
m_axi_arburst : out std_logic_vector(1 downto 0);
m_axi_arlen : out std_logic_vector(7 downto 0);
m_axi_arsize : out std_logic_vector(2 downto 0);
m_axi_arcache : out std_logic_vector(3 downto 0);
m_axi_arqos : out std_logic_vector(3 downto 0);
m_axi_aruser : out std_logic_vector(2 downto 0);
m_axi_awregion : out std_logic_vector(3 downto 0);
m_axi_arregion : out std_logic_vector(3 downto 0);
m_axi_arid : out std_logic_vector(7 downto 0);
m_axi_wuser : out std_logic_vector(2 downto 0);
m_axi_ruser : in std_logic_vector(2 downto 0);
m_axi_buser : in std_logic_vector(2 downto 0);
s_axi_aruser : in std_logic_vector(5 downto 0);
s_axi_wuser : in std_logic_vector(5 downto 0);
s_axi_buser : out std_logic_vector(5 downto 0);
s_axi_ruser : out std_logic_vector(5 downto 0)
);
end component gAXIM_2to1_switch;
---------------------- End COMPONENT Declaration ------------
------------- Begin Cut here for INSTANTIATION Template -----
u_gAXIM_2to1_switch : gAXIM_2to1_switch
port map (
rst_n => rst_n,
clk => clk,
s_axi_awvalid => s_axi_awvalid,
s_axi_awaddr => s_axi_awaddr,
s_axi_awlock => s_axi_awlock,
s_axi_awready => s_axi_awready,
s_axi_arvalid => s_axi_arvalid,
s_axi_araddr => s_axi_araddr,
s_axi_arlock => s_axi_arlock,
s_axi_arready => s_axi_arready,
s_axi_wvalid => s_axi_wvalid,
s_axi_wlast => s_axi_wlast,
s_axi_wid => s_axi_wid,
s_axi_bready => s_axi_bready,
s_axi_bresp => s_axi_bresp,
s_axi_rready => s_axi_rready,
s_axi_bid => s_axi_bid,
s_axi_rid => s_axi_rid,
s_axi_wdata => s_axi_wdata,
s_axi_rdata => s_axi_rdata,
s_axi_rresp => s_axi_rresp,
s_axi_bvalid => s_axi_bvalid,
s_axi_rvalid => s_axi_rvalid,
s_axi_rlast => s_axi_rlast,
s_axi_wstrb => s_axi_wstrb,
m_axi_awvalid => m_axi_awvalid,
m_axi_awaddr => m_axi_awaddr,
m_axi_awlock => m_axi_awlock,
m_axi_awready => m_axi_awready,
m_axi_arvalid => m_axi_arvalid,
m_axi_araddr => m_axi_araddr,
m_axi_arlock => m_axi_arlock,
m_axi_arready => m_axi_arready,
m_axi_wvalid => m_axi_wvalid,
m_axi_wlast => m_axi_wlast,
m_axi_bready => m_axi_bready,
m_axi_bresp => m_axi_bresp,
m_axi_rready => m_axi_rready,
m_axi_bid => m_axi_bid,
m_axi_rid => m_axi_rid,
m_axi_wdata => m_axi_wdata,
m_axi_rdata => m_axi_rdata,
m_axi_rresp => m_axi_rresp,
m_axi_bvalid => m_axi_bvalid,
m_axi_rvalid => m_axi_rvalid,
m_axi_rlast => m_axi_rlast,
m_axi_wstrb => m_axi_wstrb,
m_axi_wready => m_axi_wready,
s_axi_wready => s_axi_wready,
s_axi_awprot => s_axi_awprot,
s_axi_awcache => s_axi_awcache,
s_axi_awqos => s_axi_awqos,
s_axi_awuser => s_axi_awuser,
s_axi_arqos => s_axi_arqos,
s_axi_arcache => s_axi_arcache,
m_axi_awprot => m_axi_awprot,
s_axi_arid => s_axi_arid,
s_axi_arsize => s_axi_arsize,
s_axi_arlen => s_axi_arlen,
s_axi_arburst => s_axi_arburst,
s_axi_arprot => s_axi_arprot,
s_axi_awid => s_axi_awid,
s_axi_awburst => s_axi_awburst,
s_axi_awlen => s_axi_awlen,
s_axi_awsize => s_axi_awsize,
m_axi_awid => m_axi_awid,
m_axi_awburst => m_axi_awburst,
m_axi_awlen => m_axi_awlen,
m_axi_awsize => m_axi_awsize,
m_axi_awcache => m_axi_awcache,
m_axi_awqos => m_axi_awqos,
m_axi_awuser => m_axi_awuser,
m_axi_arprot => m_axi_arprot,
m_axi_arburst => m_axi_arburst,
m_axi_arlen => m_axi_arlen,
m_axi_arsize => m_axi_arsize,
m_axi_arcache => m_axi_arcache,
m_axi_arqos => m_axi_arqos,
m_axi_aruser => m_axi_aruser,
m_axi_awregion => m_axi_awregion,
m_axi_arregion => m_axi_arregion,
m_axi_arid => m_axi_arid,
m_axi_wuser => m_axi_wuser,
m_axi_ruser => m_axi_ruser,
m_axi_buser => m_axi_buser,
s_axi_aruser => s_axi_aruser,
s_axi_wuser => s_axi_wuser,
s_axi_buser => s_axi_buser,
s_axi_ruser => s_axi_ruser
);
------------------------ End INSTANTIATION Template ---------

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{
"args": [
"-o",
"gAXIM_2to1_switch",
"--base_path",
"ip",
"--vlnv",
{
"vendor": "efinixinc.com",
"library": "axi_infra",
"name": "efx_axi_interconnect",
"version": "5.6"
}
],
"conf": {
"ARB_MODE": "\"ROUND_ROBIN_1\"",
"S_PORTS": "1",
"TABLE0_AXI_S0__MIN": "32'd0",
"TABLE0_AXI_S1__MIN": "32'd512",
"TABLE0_AXI_S2__MIN": "32'd285212672",
"TABLE0_AXI_S3__MIN": "32'd286261248",
"TABLE0_AXI_S4__MIN": "32'd536870912",
"TABLE0_AXI_S5__MIN": "32'd805306368",
"TABLE0_AXI_S6__MIN": "32'd1073741824",
"TABLE0_AXI_S7__MIN": "32'd1090519040",
"TABLE0_AXI_S0__MAX": "32'd9",
"TABLE0_AXI_S1__MAX": "32'd8",
"TABLE0_AXI_S2__MAX": "32'd12",
"TABLE0_AXI_S3__MAX": "32'd20",
"TABLE0_AXI_S4__MAX": "32'd28",
"TABLE0_AXI_S5__MAX": "32'd28",
"TABLE0_AXI_S6__MAX": "32'd24",
"TABLE0_AXI_S7__MAX": "32'd20",
"DATA_WIDTH": "32",
"ADDR_WIDTH": "32",
"M_PORTS": "2",
"ID_WIDTH": "8",
"USER_WIDTH": "3",
"PROTOCOL": "\"AXI4_LITE\""
},
"output": {
"external_script_generator": [],
"external_source_source": [],
"external_example_example": [],
"external_testbench_synopsys": [],
"external_testbench_modelsim": [],
"external_testbench_ncsim": [],
"external_testbench_aldec": [],
"external_testbench_testbench": []
},
"ooc_synthesis": {},
"sw_version": "2026.1.132",
"external_path_option": "RELATIVE_PATH"
}

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Ti375C529_devkit/ip/gAXIS_1to3_switch/axi_interconnect.vh Normal file
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localparam M_BASE_ADDR = {32'h41000000,32'h40000000,32'h30000000,32'h20000000,32'h11100000,32'h1100000,32'h1000000,32'h0};
localparam M_ADDR_WIDTH = {32'd20,32'd24,32'd28,32'd28,32'd20,32'd16,32'd16,32'd24};

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// =============================================================================
// Generated by efx_ipmgr
// Version: 2026.1.132
// IP Version: 5.6
// =============================================================================
////////////////////////////////////////////////////////////////////////////////
// Copyright (C) 2013-2026 Efinix Inc. All rights reserved.
//
// This document contains proprietary information which is
// protected by copyright. All rights are reserved. This notice
// refers to original work by Efinix, Inc. which may be derivitive
// of other work distributed under license of the authors. In the
// case of derivative work, nothing in this notice overrides the
// original author's license agreement. Where applicable, the
// original license agreement is included in it's original
// unmodified form immediately below this header.
//
// WARRANTY DISCLAIMER.
// THE DESIGN, CODE, OR INFORMATION ARE PROVIDED “AS IS” AND
// EFINIX MAKES NO WARRANTIES, EXPRESS OR IMPLIED WITH
// RESPECT THERETO, AND EXPRESSLY DISCLAIMS ANY IMPLIED WARRANTIES,
// INCLUDING, WITHOUT LIMITATION, THE IMPLIED WARRANTIES OF
// MERCHANTABILITY, NON-INFRINGEMENT AND FITNESS FOR A PARTICULAR
// PURPOSE. SOME STATES DO NOT ALLOW EXCLUSIONS OF AN IMPLIED
// WARRANTY, SO THIS DISCLAIMER MAY NOT APPLY TO LICENSEE.
//
// LIMITATION OF LIABILITY.
// NOTWITHSTANDING ANYTHING TO THE CONTRARY, EXCEPT FOR BODILY
// INJURY, EFINIX SHALL NOT BE LIABLE WITH RESPECT TO ANY SUBJECT
// MATTER OF THIS AGREEMENT UNDER TORT, CONTRACT, STRICT LIABILITY
// OR ANY OTHER LEGAL OR EQUITABLE THEORY (I) FOR ANY INDIRECT,
// SPECIAL, INCIDENTAL, EXEMPLARY OR CONSEQUENTIAL DAMAGES OF ANY
// CHARACTER INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF
// GOODWILL, DATA OR PROFIT, WORK STOPPAGE, OR COMPUTER FAILURE OR
// MALFUNCTION, OR IN ANY EVENT (II) FOR ANY AMOUNT IN EXCESS, IN
// THE AGGREGATE, OF THE FEE PAID BY LICENSEE TO EFINIX HEREUNDER
// (OR, IF THE FEE HAS BEEN WAIVED, $100), EVEN IF EFINIX SHALL HAVE
// BEEN INFORMED OF THE POSSIBILITY OF SUCH DAMAGES. SOME STATES DO
// NOT ALLOW THE EXCLUSION OR LIMITATION OF INCIDENTAL OR
// CONSEQUENTIAL DAMAGES, SO THIS LIMITATION AND EXCLUSION MAY NOT
// APPLY TO LICENSEE.
//
////////////////////////////////////////////////////////////////////////////////
localparam ARB_MODE = "ROUND_ROBIN_1";
localparam S_PORTS = 1;
localparam DATA_WIDTH = 32;
localparam ADDR_WIDTH = 32;
localparam M_PORTS = 3;
localparam ID_WIDTH = 8;
localparam USER_WIDTH = 3;
localparam PROTOCOL = "AXI4";

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// =============================================================================
// Generated by efx_ipmgr
// Version: 2026.1.132
// IP Version: 5.6
// =============================================================================
////////////////////////////////////////////////////////////////////////////////
// Copyright (C) 2013-2026 Efinix Inc. All rights reserved.
//
// This document contains proprietary information which is
// protected by copyright. All rights are reserved. This notice
// refers to original work by Efinix, Inc. which may be derivitive
// of other work distributed under license of the authors. In the
// case of derivative work, nothing in this notice overrides the
// original author's license agreement. Where applicable, the
// original license agreement is included in it's original
// unmodified form immediately below this header.
//
// WARRANTY DISCLAIMER.
// THE DESIGN, CODE, OR INFORMATION ARE PROVIDED “AS IS” AND
// EFINIX MAKES NO WARRANTIES, EXPRESS OR IMPLIED WITH
// RESPECT THERETO, AND EXPRESSLY DISCLAIMS ANY IMPLIED WARRANTIES,
// INCLUDING, WITHOUT LIMITATION, THE IMPLIED WARRANTIES OF
// MERCHANTABILITY, NON-INFRINGEMENT AND FITNESS FOR A PARTICULAR
// PURPOSE. SOME STATES DO NOT ALLOW EXCLUSIONS OF AN IMPLIED
// WARRANTY, SO THIS DISCLAIMER MAY NOT APPLY TO LICENSEE.
//
// LIMITATION OF LIABILITY.
// NOTWITHSTANDING ANYTHING TO THE CONTRARY, EXCEPT FOR BODILY
// INJURY, EFINIX SHALL NOT BE LIABLE WITH RESPECT TO ANY SUBJECT
// MATTER OF THIS AGREEMENT UNDER TORT, CONTRACT, STRICT LIABILITY
// OR ANY OTHER LEGAL OR EQUITABLE THEORY (I) FOR ANY INDIRECT,
// SPECIAL, INCIDENTAL, EXEMPLARY OR CONSEQUENTIAL DAMAGES OF ANY
// CHARACTER INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF
// GOODWILL, DATA OR PROFIT, WORK STOPPAGE, OR COMPUTER FAILURE OR
// MALFUNCTION, OR IN ANY EVENT (II) FOR ANY AMOUNT IN EXCESS, IN
// THE AGGREGATE, OF THE FEE PAID BY LICENSEE TO EFINIX HEREUNDER
// (OR, IF THE FEE HAS BEEN WAIVED, $100), EVEN IF EFINIX SHALL HAVE
// BEEN INFORMED OF THE POSSIBILITY OF SUCH DAMAGES. SOME STATES DO
// NOT ALLOW THE EXCLUSION OR LIMITATION OF INCIDENTAL OR
// CONSEQUENTIAL DAMAGES, SO THIS LIMITATION AND EXCLUSION MAY NOT
// APPLY TO LICENSEE.
//
////////////////////////////////////////////////////////////////////////////////
gAXIS_1to3_switch u_gAXIS_1to3_switch
(
.rst_n ( rst_n ),
.clk ( clk ),
.s_axi_awvalid ( s_axi_awvalid ),
.s_axi_awaddr ( s_axi_awaddr ),
.s_axi_awlock ( s_axi_awlock ),
.s_axi_awready ( s_axi_awready ),
.s_axi_arvalid ( s_axi_arvalid ),
.s_axi_araddr ( s_axi_araddr ),
.s_axi_arlock ( s_axi_arlock ),
.s_axi_arready ( s_axi_arready ),
.s_axi_wvalid ( s_axi_wvalid ),
.s_axi_wlast ( s_axi_wlast ),
.s_axi_wid ( s_axi_wid ),
.s_axi_bready ( s_axi_bready ),
.s_axi_bresp ( s_axi_bresp ),
.s_axi_rready ( s_axi_rready ),
.s_axi_bid ( s_axi_bid ),
.s_axi_rid ( s_axi_rid ),
.s_axi_wdata ( s_axi_wdata ),
.s_axi_rdata ( s_axi_rdata ),
.s_axi_rresp ( s_axi_rresp ),
.s_axi_bvalid ( s_axi_bvalid ),
.s_axi_rvalid ( s_axi_rvalid ),
.s_axi_rlast ( s_axi_rlast ),
.s_axi_wstrb ( s_axi_wstrb ),
.m_axi_awvalid ( m_axi_awvalid ),
.m_axi_awaddr ( m_axi_awaddr ),
.m_axi_awlock ( m_axi_awlock ),
.m_axi_awready ( m_axi_awready ),
.m_axi_arvalid ( m_axi_arvalid ),
.m_axi_araddr ( m_axi_araddr ),
.m_axi_arlock ( m_axi_arlock ),
.m_axi_arready ( m_axi_arready ),
.m_axi_wvalid ( m_axi_wvalid ),
.m_axi_wlast ( m_axi_wlast ),
.m_axi_bready ( m_axi_bready ),
.m_axi_bresp ( m_axi_bresp ),
.m_axi_rready ( m_axi_rready ),
.m_axi_bid ( m_axi_bid ),
.m_axi_rid ( m_axi_rid ),
.m_axi_wdata ( m_axi_wdata ),
.m_axi_rdata ( m_axi_rdata ),
.m_axi_rresp ( m_axi_rresp ),
.m_axi_bvalid ( m_axi_bvalid ),
.m_axi_rvalid ( m_axi_rvalid ),
.m_axi_rlast ( m_axi_rlast ),
.m_axi_wstrb ( m_axi_wstrb ),
.m_axi_wready ( m_axi_wready ),
.s_axi_wready ( s_axi_wready ),
.s_axi_awprot ( s_axi_awprot ),
.s_axi_awcache ( s_axi_awcache ),
.s_axi_awqos ( s_axi_awqos ),
.s_axi_awuser ( s_axi_awuser ),
.s_axi_arqos ( s_axi_arqos ),
.s_axi_arcache ( s_axi_arcache ),
.m_axi_awprot ( m_axi_awprot ),
.s_axi_arid ( s_axi_arid ),
.s_axi_arsize ( s_axi_arsize ),
.s_axi_arlen ( s_axi_arlen ),
.s_axi_arburst ( s_axi_arburst ),
.s_axi_arprot ( s_axi_arprot ),
.s_axi_awid ( s_axi_awid ),
.s_axi_awburst ( s_axi_awburst ),
.s_axi_awlen ( s_axi_awlen ),
.s_axi_awsize ( s_axi_awsize ),
.m_axi_awid ( m_axi_awid ),
.m_axi_awburst ( m_axi_awburst ),
.m_axi_awlen ( m_axi_awlen ),
.m_axi_awsize ( m_axi_awsize ),
.m_axi_awcache ( m_axi_awcache ),
.m_axi_awqos ( m_axi_awqos ),
.m_axi_awuser ( m_axi_awuser ),
.m_axi_arprot ( m_axi_arprot ),
.m_axi_arburst ( m_axi_arburst ),
.m_axi_arlen ( m_axi_arlen ),
.m_axi_arsize ( m_axi_arsize ),
.m_axi_arcache ( m_axi_arcache ),
.m_axi_arqos ( m_axi_arqos ),
.m_axi_aruser ( m_axi_aruser ),
.m_axi_awregion ( m_axi_awregion ),
.m_axi_arregion ( m_axi_arregion ),
.m_axi_arid ( m_axi_arid ),
.m_axi_wuser ( m_axi_wuser ),
.m_axi_ruser ( m_axi_ruser ),
.m_axi_buser ( m_axi_buser ),
.s_axi_aruser ( s_axi_aruser ),
.s_axi_wuser ( s_axi_wuser ),
.s_axi_buser ( s_axi_buser ),
.s_axi_ruser ( s_axi_ruser )
);

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--------------------------------------------------------------------------------
-- Copyright (C) 2013-2026 Efinix Inc. All rights reserved.
--
-- This document contains proprietary information which is
-- protected by copyright. All rights are reserved. This notice
-- refers to original work by Efinix, Inc. which may be derivitive
-- of other work distributed under license of the authors. In the
-- case of derivative work, nothing in this notice overrides the
-- original author's license agreement. Where applicable, the
-- original license agreement is included in it's original
-- unmodified form immediately below this header.
--
-- WARRANTY DISCLAIMER.
-- THE DESIGN, CODE, OR INFORMATION ARE PROVIDED “AS IS” AND
-- EFINIX MAKES NO WARRANTIES, EXPRESS OR IMPLIED WITH
-- RESPECT THERETO, AND EXPRESSLY DISCLAIMS ANY IMPLIED WARRANTIES,
-- INCLUDING, WITHOUT LIMITATION, THE IMPLIED WARRANTIES OF
-- MERCHANTABILITY, NON-INFRINGEMENT AND FITNESS FOR A PARTICULAR
-- PURPOSE. SOME STATES DO NOT ALLOW EXCLUSIONS OF AN IMPLIED
-- WARRANTY, SO THIS DISCLAIMER MAY NOT APPLY TO LICENSEE.
--
-- LIMITATION OF LIABILITY.
-- NOTWITHSTANDING ANYTHING TO THE CONTRARY, EXCEPT FOR BODILY
-- INJURY, EFINIX SHALL NOT BE LIABLE WITH RESPECT TO ANY SUBJECT
-- MATTER OF THIS AGREEMENT UNDER TORT, CONTRACT, STRICT LIABILITY
-- OR ANY OTHER LEGAL OR EQUITABLE THEORY (I) FOR ANY INDIRECT,
-- SPECIAL, INCIDENTAL, EXEMPLARY OR CONSEQUENTIAL DAMAGES OF ANY
-- CHARACTER INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF
-- GOODWILL, DATA OR PROFIT, WORK STOPPAGE, OR COMPUTER FAILURE OR
-- MALFUNCTION, OR IN ANY EVENT (II) FOR ANY AMOUNT IN EXCESS, IN
-- THE AGGREGATE, OF THE FEE PAID BY LICENSEE TO EFINIX HEREUNDER
-- (OR, IF THE FEE HAS BEEN WAIVED, $100), EVEN IF EFINIX SHALL HAVE
-- BEEN INFORMED OF THE POSSIBILITY OF SUCH DAMAGES. SOME STATES DO
-- NOT ALLOW THE EXCLUSION OR LIMITATION OF INCIDENTAL OR
-- CONSEQUENTIAL DAMAGES, SO THIS LIMITATION AND EXCLUSION MAY NOT
-- APPLY TO LICENSEE.
--
--------------------------------------------------------------------------------
------------- Begin Cut here for COMPONENT Declaration ------
component gAXIS_1to3_switch is
port (
rst_n : in std_logic;
clk : in std_logic;
s_axi_awvalid : in std_logic_vector(0 to 0);
s_axi_awaddr : in std_logic_vector(31 downto 0);
s_axi_awlock : in std_logic_vector(1 downto 0);
s_axi_awready : out std_logic_vector(0 to 0);
s_axi_arvalid : in std_logic_vector(0 to 0);
s_axi_araddr : in std_logic_vector(31 downto 0);
s_axi_arlock : in std_logic_vector(1 downto 0);
s_axi_arready : out std_logic_vector(0 to 0);
s_axi_wvalid : in std_logic_vector(0 to 0);
s_axi_wlast : in std_logic_vector(0 to 0);
s_axi_wid : in std_logic_vector(7 downto 0);
s_axi_bready : in std_logic_vector(0 to 0);
s_axi_bresp : out std_logic_vector(1 downto 0);
s_axi_rready : in std_logic_vector(0 to 0);
s_axi_bid : out std_logic_vector(7 downto 0);
s_axi_rid : out std_logic_vector(7 downto 0);
s_axi_wdata : in std_logic_vector(31 downto 0);
s_axi_rdata : out std_logic_vector(31 downto 0);
s_axi_rresp : out std_logic_vector(1 downto 0);
s_axi_bvalid : out std_logic_vector(0 to 0);
s_axi_rvalid : out std_logic_vector(0 to 0);
s_axi_rlast : out std_logic_vector(0 to 0);
s_axi_wstrb : in std_logic_vector(3 downto 0);
m_axi_awvalid : out std_logic_vector(2 downto 0);
m_axi_awaddr : out std_logic_vector(95 downto 0);
m_axi_awlock : out std_logic_vector(5 downto 0);
m_axi_awready : in std_logic_vector(2 downto 0);
m_axi_arvalid : out std_logic_vector(2 downto 0);
m_axi_araddr : out std_logic_vector(95 downto 0);
m_axi_arlock : out std_logic_vector(5 downto 0);
m_axi_arready : in std_logic_vector(2 downto 0);
m_axi_wvalid : out std_logic_vector(2 downto 0);
m_axi_wlast : out std_logic_vector(2 downto 0);
m_axi_bready : out std_logic_vector(2 downto 0);
m_axi_bresp : in std_logic_vector(5 downto 0);
m_axi_rready : out std_logic_vector(2 downto 0);
m_axi_bid : in std_logic_vector(23 downto 0);
m_axi_rid : in std_logic_vector(23 downto 0);
m_axi_wdata : out std_logic_vector(95 downto 0);
m_axi_rdata : in std_logic_vector(95 downto 0);
m_axi_rresp : in std_logic_vector(5 downto 0);
m_axi_bvalid : in std_logic_vector(2 downto 0);
m_axi_rvalid : in std_logic_vector(2 downto 0);
m_axi_rlast : in std_logic_vector(2 downto 0);
m_axi_wstrb : out std_logic_vector(11 downto 0);
m_axi_wready : in std_logic_vector(2 downto 0);
s_axi_wready : out std_logic_vector(0 to 0);
s_axi_awprot : in std_logic_vector(2 downto 0);
s_axi_awcache : in std_logic_vector(3 downto 0);
s_axi_awqos : in std_logic_vector(3 downto 0);
s_axi_awuser : in std_logic_vector(2 downto 0);
s_axi_arqos : in std_logic_vector(3 downto 0);
s_axi_arcache : in std_logic_vector(3 downto 0);
m_axi_awprot : out std_logic_vector(8 downto 0);
s_axi_arid : in std_logic_vector(7 downto 0);
s_axi_arsize : in std_logic_vector(2 downto 0);
s_axi_arlen : in std_logic_vector(7 downto 0);
s_axi_arburst : in std_logic_vector(1 downto 0);
s_axi_arprot : in std_logic_vector(2 downto 0);
s_axi_awid : in std_logic_vector(7 downto 0);
s_axi_awburst : in std_logic_vector(1 downto 0);
s_axi_awlen : in std_logic_vector(7 downto 0);
s_axi_awsize : in std_logic_vector(2 downto 0);
m_axi_awid : out std_logic_vector(23 downto 0);
m_axi_awburst : out std_logic_vector(5 downto 0);
m_axi_awlen : out std_logic_vector(23 downto 0);
m_axi_awsize : out std_logic_vector(8 downto 0);
m_axi_awcache : out std_logic_vector(11 downto 0);
m_axi_awqos : out std_logic_vector(11 downto 0);
m_axi_awuser : out std_logic_vector(8 downto 0);
m_axi_arprot : out std_logic_vector(8 downto 0);
m_axi_arburst : out std_logic_vector(5 downto 0);
m_axi_arlen : out std_logic_vector(23 downto 0);
m_axi_arsize : out std_logic_vector(8 downto 0);
m_axi_arcache : out std_logic_vector(11 downto 0);
m_axi_arqos : out std_logic_vector(11 downto 0);
m_axi_aruser : out std_logic_vector(8 downto 0);
m_axi_awregion : out std_logic_vector(11 downto 0);
m_axi_arregion : out std_logic_vector(11 downto 0);
m_axi_arid : out std_logic_vector(23 downto 0);
m_axi_wuser : out std_logic_vector(8 downto 0);
m_axi_ruser : in std_logic_vector(8 downto 0);
m_axi_buser : in std_logic_vector(8 downto 0);
s_axi_aruser : in std_logic_vector(2 downto 0);
s_axi_wuser : in std_logic_vector(2 downto 0);
s_axi_buser : out std_logic_vector(2 downto 0);
s_axi_ruser : out std_logic_vector(2 downto 0)
);
end component gAXIS_1to3_switch;
---------------------- End COMPONENT Declaration ------------
------------- Begin Cut here for INSTANTIATION Template -----
u_gAXIS_1to3_switch : gAXIS_1to3_switch
port map (
rst_n => rst_n,
clk => clk,
s_axi_awvalid => s_axi_awvalid,
s_axi_awaddr => s_axi_awaddr,
s_axi_awlock => s_axi_awlock,
s_axi_awready => s_axi_awready,
s_axi_arvalid => s_axi_arvalid,
s_axi_araddr => s_axi_araddr,
s_axi_arlock => s_axi_arlock,
s_axi_arready => s_axi_arready,
s_axi_wvalid => s_axi_wvalid,
s_axi_wlast => s_axi_wlast,
s_axi_wid => s_axi_wid,
s_axi_bready => s_axi_bready,
s_axi_bresp => s_axi_bresp,
s_axi_rready => s_axi_rready,
s_axi_bid => s_axi_bid,
s_axi_rid => s_axi_rid,
s_axi_wdata => s_axi_wdata,
s_axi_rdata => s_axi_rdata,
s_axi_rresp => s_axi_rresp,
s_axi_bvalid => s_axi_bvalid,
s_axi_rvalid => s_axi_rvalid,
s_axi_rlast => s_axi_rlast,
s_axi_wstrb => s_axi_wstrb,
m_axi_awvalid => m_axi_awvalid,
m_axi_awaddr => m_axi_awaddr,
m_axi_awlock => m_axi_awlock,
m_axi_awready => m_axi_awready,
m_axi_arvalid => m_axi_arvalid,
m_axi_araddr => m_axi_araddr,
m_axi_arlock => m_axi_arlock,
m_axi_arready => m_axi_arready,
m_axi_wvalid => m_axi_wvalid,
m_axi_wlast => m_axi_wlast,
m_axi_bready => m_axi_bready,
m_axi_bresp => m_axi_bresp,
m_axi_rready => m_axi_rready,
m_axi_bid => m_axi_bid,
m_axi_rid => m_axi_rid,
m_axi_wdata => m_axi_wdata,
m_axi_rdata => m_axi_rdata,
m_axi_rresp => m_axi_rresp,
m_axi_bvalid => m_axi_bvalid,
m_axi_rvalid => m_axi_rvalid,
m_axi_rlast => m_axi_rlast,
m_axi_wstrb => m_axi_wstrb,
m_axi_wready => m_axi_wready,
s_axi_wready => s_axi_wready,
s_axi_awprot => s_axi_awprot,
s_axi_awcache => s_axi_awcache,
s_axi_awqos => s_axi_awqos,
s_axi_awuser => s_axi_awuser,
s_axi_arqos => s_axi_arqos,
s_axi_arcache => s_axi_arcache,
m_axi_awprot => m_axi_awprot,
s_axi_arid => s_axi_arid,
s_axi_arsize => s_axi_arsize,
s_axi_arlen => s_axi_arlen,
s_axi_arburst => s_axi_arburst,
s_axi_arprot => s_axi_arprot,
s_axi_awid => s_axi_awid,
s_axi_awburst => s_axi_awburst,
s_axi_awlen => s_axi_awlen,
s_axi_awsize => s_axi_awsize,
m_axi_awid => m_axi_awid,
m_axi_awburst => m_axi_awburst,
m_axi_awlen => m_axi_awlen,
m_axi_awsize => m_axi_awsize,
m_axi_awcache => m_axi_awcache,
m_axi_awqos => m_axi_awqos,
m_axi_awuser => m_axi_awuser,
m_axi_arprot => m_axi_arprot,
m_axi_arburst => m_axi_arburst,
m_axi_arlen => m_axi_arlen,
m_axi_arsize => m_axi_arsize,
m_axi_arcache => m_axi_arcache,
m_axi_arqos => m_axi_arqos,
m_axi_aruser => m_axi_aruser,
m_axi_awregion => m_axi_awregion,
m_axi_arregion => m_axi_arregion,
m_axi_arid => m_axi_arid,
m_axi_wuser => m_axi_wuser,
m_axi_ruser => m_axi_ruser,
m_axi_buser => m_axi_buser,
s_axi_aruser => s_axi_aruser,
s_axi_wuser => s_axi_wuser,
s_axi_buser => s_axi_buser,
s_axi_ruser => s_axi_ruser
);
------------------------ End INSTANTIATION Template ---------

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{
"args": [
"-o",
"gAXIS_1to3_switch",
"--base_path",
"ip",
"--vlnv",
{
"vendor": "efinixinc.com",
"library": "axi_infra",
"name": "efx_axi_interconnect",
"version": "5.6"
}
],
"conf": {
"ARB_MODE": "\"ROUND_ROBIN_1\"",
"S_PORTS": "1",
"TABLE0_AXI_S0__MIN": "32'd0",
"TABLE0_AXI_S1__MIN": "32'd512",
"TABLE0_AXI_S2__MIN": "32'd285212672",
"TABLE0_AXI_S3__MIN": "32'd286261248",
"TABLE0_AXI_S4__MIN": "32'd536870912",
"TABLE0_AXI_S5__MIN": "32'd805306368",
"TABLE0_AXI_S6__MIN": "32'd1073741824",
"TABLE0_AXI_S7__MIN": "32'd1090519040",
"TABLE0_AXI_S0__MAX": "32'd9",
"TABLE0_AXI_S1__MAX": "32'd8",
"TABLE0_AXI_S2__MAX": "32'd12",
"TABLE0_AXI_S3__MAX": "32'd20",
"TABLE0_AXI_S4__MAX": "32'd28",
"TABLE0_AXI_S5__MAX": "32'd28",
"TABLE0_AXI_S6__MAX": "32'd24",
"TABLE0_AXI_S7__MAX": "32'd20",
"DATA_WIDTH": "32",
"ADDR_WIDTH": "32",
"M_PORTS": "2",
"ID_WIDTH": "8",
"USER_WIDTH": "3",
"PROTOCOL": "\"AXI4_LITE\""
},
"output": {
"external_script_generator": [],
"external_source_source": [],
"external_example_example": [],
"external_testbench_synopsys": [],
"external_testbench_modelsim": [],
"external_testbench_ncsim": [],
"external_testbench_aldec": [],
"external_testbench_testbench": []
},
"ooc_synthesis": {},
"sw_version": "2026.1.132",
"external_path_option": "RELATIVE_PATH"
}

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// =============================================================================
// Generated by efx_ipmgr
// Version: 2025.2.272
// IP Version: 6.4.2
// =============================================================================
////////////////////////////////////////////////////////////////////////////////
// Copyright (C) 2013-2025 Efinix Inc. All rights reserved.
//
// This document contains proprietary information which is
// protected by copyright. All rights are reserved. This notice
// refers to original work by Efinix, Inc. which may be derivitive
// of other work distributed under license of the authors. In the
// case of derivative work, nothing in this notice overrides the
// original author's license agreement. Where applicable, the
// original license agreement is included in it's original
// unmodified form immediately below this header.
//
// WARRANTY DISCLAIMER.
// THE DESIGN, CODE, OR INFORMATION ARE PROVIDED “AS IS” AND
// EFINIX MAKES NO WARRANTIES, EXPRESS OR IMPLIED WITH
// RESPECT THERETO, AND EXPRESSLY DISCLAIMS ANY IMPLIED WARRANTIES,
// INCLUDING, WITHOUT LIMITATION, THE IMPLIED WARRANTIES OF
// MERCHANTABILITY, NON-INFRINGEMENT AND FITNESS FOR A PARTICULAR
// PURPOSE. SOME STATES DO NOT ALLOW EXCLUSIONS OF AN IMPLIED
// WARRANTY, SO THIS DISCLAIMER MAY NOT APPLY TO LICENSEE.
//
// LIMITATION OF LIABILITY.
// NOTWITHSTANDING ANYTHING TO THE CONTRARY, EXCEPT FOR BODILY
// INJURY, EFINIX SHALL NOT BE LIABLE WITH RESPECT TO ANY SUBJECT
// MATTER OF THIS AGREEMENT UNDER TORT, CONTRACT, STRICT LIABILITY
// OR ANY OTHER LEGAL OR EQUITABLE THEORY (I) FOR ANY INDIRECT,
// SPECIAL, INCIDENTAL, EXEMPLARY OR CONSEQUENTIAL DAMAGES OF ANY
// CHARACTER INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF
// GOODWILL, DATA OR PROFIT, WORK STOPPAGE, OR COMPUTER FAILURE OR
// MALFUNCTION, OR IN ANY EVENT (II) FOR ANY AMOUNT IN EXCESS, IN
// THE AGGREGATE, OF THE FEE PAID BY LICENSEE TO EFINIX HEREUNDER
// (OR, IF THE FEE HAS BEEN WAIVED, $100), EVEN IF EFINIX SHALL HAVE
// BEEN INFORMED OF THE POSSIBILITY OF SUCH DAMAGES. SOME STATES DO
// NOT ALLOW THE EXCLUSION OR LIMITATION OF INCIDENTAL OR
// CONSEQUENTIAL DAMAGES, SO THIS LIMITATION AND EXCLUSION MAY NOT
// APPLY TO LICENSEE.
//
////////////////////////////////////////////////////////////////////////////////

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// =============================================================================
// Generated by efx_ipmgr
// Version: 2025.2.272
// IP Version: 6.4.2
// =============================================================================
////////////////////////////////////////////////////////////////////////////////
// Copyright (C) 2013-2025 Efinix Inc. All rights reserved.
//
// This document contains proprietary information which is
// protected by copyright. All rights are reserved. This notice
// refers to original work by Efinix, Inc. which may be derivitive
// of other work distributed under license of the authors. In the
// case of derivative work, nothing in this notice overrides the
// original author's license agreement. Where applicable, the
// original license agreement is included in it's original
// unmodified form immediately below this header.
//
// WARRANTY DISCLAIMER.
// THE DESIGN, CODE, OR INFORMATION ARE PROVIDED “AS IS” AND
// EFINIX MAKES NO WARRANTIES, EXPRESS OR IMPLIED WITH
// RESPECT THERETO, AND EXPRESSLY DISCLAIMS ANY IMPLIED WARRANTIES,
// INCLUDING, WITHOUT LIMITATION, THE IMPLIED WARRANTIES OF
// MERCHANTABILITY, NON-INFRINGEMENT AND FITNESS FOR A PARTICULAR
// PURPOSE. SOME STATES DO NOT ALLOW EXCLUSIONS OF AN IMPLIED
// WARRANTY, SO THIS DISCLAIMER MAY NOT APPLY TO LICENSEE.
//
// LIMITATION OF LIABILITY.
// NOTWITHSTANDING ANYTHING TO THE CONTRARY, EXCEPT FOR BODILY
// INJURY, EFINIX SHALL NOT BE LIABLE WITH RESPECT TO ANY SUBJECT
// MATTER OF THIS AGREEMENT UNDER TORT, CONTRACT, STRICT LIABILITY
// OR ANY OTHER LEGAL OR EQUITABLE THEORY (I) FOR ANY INDIRECT,
// SPECIAL, INCIDENTAL, EXEMPLARY OR CONSEQUENTIAL DAMAGES OF ANY
// CHARACTER INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF
// GOODWILL, DATA OR PROFIT, WORK STOPPAGE, OR COMPUTER FAILURE OR
// MALFUNCTION, OR IN ANY EVENT (II) FOR ANY AMOUNT IN EXCESS, IN
// THE AGGREGATE, OF THE FEE PAID BY LICENSEE TO EFINIX HEREUNDER
// (OR, IF THE FEE HAS BEEN WAIVED, $100), EVEN IF EFINIX SHALL HAVE
// BEEN INFORMED OF THE POSSIBILITY OF SUCH DAMAGES. SOME STATES DO
// NOT ALLOW THE EXCLUSION OR LIMITATION OF INCIDENTAL OR
// CONSEQUENTIAL DAMAGES, SO THIS LIMITATION AND EXCLUSION MAY NOT
// APPLY TO LICENSEE.
//
////////////////////////////////////////////////////////////////////////////////
gDMA u_gDMA
(
.clk ( clk ),
.ctrl_reset ( ctrl_reset ),
.reset ( reset ),
.ctrl_clk ( ctrl_clk ),
.ctrl_PADDR ( ctrl_PADDR ),
.ctrl_PREADY ( ctrl_PREADY ),
.ctrl_PENABLE ( ctrl_PENABLE ),
.ctrl_PSEL ( ctrl_PSEL ),
.ctrl_PWRITE ( ctrl_PWRITE ),
.ctrl_PWDATA ( ctrl_PWDATA ),
.ctrl_PRDATA ( ctrl_PRDATA ),
.ctrl_PSLVERROR ( ctrl_PSLVERROR ),
.ctrl_interrupts ( ctrl_interrupts ),
.read_arvalid ( read_arvalid ),
.read_araddr ( read_araddr ),
.read_arready ( read_arready ),
.read_arregion ( read_arregion ),
.read_arlen ( read_arlen ),
.read_arsize ( read_arsize ),
.read_arburst ( read_arburst ),
.read_arlock ( read_arlock ),
.read_arcache ( read_arcache ),
.read_arqos ( read_arqos ),
.read_arprot ( read_arprot ),
.read_rready ( read_rready ),
.read_rvalid ( read_rvalid ),
.read_rdata ( read_rdata ),
.read_rlast ( read_rlast ),
.write_awvalid ( write_awvalid ),
.write_awready ( write_awready ),
.write_awaddr ( write_awaddr ),
.write_awregion ( write_awregion ),
.write_awlen ( write_awlen ),
.write_awsize ( write_awsize ),
.write_awburst ( write_awburst ),
.write_awlock ( write_awlock ),
.write_awcache ( write_awcache ),
.write_awqos ( write_awqos ),
.write_awprot ( write_awprot ),
.write_wvalid ( write_wvalid ),
.write_wready ( write_wready ),
.write_wdata ( write_wdata ),
.write_wstrb ( write_wstrb ),
.write_wlast ( write_wlast ),
.write_bvalid ( write_bvalid ),
.write_bready ( write_bready ),
.write_bresp ( write_bresp ),
.dat1_o_tvalid ( dat1_o_tvalid ),
.dat1_o_tready ( dat1_o_tready ),
.dat1_o_tdata ( dat1_o_tdata ),
.dat1_o_tkeep ( dat1_o_tkeep ),
.dat1_o_tdest ( dat1_o_tdest ),
.dat1_o_tlast ( dat1_o_tlast ),
.io_0_descriptorUpdate ( io_0_descriptorUpdate ),
.dat1_o_clk ( dat1_o_clk ),
.dat1_o_reset ( dat1_o_reset ),
.dat0_i_clk ( dat0_i_clk ),
.dat0_i_reset ( dat0_i_reset ),
.dat0_i_tvalid ( dat0_i_tvalid ),
.dat0_i_tready ( dat0_i_tready ),
.dat0_i_tdata ( dat0_i_tdata ),
.dat0_i_tkeep ( dat0_i_tkeep ),
.dat0_i_tdest ( dat0_i_tdest ),
.dat0_i_tlast ( dat0_i_tlast ),
.read_rresp ( read_rresp ),
.io_1_descriptorUpdate ( io_1_descriptorUpdate )
);

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--------------------------------------------------------------------------------
-- Copyright (C) 2013-2025 Efinix Inc. All rights reserved.
--
-- This document contains proprietary information which is
-- protected by copyright. All rights are reserved. This notice
-- refers to original work by Efinix, Inc. which may be derivitive
-- of other work distributed under license of the authors. In the
-- case of derivative work, nothing in this notice overrides the
-- original author's license agreement. Where applicable, the
-- original license agreement is included in it's original
-- unmodified form immediately below this header.
--
-- WARRANTY DISCLAIMER.
-- THE DESIGN, CODE, OR INFORMATION ARE PROVIDED “AS IS” AND
-- EFINIX MAKES NO WARRANTIES, EXPRESS OR IMPLIED WITH
-- RESPECT THERETO, AND EXPRESSLY DISCLAIMS ANY IMPLIED WARRANTIES,
-- INCLUDING, WITHOUT LIMITATION, THE IMPLIED WARRANTIES OF
-- MERCHANTABILITY, NON-INFRINGEMENT AND FITNESS FOR A PARTICULAR
-- PURPOSE. SOME STATES DO NOT ALLOW EXCLUSIONS OF AN IMPLIED
-- WARRANTY, SO THIS DISCLAIMER MAY NOT APPLY TO LICENSEE.
--
-- LIMITATION OF LIABILITY.
-- NOTWITHSTANDING ANYTHING TO THE CONTRARY, EXCEPT FOR BODILY
-- INJURY, EFINIX SHALL NOT BE LIABLE WITH RESPECT TO ANY SUBJECT
-- MATTER OF THIS AGREEMENT UNDER TORT, CONTRACT, STRICT LIABILITY
-- OR ANY OTHER LEGAL OR EQUITABLE THEORY (I) FOR ANY INDIRECT,
-- SPECIAL, INCIDENTAL, EXEMPLARY OR CONSEQUENTIAL DAMAGES OF ANY
-- CHARACTER INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF
-- GOODWILL, DATA OR PROFIT, WORK STOPPAGE, OR COMPUTER FAILURE OR
-- MALFUNCTION, OR IN ANY EVENT (II) FOR ANY AMOUNT IN EXCESS, IN
-- THE AGGREGATE, OF THE FEE PAID BY LICENSEE TO EFINIX HEREUNDER
-- (OR, IF THE FEE HAS BEEN WAIVED, $100), EVEN IF EFINIX SHALL HAVE
-- BEEN INFORMED OF THE POSSIBILITY OF SUCH DAMAGES. SOME STATES DO
-- NOT ALLOW THE EXCLUSION OR LIMITATION OF INCIDENTAL OR
-- CONSEQUENTIAL DAMAGES, SO THIS LIMITATION AND EXCLUSION MAY NOT
-- APPLY TO LICENSEE.
--
--------------------------------------------------------------------------------
------------- Begin Cut here for COMPONENT Declaration ------
component gDMA is
port (
clk : in std_logic;
ctrl_reset : in std_logic;
reset : in std_logic;
ctrl_clk : in std_logic;
ctrl_PADDR : in std_logic_vector(13 downto 0);
ctrl_PREADY : out std_logic;
ctrl_PENABLE : in std_logic;
ctrl_PSEL : in std_logic;
ctrl_PWRITE : in std_logic;
ctrl_PWDATA : in std_logic_vector(31 downto 0);
ctrl_PRDATA : out std_logic_vector(31 downto 0);
ctrl_PSLVERROR : out std_logic;
ctrl_interrupts : out std_logic_vector(1 downto 0);
read_arvalid : out std_logic;
read_araddr : out std_logic_vector(31 downto 0);
read_arready : in std_logic;
read_arregion : out std_logic_vector(3 downto 0);
read_arlen : out std_logic_vector(7 downto 0);
read_arsize : out std_logic_vector(2 downto 0);
read_arburst : out std_logic_vector(1 downto 0);
read_arlock : out std_logic;
read_arcache : out std_logic_vector(3 downto 0);
read_arqos : out std_logic_vector(3 downto 0);
read_arprot : out std_logic_vector(2 downto 0);
read_rready : out std_logic;
read_rvalid : in std_logic;
read_rdata : in std_logic_vector(127 downto 0);
read_rlast : in std_logic;
write_awvalid : out std_logic;
write_awready : in std_logic;
write_awaddr : out std_logic_vector(31 downto 0);
write_awregion : out std_logic_vector(3 downto 0);
write_awlen : out std_logic_vector(7 downto 0);
write_awsize : out std_logic_vector(2 downto 0);
write_awburst : out std_logic_vector(1 downto 0);
write_awlock : out std_logic;
write_awcache : out std_logic_vector(3 downto 0);
write_awqos : out std_logic_vector(3 downto 0);
write_awprot : out std_logic_vector(2 downto 0);
write_wvalid : out std_logic;
write_wready : in std_logic;
write_wdata : out std_logic_vector(127 downto 0);
write_wstrb : out std_logic_vector(15 downto 0);
write_wlast : out std_logic;
write_bvalid : in std_logic;
write_bready : out std_logic;
write_bresp : in std_logic_vector(1 downto 0);
dat1_o_tvalid : out std_logic;
dat1_o_tready : in std_logic;
dat1_o_tdata : out std_logic_vector(7 downto 0);
dat1_o_tkeep : out std_logic_vector(0 to 0);
dat1_o_tdest : out std_logic_vector(3 downto 0);
dat1_o_tlast : out std_logic;
io_0_descriptorUpdate : out std_logic;
dat1_o_clk : in std_logic;
dat1_o_reset : in std_logic;
dat0_i_clk : in std_logic;
dat0_i_reset : in std_logic;
dat0_i_tvalid : in std_logic;
dat0_i_tready : out std_logic;
dat0_i_tdata : in std_logic_vector(7 downto 0);
dat0_i_tkeep : in std_logic_vector(0 to 0);
dat0_i_tdest : in std_logic_vector(3 downto 0);
dat0_i_tlast : in std_logic;
read_rresp : in std_logic_vector(1 downto 0);
io_1_descriptorUpdate : out std_logic
);
end component gDMA;
---------------------- End COMPONENT Declaration ------------
------------- Begin Cut here for INSTANTIATION Template -----
u_gDMA : gDMA
port map (
clk => clk,
ctrl_reset => ctrl_reset,
reset => reset,
ctrl_clk => ctrl_clk,
ctrl_PADDR => ctrl_PADDR,
ctrl_PREADY => ctrl_PREADY,
ctrl_PENABLE => ctrl_PENABLE,
ctrl_PSEL => ctrl_PSEL,
ctrl_PWRITE => ctrl_PWRITE,
ctrl_PWDATA => ctrl_PWDATA,
ctrl_PRDATA => ctrl_PRDATA,
ctrl_PSLVERROR => ctrl_PSLVERROR,
ctrl_interrupts => ctrl_interrupts,
read_arvalid => read_arvalid,
read_araddr => read_araddr,
read_arready => read_arready,
read_arregion => read_arregion,
read_arlen => read_arlen,
read_arsize => read_arsize,
read_arburst => read_arburst,
read_arlock => read_arlock,
read_arcache => read_arcache,
read_arqos => read_arqos,
read_arprot => read_arprot,
read_rready => read_rready,
read_rvalid => read_rvalid,
read_rdata => read_rdata,
read_rlast => read_rlast,
write_awvalid => write_awvalid,
write_awready => write_awready,
write_awaddr => write_awaddr,
write_awregion => write_awregion,
write_awlen => write_awlen,
write_awsize => write_awsize,
write_awburst => write_awburst,
write_awlock => write_awlock,
write_awcache => write_awcache,
write_awqos => write_awqos,
write_awprot => write_awprot,
write_wvalid => write_wvalid,
write_wready => write_wready,
write_wdata => write_wdata,
write_wstrb => write_wstrb,
write_wlast => write_wlast,
write_bvalid => write_bvalid,
write_bready => write_bready,
write_bresp => write_bresp,
dat1_o_tvalid => dat1_o_tvalid,
dat1_o_tready => dat1_o_tready,
dat1_o_tdata => dat1_o_tdata,
dat1_o_tkeep => dat1_o_tkeep,
dat1_o_tdest => dat1_o_tdest,
dat1_o_tlast => dat1_o_tlast,
io_0_descriptorUpdate => io_0_descriptorUpdate,
dat1_o_clk => dat1_o_clk,
dat1_o_reset => dat1_o_reset,
dat0_i_clk => dat0_i_clk,
dat0_i_reset => dat0_i_reset,
dat0_i_tvalid => dat0_i_tvalid,
dat0_i_tready => dat0_i_tready,
dat0_i_tdata => dat0_i_tdata,
dat0_i_tkeep => dat0_i_tkeep,
dat0_i_tdest => dat0_i_tdest,
dat0_i_tlast => dat0_i_tlast,
read_rresp => read_rresp,
io_1_descriptorUpdate => io_1_descriptorUpdate
);
------------------------ End INSTANTIATION Template ---------

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{
"args": [
"-o",
"gDMA",
"--base_path",
"/projects/SSE/llching/repo/efx_IP_master/efx_IP/efx_hard_soc/fpga/Ti375C529_devkit/ip",
"--vlnv",
{
"vendor": "efinixinc.com",
"library": "bridges_and_adaptors",
"name": "efx_dma",
"version": "6.4.2"
}
],
"conf": {
"PriorityEncode": "1'b0",
"WrQueue": "1'b0",
"CTRL_ASYNC_MODE": "1'b1",
"EfinixDDR": "1'b0",
"RdQueue": "1'b0",
"BufferWidth": "64",
"BufferWords": "512",
"MemExtWidth": "128",
"CH0_SGMode": "1'b1",
"CH0_Output": "1'b0",
"CH0_Input": "1'b1",
"CH4_Input": "1'b1",
"CH4_Width": "32",
"CH4_Output": "1'b1",
"CH4_SGMode": "1'b0",
"CH4_SR": "1'b0",
"CH5_BurstSize": "64",
"CH5_BufferSize": "1024",
"CH5_SR": "1'b0",
"CH6_Output": "1'b1",
"CH6_SGMode": "1'b0",
"CH6_SR": "1'b0",
"CH7_Output": "1'b1",
"CH7_SGMode": "1'b0",
"CH7_SR": "1'b0",
"CH7_Input": "1'b1",
"CH7_Width": "32",
"CH7_BurstSize": "64",
"CH7_BufferSize": "1024",
"CH6_Width": "32",
"CH6_Input": "1'b1",
"CH6_BurstSize": "64",
"CH6_BufferSize": "1024",
"CH5_Width": "32",
"CH5_Output": "1'b1",
"CH5_SGMode": "1'b0",
"CH5_Input": "1'b1",
"CH4_BurstSize": "64",
"CH4_BufferSize": "1024",
"CH3_SR": "1'b0",
"CH3_SGMode": "1'b0",
"CH3_Output": "1'b1",
"CH3_Width": "32",
"CH3_Input": "1'b1",
"CH3_BufferSize": "1024",
"CH3_BurstSize": "64",
"BufferCount": "2",
"CH0_Enable": "1'b1",
"CH1_Enable": "1'b1",
"CH1_AsyncMode": "1'b1",
"CH6_AsyncMode": "1'b0",
"CH5_AsyncMode": "1'b0",
"CH7_AsyncMode": "1'b0",
"CH0_AsyncMode": "1'b1",
"CH3_AsyncMode": "1'b0",
"CH2_AsyncMode": "1'b0",
"CH4_AsyncMode": "1'b0",
"CH0_BufferSize": "4096",
"CH0_BurstSize": "1024",
"CH0_SR": "1'b0",
"CH0_Width": "8",
"CH1_Input": "1'b0",
"CH1_Width": "8",
"CH1_Output": "1'b1",
"CH1_SGMode": "1'b1",
"CH1_SR": "1'b0",
"CH2_BufferSize": "1024",
"CH2_BurstSize": "64",
"CH2_Width": "32",
"CH2_SR": "1'b0",
"CH2_SGMode": "1'b0",
"CH2_Output": "1'b1",
"CH2_Input": "1'b1",
"CH1_BufferSize": "4096",
"CH1_BurstSize": "1024",
"CH2_Enable_user": "1'b0",
"CH2_Enable_default": "1'b0",
"CH3_Enable_default": "1'b0",
"CH3_Enable_user": "1'b0",
"CH4_Enable_default": "1'b0",
"CH4_Enable_user": "1'b0",
"CH5_Enable_user": "1'b0",
"CH5_Enable_default": "1'b0",
"CH6_Enable_user": "1'b0",
"CH6_Enable_default": "1'b0",
"CH7_Enable_user": "1'b0",
"CH7_Enable_default": "1'b0",
"CustomSGBus": "1'b0",
"CH0_MemMode": "1'b0",
"CH1_MemMode": "1'b0",
"CH2_MemMode": "1'b0",
"CH3_MemMode": "1'b0",
"CH4_MemMode": "1'b0",
"CH5_MemMode": "1'b0",
"CH6_MemMode": "1'b0",
"CH7_MemMode": "1'b0"
},
"output": {
"external_script_generator": [],
"external_source_source": [
"gDMA/gDMA_define.vh",
"gDMA/gDMA.v",
"gDMA/gDMA_tmpl.v",
"gDMA/gDMA_tmpl.vhd"
],
"external_script_script": []
},
"ooc_synthesis": {},
"sw_version": "2025.2.272",
"generated_date": "2025-10-16T09:35:15.778966+00:00"
}

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{
"name": "EfxDMA",
"efinix_ddr": false,
"with_sg_bus": false,
"with_ddr_write_queue": false,
"with_ddr_read_queue": false,
"ctrl": {
"asynchronous": true
},
"buffer": {
"bank_count": 2,
"bank_width": 64,
"bank_words": 512
},
"read": {
"address_width": 32,
"data_width_external": 128,
"data_width_internal": 128
},
"write": {
"address_width": 32,
"data_width_external": 128,
"data_width_internal": 128
},
"channels": {
"c0": {
"progress_probe": true,
"direct_ctrl_capable": true,
"linked_list_capable": true,
"memory_to_memory": false,
"inputs": [
"dat0_i"
],
"half_completion_interrupt": false,
"self_restart_capable": false,
"bytes_per_burst": 1024,
"buffer_address": 0,
"buffer_size": 4096
},
"c1": {
"progress_probe": true,
"direct_ctrl_capable": true,
"linked_list_capable": true,
"memory_to_memory": false,
"outputs": [
"dat1_o"
],
"half_completion_interrupt": false,
"self_restart_capable": false,
"bytes_per_burst": 1024,
"buffer_address": 4096,
"buffer_size": 4096
}
},
"inputs": {
"dat0_i": {
"data_width": 8,
"tid_width": 0,
"tdest_width": 4,
"asynchronous": true
}
},
"outputs": {
"dat1_o": {
"data_width": 8,
"tid_width": 0,
"tdest_width": 4,
"asynchronous": true
}
}
}

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// =============================================================================
// Generated by efx_ipmgr
// Version: 2025.2.272
// IP Version: 6.0
// =============================================================================
////////////////////////////////////////////////////////////////////////////////
// Copyright (C) 2013-2025 Efinix Inc. All rights reserved.
//
// This document contains proprietary information which is
// protected by copyright. All rights are reserved. This notice
// refers to original work by Efinix, Inc. which may be derivitive
// of other work distributed under license of the authors. In the
// case of derivative work, nothing in this notice overrides the
// original author's license agreement. Where applicable, the
// original license agreement is included in it's original
// unmodified form immediately below this header.
//
// WARRANTY DISCLAIMER.
// THE DESIGN, CODE, OR INFORMATION ARE PROVIDED “AS IS” AND
// EFINIX MAKES NO WARRANTIES, EXPRESS OR IMPLIED WITH
// RESPECT THERETO, AND EXPRESSLY DISCLAIMS ANY IMPLIED WARRANTIES,
// INCLUDING, WITHOUT LIMITATION, THE IMPLIED WARRANTIES OF
// MERCHANTABILITY, NON-INFRINGEMENT AND FITNESS FOR A PARTICULAR
// PURPOSE. SOME STATES DO NOT ALLOW EXCLUSIONS OF AN IMPLIED
// WARRANTY, SO THIS DISCLAIMER MAY NOT APPLY TO LICENSEE.
//
// LIMITATION OF LIABILITY.
// NOTWITHSTANDING ANYTHING TO THE CONTRARY, EXCEPT FOR BODILY
// INJURY, EFINIX SHALL NOT BE LIABLE WITH RESPECT TO ANY SUBJECT
// MATTER OF THIS AGREEMENT UNDER TORT, CONTRACT, STRICT LIABILITY
// OR ANY OTHER LEGAL OR EQUITABLE THEORY (I) FOR ANY INDIRECT,
// SPECIAL, INCIDENTAL, EXEMPLARY OR CONSEQUENTIAL DAMAGES OF ANY
// CHARACTER INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF
// GOODWILL, DATA OR PROFIT, WORK STOPPAGE, OR COMPUTER FAILURE OR
// MALFUNCTION, OR IN ANY EVENT (II) FOR ANY AMOUNT IN EXCESS, IN
// THE AGGREGATE, OF THE FEE PAID BY LICENSEE TO EFINIX HEREUNDER
// (OR, IF THE FEE HAS BEEN WAIVED, $100), EVEN IF EFINIX SHALL HAVE
// BEEN INFORMED OF THE POSSIBILITY OF SUCH DAMAGES. SOME STATES DO
// NOT ALLOW THE EXCLUSION OR LIMITATION OF INCIDENTAL OR
// CONSEQUENTIAL DAMAGES, SO THIS LIMITATION AND EXCLUSION MAY NOT
// APPLY TO LICENSEE.
//
////////////////////////////////////////////////////////////////////////////////
localparam DATA_BUFFER_DEPTH = 512;
localparam ADMA_DATA_WIDTH = 128;

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// =============================================================================
// Generated by efx_ipmgr
// Version: 2025.2.272
// IP Version: 6.0
// =============================================================================
////////////////////////////////////////////////////////////////////////////////
// Copyright (C) 2013-2025 Efinix Inc. All rights reserved.
//
// This document contains proprietary information which is
// protected by copyright. All rights are reserved. This notice
// refers to original work by Efinix, Inc. which may be derivitive
// of other work distributed under license of the authors. In the
// case of derivative work, nothing in this notice overrides the
// original author's license agreement. Where applicable, the
// original license agreement is included in it's original
// unmodified form immediately below this header.
//
// WARRANTY DISCLAIMER.
// THE DESIGN, CODE, OR INFORMATION ARE PROVIDED “AS IS” AND
// EFINIX MAKES NO WARRANTIES, EXPRESS OR IMPLIED WITH
// RESPECT THERETO, AND EXPRESSLY DISCLAIMS ANY IMPLIED WARRANTIES,
// INCLUDING, WITHOUT LIMITATION, THE IMPLIED WARRANTIES OF
// MERCHANTABILITY, NON-INFRINGEMENT AND FITNESS FOR A PARTICULAR
// PURPOSE. SOME STATES DO NOT ALLOW EXCLUSIONS OF AN IMPLIED
// WARRANTY, SO THIS DISCLAIMER MAY NOT APPLY TO LICENSEE.
//
// LIMITATION OF LIABILITY.
// NOTWITHSTANDING ANYTHING TO THE CONTRARY, EXCEPT FOR BODILY
// INJURY, EFINIX SHALL NOT BE LIABLE WITH RESPECT TO ANY SUBJECT
// MATTER OF THIS AGREEMENT UNDER TORT, CONTRACT, STRICT LIABILITY
// OR ANY OTHER LEGAL OR EQUITABLE THEORY (I) FOR ANY INDIRECT,
// SPECIAL, INCIDENTAL, EXEMPLARY OR CONSEQUENTIAL DAMAGES OF ANY
// CHARACTER INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF
// GOODWILL, DATA OR PROFIT, WORK STOPPAGE, OR COMPUTER FAILURE OR
// MALFUNCTION, OR IN ANY EVENT (II) FOR ANY AMOUNT IN EXCESS, IN
// THE AGGREGATE, OF THE FEE PAID BY LICENSEE TO EFINIX HEREUNDER
// (OR, IF THE FEE HAS BEEN WAIVED, $100), EVEN IF EFINIX SHALL HAVE
// BEEN INFORMED OF THE POSSIBILITY OF SUCH DAMAGES. SOME STATES DO
// NOT ALLOW THE EXCLUSION OR LIMITATION OF INCIDENTAL OR
// CONSEQUENTIAL DAMAGES, SO THIS LIMITATION AND EXCLUSION MAY NOT
// APPLY TO LICENSEE.
//
////////////////////////////////////////////////////////////////////////////////
gSDHC u_gSDHC
(
.sd_rst ( sd_rst ),
.sd_base_clk ( sd_base_clk ),
.sd_int ( sd_int ),
.sd_cd_n ( sd_cd_n ),
.sd_wp ( sd_wp ),
.s_axi_awaddr ( s_axi_awaddr ),
.s_axi_aclk ( s_axi_aclk ),
.s_axi_awready ( s_axi_awready ),
.s_axi_awvalid ( s_axi_awvalid ),
.s_axi_wdata ( s_axi_wdata ),
.s_axi_wready ( s_axi_wready ),
.s_axi_wvalid ( s_axi_wvalid ),
.s_axi_bresp ( s_axi_bresp ),
.s_axi_bvalid ( s_axi_bvalid ),
.s_axi_araddr ( s_axi_araddr ),
.s_axi_bready ( s_axi_bready ),
.s_axi_arready ( s_axi_arready ),
.s_axi_arvalid ( s_axi_arvalid ),
.s_axi_rresp ( s_axi_rresp ),
.s_axi_rdata ( s_axi_rdata ),
.s_axi_rvalid ( s_axi_rvalid ),
.s_axi_rready ( s_axi_rready ),
.m_axi_awaddr ( m_axi_awaddr ),
.m_axi_awvalid ( m_axi_awvalid ),
.m_axi_clk ( m_axi_clk ),
.m_axi_awlen ( m_axi_awlen ),
.m_axi_awready ( m_axi_awready ),
.m_axi_awsize ( m_axi_awsize ),
.m_axi_awcache ( m_axi_awcache ),
.m_axi_awlock ( m_axi_awlock ),
.m_axi_awprot ( m_axi_awprot ),
.m_axi_wlast ( m_axi_wlast ),
.m_axi_wvalid ( m_axi_wvalid ),
.m_axi_wready ( m_axi_wready ),
.m_axi_bresp ( m_axi_bresp ),
.m_axi_bvalid ( m_axi_bvalid ),
.m_axi_bready ( m_axi_bready ),
.m_axi_arvalid ( m_axi_arvalid ),
.m_axi_araddr ( m_axi_araddr ),
.m_axi_arlen ( m_axi_arlen ),
.m_axi_arsize ( m_axi_arsize ),
.m_axi_arburst ( m_axi_arburst ),
.m_axi_arprot ( m_axi_arprot ),
.m_axi_arlock ( m_axi_arlock ),
.m_axi_arcache ( m_axi_arcache ),
.m_axi_arready ( m_axi_arready ),
.m_axi_rvalid ( m_axi_rvalid ),
.m_axi_rlast ( m_axi_rlast ),
.m_axi_rresp ( m_axi_rresp ),
.m_axi_rready ( m_axi_rready ),
.sd_clk_hi ( sd_clk_hi ),
.sd_clk_lo ( sd_clk_lo ),
.sd_cmd_i ( sd_cmd_i ),
.sd_cmd_o ( sd_cmd_o ),
.sd_cmd_oe ( sd_cmd_oe ),
.sd_dat_i ( sd_dat_i ),
.sd_dat_o ( sd_dat_o ),
.sd_dat_oe ( sd_dat_oe ),
.m_axi_awburst ( m_axi_awburst ),
.m_axi_wdata ( m_axi_wdata ),
.m_axi_wstrb ( m_axi_wstrb ),
.m_axi_rdata ( m_axi_rdata ),
.s_axi_wstrb ( s_axi_wstrb )
);

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--------------------------------------------------------------------------------
-- Copyright (C) 2013-2025 Efinix Inc. All rights reserved.
--
-- This document contains proprietary information which is
-- protected by copyright. All rights are reserved. This notice
-- refers to original work by Efinix, Inc. which may be derivitive
-- of other work distributed under license of the authors. In the
-- case of derivative work, nothing in this notice overrides the
-- original author's license agreement. Where applicable, the
-- original license agreement is included in it's original
-- unmodified form immediately below this header.
--
-- WARRANTY DISCLAIMER.
-- THE DESIGN, CODE, OR INFORMATION ARE PROVIDED “AS IS” AND
-- EFINIX MAKES NO WARRANTIES, EXPRESS OR IMPLIED WITH
-- RESPECT THERETO, AND EXPRESSLY DISCLAIMS ANY IMPLIED WARRANTIES,
-- INCLUDING, WITHOUT LIMITATION, THE IMPLIED WARRANTIES OF
-- MERCHANTABILITY, NON-INFRINGEMENT AND FITNESS FOR A PARTICULAR
-- PURPOSE. SOME STATES DO NOT ALLOW EXCLUSIONS OF AN IMPLIED
-- WARRANTY, SO THIS DISCLAIMER MAY NOT APPLY TO LICENSEE.
--
-- LIMITATION OF LIABILITY.
-- NOTWITHSTANDING ANYTHING TO THE CONTRARY, EXCEPT FOR BODILY
-- INJURY, EFINIX SHALL NOT BE LIABLE WITH RESPECT TO ANY SUBJECT
-- MATTER OF THIS AGREEMENT UNDER TORT, CONTRACT, STRICT LIABILITY
-- OR ANY OTHER LEGAL OR EQUITABLE THEORY (I) FOR ANY INDIRECT,
-- SPECIAL, INCIDENTAL, EXEMPLARY OR CONSEQUENTIAL DAMAGES OF ANY
-- CHARACTER INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF
-- GOODWILL, DATA OR PROFIT, WORK STOPPAGE, OR COMPUTER FAILURE OR
-- MALFUNCTION, OR IN ANY EVENT (II) FOR ANY AMOUNT IN EXCESS, IN
-- THE AGGREGATE, OF THE FEE PAID BY LICENSEE TO EFINIX HEREUNDER
-- (OR, IF THE FEE HAS BEEN WAIVED, $100), EVEN IF EFINIX SHALL HAVE
-- BEEN INFORMED OF THE POSSIBILITY OF SUCH DAMAGES. SOME STATES DO
-- NOT ALLOW THE EXCLUSION OR LIMITATION OF INCIDENTAL OR
-- CONSEQUENTIAL DAMAGES, SO THIS LIMITATION AND EXCLUSION MAY NOT
-- APPLY TO LICENSEE.
--
--------------------------------------------------------------------------------
------------- Begin Cut here for COMPONENT Declaration ------
component gSDHC is
port (
sd_rst : in std_logic;
sd_base_clk : in std_logic;
sd_int : out std_logic;
sd_cd_n : in std_logic;
sd_wp : in std_logic;
s_axi_awaddr : in std_logic_vector(9 downto 0);
s_axi_aclk : in std_logic;
s_axi_awready : out std_logic;
s_axi_awvalid : in std_logic;
s_axi_wdata : in std_logic_vector(31 downto 0);
s_axi_wready : out std_logic;
s_axi_wvalid : in std_logic;
s_axi_bresp : out std_logic_vector(1 downto 0);
s_axi_bvalid : out std_logic;
s_axi_araddr : in std_logic_vector(9 downto 0);
s_axi_bready : in std_logic;
s_axi_arready : out std_logic;
s_axi_arvalid : in std_logic;
s_axi_rresp : out std_logic_vector(1 downto 0);
s_axi_rdata : out std_logic_vector(31 downto 0);
s_axi_rvalid : out std_logic;
s_axi_rready : in std_logic;
m_axi_awaddr : out std_logic_vector(31 downto 0);
m_axi_awvalid : out std_logic;
m_axi_clk : in std_logic;
m_axi_awlen : out std_logic_vector(7 downto 0);
m_axi_awready : in std_logic;
m_axi_awsize : out std_logic_vector(2 downto 0);
m_axi_awcache : out std_logic_vector(3 downto 0);
m_axi_awlock : out std_logic_vector(1 downto 0);
m_axi_awprot : out std_logic_vector(2 downto 0);
m_axi_wlast : out std_logic;
m_axi_wvalid : out std_logic;
m_axi_wready : in std_logic;
m_axi_bresp : in std_logic_vector(1 downto 0);
m_axi_bvalid : in std_logic;
m_axi_bready : out std_logic;
m_axi_arvalid : out std_logic;
m_axi_araddr : out std_logic_vector(31 downto 0);
m_axi_arlen : out std_logic_vector(7 downto 0);
m_axi_arsize : out std_logic_vector(2 downto 0);
m_axi_arburst : out std_logic_vector(1 downto 0);
m_axi_arprot : out std_logic_vector(2 downto 0);
m_axi_arlock : out std_logic_vector(1 downto 0);
m_axi_arcache : out std_logic_vector(3 downto 0);
m_axi_arready : in std_logic;
m_axi_rvalid : in std_logic;
m_axi_rlast : in std_logic;
m_axi_rresp : in std_logic_vector(1 downto 0);
m_axi_rready : out std_logic;
sd_clk_hi : out std_logic;
sd_clk_lo : out std_logic;
sd_cmd_i : in std_logic;
sd_cmd_o : out std_logic;
sd_cmd_oe : out std_logic;
sd_dat_i : in std_logic_vector(3 downto 0);
sd_dat_o : out std_logic_vector(3 downto 0);
sd_dat_oe : out std_logic;
m_axi_awburst : out std_logic_vector(1 downto 0);
m_axi_wdata : out std_logic_vector(127 downto 0);
m_axi_wstrb : out std_logic_vector(15 downto 0);
m_axi_rdata : in std_logic_vector(127 downto 0);
s_axi_wstrb : in std_logic_vector(3 downto 0)
);
end component gSDHC;
---------------------- End COMPONENT Declaration ------------
------------- Begin Cut here for INSTANTIATION Template -----
u_gSDHC : gSDHC
port map (
sd_rst => sd_rst,
sd_base_clk => sd_base_clk,
sd_int => sd_int,
sd_cd_n => sd_cd_n,
sd_wp => sd_wp,
s_axi_awaddr => s_axi_awaddr,
s_axi_aclk => s_axi_aclk,
s_axi_awready => s_axi_awready,
s_axi_awvalid => s_axi_awvalid,
s_axi_wdata => s_axi_wdata,
s_axi_wready => s_axi_wready,
s_axi_wvalid => s_axi_wvalid,
s_axi_bresp => s_axi_bresp,
s_axi_bvalid => s_axi_bvalid,
s_axi_araddr => s_axi_araddr,
s_axi_bready => s_axi_bready,
s_axi_arready => s_axi_arready,
s_axi_arvalid => s_axi_arvalid,
s_axi_rresp => s_axi_rresp,
s_axi_rdata => s_axi_rdata,
s_axi_rvalid => s_axi_rvalid,
s_axi_rready => s_axi_rready,
m_axi_awaddr => m_axi_awaddr,
m_axi_awvalid => m_axi_awvalid,
m_axi_clk => m_axi_clk,
m_axi_awlen => m_axi_awlen,
m_axi_awready => m_axi_awready,
m_axi_awsize => m_axi_awsize,
m_axi_awcache => m_axi_awcache,
m_axi_awlock => m_axi_awlock,
m_axi_awprot => m_axi_awprot,
m_axi_wlast => m_axi_wlast,
m_axi_wvalid => m_axi_wvalid,
m_axi_wready => m_axi_wready,
m_axi_bresp => m_axi_bresp,
m_axi_bvalid => m_axi_bvalid,
m_axi_bready => m_axi_bready,
m_axi_arvalid => m_axi_arvalid,
m_axi_araddr => m_axi_araddr,
m_axi_arlen => m_axi_arlen,
m_axi_arsize => m_axi_arsize,
m_axi_arburst => m_axi_arburst,
m_axi_arprot => m_axi_arprot,
m_axi_arlock => m_axi_arlock,
m_axi_arcache => m_axi_arcache,
m_axi_arready => m_axi_arready,
m_axi_rvalid => m_axi_rvalid,
m_axi_rlast => m_axi_rlast,
m_axi_rresp => m_axi_rresp,
m_axi_rready => m_axi_rready,
sd_clk_hi => sd_clk_hi,
sd_clk_lo => sd_clk_lo,
sd_cmd_i => sd_cmd_i,
sd_cmd_o => sd_cmd_o,
sd_cmd_oe => sd_cmd_oe,
sd_dat_i => sd_dat_i,
sd_dat_o => sd_dat_o,
sd_dat_oe => sd_dat_oe,
m_axi_awburst => m_axi_awburst,
m_axi_wdata => m_axi_wdata,
m_axi_wstrb => m_axi_wstrb,
m_axi_rdata => m_axi_rdata,
s_axi_wstrb => s_axi_wstrb
);
------------------------ End INSTANTIATION Template ---------

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{
"args": [
"-o",
"gSDHC",
"--base_path",
"/projects/SSE/llching/repo/efx_IP_master/efx_IP/efx_hard_soc/fpga/Ti375C529_devkit/ip",
"--vlnv",
{
"vendor": "efinixinc.com",
"library": "memory_controller",
"name": "efx_sd_host_controller",
"version": "6.0"
}
],
"conf": {
"DATA_BUFFER_DEPTH": "512",
"ADMA_DATA_WIDTH": "128"
},
"output": {
"external_script_reference_design": [],
"external_source_source": [
"gSDHC/gSDHC_define.vh",
"gSDHC/gSDHC.v",
"gSDHC/gSDHC_tmpl.v",
"gSDHC/gSDHC_tmpl.vhd"
]
},
"ooc_synthesis": {},
"sw_version": "2025.2.272",
"generated_date": "2025-10-16T09:29:16.536987+00:00"
}

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Ti375C529_devkit/ip/gTSE/gTSE.sv Normal file
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// =============================================================================
// Generated by efx_ipmgr
// Version: 2026.1.132
// IP Version: 7.3
// =============================================================================
////////////////////////////////////////////////////////////////////////////////
// Copyright (C) 2013-2026 Efinix Inc. All rights reserved.
//
// This document contains proprietary information which is
// protected by copyright. All rights are reserved. This notice
// refers to original work by Efinix, Inc. which may be derivitive
// of other work distributed under license of the authors. In the
// case of derivative work, nothing in this notice overrides the
// original author's license agreement. Where applicable, the
// original license agreement is included in it's original
// unmodified form immediately below this header.
//
// WARRANTY DISCLAIMER.
// THE DESIGN, CODE, OR INFORMATION ARE PROVIDED “AS IS” AND
// EFINIX MAKES NO WARRANTIES, EXPRESS OR IMPLIED WITH
// RESPECT THERETO, AND EXPRESSLY DISCLAIMS ANY IMPLIED WARRANTIES,
// INCLUDING, WITHOUT LIMITATION, THE IMPLIED WARRANTIES OF
// MERCHANTABILITY, NON-INFRINGEMENT AND FITNESS FOR A PARTICULAR
// PURPOSE. SOME STATES DO NOT ALLOW EXCLUSIONS OF AN IMPLIED
// WARRANTY, SO THIS DISCLAIMER MAY NOT APPLY TO LICENSEE.
//
// LIMITATION OF LIABILITY.
// NOTWITHSTANDING ANYTHING TO THE CONTRARY, EXCEPT FOR BODILY
// INJURY, EFINIX SHALL NOT BE LIABLE WITH RESPECT TO ANY SUBJECT
// MATTER OF THIS AGREEMENT UNDER TORT, CONTRACT, STRICT LIABILITY
// OR ANY OTHER LEGAL OR EQUITABLE THEORY (I) FOR ANY INDIRECT,
// SPECIAL, INCIDENTAL, EXEMPLARY OR CONSEQUENTIAL DAMAGES OF ANY
// CHARACTER INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF
// GOODWILL, DATA OR PROFIT, WORK STOPPAGE, OR COMPUTER FAILURE OR
// MALFUNCTION, OR IN ANY EVENT (II) FOR ANY AMOUNT IN EXCESS, IN
// THE AGGREGATE, OF THE FEE PAID BY LICENSEE TO EFINIX HEREUNDER
// (OR, IF THE FEE HAS BEEN WAIVED, $100), EVEN IF EFINIX SHALL HAVE
// BEEN INFORMED OF THE POSSIBILITY OF SUCH DAMAGES. SOME STATES DO
// NOT ALLOW THE EXCLUSION OR LIMITATION OF INCIDENTAL OR
// CONSEQUENTIAL DAMAGES, SO THIS LIMITATION AND EXCLUSION MAY NOT
// APPLY TO LICENSEE.
//
////////////////////////////////////////////////////////////////////////////////
localparam VERSION = 16;
localparam TXFIFO_EN = 1'b1;
localparam RXFIFO_EN = 1'b1;
localparam TXFIFO_DTH = 4096;
localparam RXFIFO_DTH = 4096;
localparam PHY_INTF_MODE = 0;
localparam AXIS_DW = 8;
localparam RGMII_RXC_EDGE = 1'b1;
localparam RGMII_TXC_DLY = 1'b1;
localparam INTER_PACKET_GAP = 6'd12;
localparam MTU_FRAME_LENGTH = 16'd1518;
localparam MAC_SOURCE_ADDRESS = 48'd0;
localparam ENABLE_BROADCAST_FILTERING = 1'b1;
localparam LOOPBACK_EN = 1'b1;
localparam APBIF = 1'b0;
localparam FAMILY = "TITANIUM";

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// =============================================================================
// Generated by efx_ipmgr
// Version: 2026.1.132
// IP Version: 7.3
// =============================================================================
////////////////////////////////////////////////////////////////////////////////
// Copyright (C) 2013-2026 Efinix Inc. All rights reserved.
//
// This document contains proprietary information which is
// protected by copyright. All rights are reserved. This notice
// refers to original work by Efinix, Inc. which may be derivitive
// of other work distributed under license of the authors. In the
// case of derivative work, nothing in this notice overrides the
// original author's license agreement. Where applicable, the
// original license agreement is included in it's original
// unmodified form immediately below this header.
//
// WARRANTY DISCLAIMER.
// THE DESIGN, CODE, OR INFORMATION ARE PROVIDED “AS IS” AND
// EFINIX MAKES NO WARRANTIES, EXPRESS OR IMPLIED WITH
// RESPECT THERETO, AND EXPRESSLY DISCLAIMS ANY IMPLIED WARRANTIES,
// INCLUDING, WITHOUT LIMITATION, THE IMPLIED WARRANTIES OF
// MERCHANTABILITY, NON-INFRINGEMENT AND FITNESS FOR A PARTICULAR
// PURPOSE. SOME STATES DO NOT ALLOW EXCLUSIONS OF AN IMPLIED
// WARRANTY, SO THIS DISCLAIMER MAY NOT APPLY TO LICENSEE.
//
// LIMITATION OF LIABILITY.
// NOTWITHSTANDING ANYTHING TO THE CONTRARY, EXCEPT FOR BODILY
// INJURY, EFINIX SHALL NOT BE LIABLE WITH RESPECT TO ANY SUBJECT
// MATTER OF THIS AGREEMENT UNDER TORT, CONTRACT, STRICT LIABILITY
// OR ANY OTHER LEGAL OR EQUITABLE THEORY (I) FOR ANY INDIRECT,
// SPECIAL, INCIDENTAL, EXEMPLARY OR CONSEQUENTIAL DAMAGES OF ANY
// CHARACTER INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF
// GOODWILL, DATA OR PROFIT, WORK STOPPAGE, OR COMPUTER FAILURE OR
// MALFUNCTION, OR IN ANY EVENT (II) FOR ANY AMOUNT IN EXCESS, IN
// THE AGGREGATE, OF THE FEE PAID BY LICENSEE TO EFINIX HEREUNDER
// (OR, IF THE FEE HAS BEEN WAIVED, $100), EVEN IF EFINIX SHALL HAVE
// BEEN INFORMED OF THE POSSIBILITY OF SUCH DAMAGES. SOME STATES DO
// NOT ALLOW THE EXCLUSION OR LIMITATION OF INCIDENTAL OR
// CONSEQUENTIAL DAMAGES, SO THIS LIMITATION AND EXCLUSION MAY NOT
// APPLY TO LICENSEE.
//
////////////////////////////////////////////////////////////////////////////////
gTSE u_gTSE
(
.mac_reset ( mac_reset ),
.proto_reset ( proto_reset ),
.rx_mac_aclk ( rx_mac_aclk ),
.tx_mac_aclk ( tx_mac_aclk ),
.eth_speed ( eth_speed ),
.rx_axis_clk ( rx_axis_clk ),
.rx_axis_mac_tuser ( rx_axis_mac_tuser ),
.rx_axis_mac_tlast ( rx_axis_mac_tlast ),
.rx_axis_mac_tvalid ( rx_axis_mac_tvalid ),
.rx_axis_mac_tready ( rx_axis_mac_tready ),
.tx_axis_clk ( tx_axis_clk ),
.tx_axis_mac_tvalid ( tx_axis_mac_tvalid ),
.tx_axis_mac_tlast ( tx_axis_mac_tlast ),
.tx_axis_mac_tuser ( tx_axis_mac_tuser ),
.tx_axis_mac_tready ( tx_axis_mac_tready ),
.rgmii_txd_HI ( rgmii_txd_HI ),
.rgmii_txd_LO ( rgmii_txd_LO ),
.rgmii_tx_ctl_HI ( rgmii_tx_ctl_HI ),
.rgmii_tx_ctl_LO ( rgmii_tx_ctl_LO ),
.rgmii_txc_HI ( rgmii_txc_HI ),
.rgmii_txc_LO ( rgmii_txc_LO ),
.rgmii_rxd_HI ( rgmii_rxd_HI ),
.rgmii_rxd_LO ( rgmii_rxd_LO ),
.rgmii_rx_ctl_HI ( rgmii_rx_ctl_HI ),
.rgmii_rx_ctl_LO ( rgmii_rx_ctl_LO ),
.rgmii_rxc ( rgmii_rxc ),
.s_axi_aclk ( s_axi_aclk ),
.rx_axis_mac_tdata ( rx_axis_mac_tdata ),
.tx_axis_mac_tdata ( tx_axis_mac_tdata ),
.tx_axis_mac_tstrb ( tx_axis_mac_tstrb ),
.rx_axis_mac_tstrb ( rx_axis_mac_tstrb ),
.MdoEn ( MdoEn ),
.Mdo ( Mdo ),
.Mdi ( Mdi ),
.Mdc ( Mdc ),
.s_axi_araddr ( s_axi_araddr ),
.s_axi_arready ( s_axi_arready ),
.s_axi_arvalid ( s_axi_arvalid ),
.s_axi_awaddr ( s_axi_awaddr ),
.s_axi_awready ( s_axi_awready ),
.s_axi_awvalid ( s_axi_awvalid ),
.s_axi_bready ( s_axi_bready ),
.s_axi_bresp ( s_axi_bresp ),
.s_axi_bvalid ( s_axi_bvalid ),
.s_axi_rdata ( s_axi_rdata ),
.s_axi_rready ( s_axi_rready ),
.s_axi_rresp ( s_axi_rresp ),
.s_axi_rvalid ( s_axi_rvalid ),
.s_axi_wdata ( s_axi_wdata ),
.s_axi_wready ( s_axi_wready ),
.s_axi_wvalid ( s_axi_wvalid )
);

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--------------------------------------------------------------------------------
-- Copyright (C) 2013-2026 Efinix Inc. All rights reserved.
--
-- This document contains proprietary information which is
-- protected by copyright. All rights are reserved. This notice
-- refers to original work by Efinix, Inc. which may be derivitive
-- of other work distributed under license of the authors. In the
-- case of derivative work, nothing in this notice overrides the
-- original author's license agreement. Where applicable, the
-- original license agreement is included in it's original
-- unmodified form immediately below this header.
--
-- WARRANTY DISCLAIMER.
-- THE DESIGN, CODE, OR INFORMATION ARE PROVIDED “AS IS” AND
-- EFINIX MAKES NO WARRANTIES, EXPRESS OR IMPLIED WITH
-- RESPECT THERETO, AND EXPRESSLY DISCLAIMS ANY IMPLIED WARRANTIES,
-- INCLUDING, WITHOUT LIMITATION, THE IMPLIED WARRANTIES OF
-- MERCHANTABILITY, NON-INFRINGEMENT AND FITNESS FOR A PARTICULAR
-- PURPOSE. SOME STATES DO NOT ALLOW EXCLUSIONS OF AN IMPLIED
-- WARRANTY, SO THIS DISCLAIMER MAY NOT APPLY TO LICENSEE.
--
-- LIMITATION OF LIABILITY.
-- NOTWITHSTANDING ANYTHING TO THE CONTRARY, EXCEPT FOR BODILY
-- INJURY, EFINIX SHALL NOT BE LIABLE WITH RESPECT TO ANY SUBJECT
-- MATTER OF THIS AGREEMENT UNDER TORT, CONTRACT, STRICT LIABILITY
-- OR ANY OTHER LEGAL OR EQUITABLE THEORY (I) FOR ANY INDIRECT,
-- SPECIAL, INCIDENTAL, EXEMPLARY OR CONSEQUENTIAL DAMAGES OF ANY
-- CHARACTER INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF
-- GOODWILL, DATA OR PROFIT, WORK STOPPAGE, OR COMPUTER FAILURE OR
-- MALFUNCTION, OR IN ANY EVENT (II) FOR ANY AMOUNT IN EXCESS, IN
-- THE AGGREGATE, OF THE FEE PAID BY LICENSEE TO EFINIX HEREUNDER
-- (OR, IF THE FEE HAS BEEN WAIVED, $100), EVEN IF EFINIX SHALL HAVE
-- BEEN INFORMED OF THE POSSIBILITY OF SUCH DAMAGES. SOME STATES DO
-- NOT ALLOW THE EXCLUSION OR LIMITATION OF INCIDENTAL OR
-- CONSEQUENTIAL DAMAGES, SO THIS LIMITATION AND EXCLUSION MAY NOT
-- APPLY TO LICENSEE.
--
--------------------------------------------------------------------------------
------------- Begin Cut here for COMPONENT Declaration ------
component gTSE is
port (
mac_reset : in std_logic;
proto_reset : in std_logic;
rx_mac_aclk : out std_logic;
tx_mac_aclk : in std_logic;
eth_speed : out std_logic_vector(2 downto 0);
rx_axis_clk : in std_logic;
rx_axis_mac_tuser : out std_logic;
rx_axis_mac_tlast : out std_logic;
rx_axis_mac_tvalid : out std_logic;
rx_axis_mac_tready : in std_logic;
tx_axis_clk : in std_logic;
tx_axis_mac_tvalid : in std_logic;
tx_axis_mac_tlast : in std_logic;
tx_axis_mac_tuser : in std_logic;
tx_axis_mac_tready : out std_logic;
rgmii_txd_HI : out std_logic_vector(3 downto 0);
rgmii_txd_LO : out std_logic_vector(3 downto 0);
rgmii_tx_ctl_HI : out std_logic;
rgmii_tx_ctl_LO : out std_logic;
rgmii_txc_HI : out std_logic;
rgmii_txc_LO : out std_logic;
rgmii_rxd_HI : in std_logic_vector(3 downto 0);
rgmii_rxd_LO : in std_logic_vector(3 downto 0);
rgmii_rx_ctl_HI : in std_logic;
rgmii_rx_ctl_LO : in std_logic;
rgmii_rxc : in std_logic;
s_axi_aclk : in std_logic;
rx_axis_mac_tdata : out std_logic_vector(7 downto 0);
tx_axis_mac_tdata : in std_logic_vector(7 downto 0);
tx_axis_mac_tstrb : in std_logic_vector(0 to 0);
rx_axis_mac_tstrb : out std_logic_vector(0 to 0);
MdoEn : out std_logic;
Mdo : out std_logic;
Mdi : in std_logic;
Mdc : out std_logic;
s_axi_araddr : in std_logic_vector(9 downto 0);
s_axi_arready : out std_logic;
s_axi_arvalid : in std_logic;
s_axi_awaddr : in std_logic_vector(9 downto 0);
s_axi_awready : out std_logic;
s_axi_awvalid : in std_logic;
s_axi_bready : in std_logic;
s_axi_bresp : out std_logic_vector(1 downto 0);
s_axi_bvalid : out std_logic;
s_axi_rdata : out std_logic_vector(31 downto 0);
s_axi_rready : in std_logic;
s_axi_rresp : out std_logic_vector(1 downto 0);
s_axi_rvalid : out std_logic;
s_axi_wdata : in std_logic_vector(31 downto 0);
s_axi_wready : out std_logic;
s_axi_wvalid : in std_logic
);
end component gTSE;
---------------------- End COMPONENT Declaration ------------
------------- Begin Cut here for INSTANTIATION Template -----
u_gTSE : gTSE
port map (
mac_reset => mac_reset,
proto_reset => proto_reset,
rx_mac_aclk => rx_mac_aclk,
tx_mac_aclk => tx_mac_aclk,
eth_speed => eth_speed,
rx_axis_clk => rx_axis_clk,
rx_axis_mac_tuser => rx_axis_mac_tuser,
rx_axis_mac_tlast => rx_axis_mac_tlast,
rx_axis_mac_tvalid => rx_axis_mac_tvalid,
rx_axis_mac_tready => rx_axis_mac_tready,
tx_axis_clk => tx_axis_clk,
tx_axis_mac_tvalid => tx_axis_mac_tvalid,
tx_axis_mac_tlast => tx_axis_mac_tlast,
tx_axis_mac_tuser => tx_axis_mac_tuser,
tx_axis_mac_tready => tx_axis_mac_tready,
rgmii_txd_HI => rgmii_txd_HI,
rgmii_txd_LO => rgmii_txd_LO,
rgmii_tx_ctl_HI => rgmii_tx_ctl_HI,
rgmii_tx_ctl_LO => rgmii_tx_ctl_LO,
rgmii_txc_HI => rgmii_txc_HI,
rgmii_txc_LO => rgmii_txc_LO,
rgmii_rxd_HI => rgmii_rxd_HI,
rgmii_rxd_LO => rgmii_rxd_LO,
rgmii_rx_ctl_HI => rgmii_rx_ctl_HI,
rgmii_rx_ctl_LO => rgmii_rx_ctl_LO,
rgmii_rxc => rgmii_rxc,
s_axi_aclk => s_axi_aclk,
rx_axis_mac_tdata => rx_axis_mac_tdata,
tx_axis_mac_tdata => tx_axis_mac_tdata,
tx_axis_mac_tstrb => tx_axis_mac_tstrb,
rx_axis_mac_tstrb => rx_axis_mac_tstrb,
MdoEn => MdoEn,
Mdo => Mdo,
Mdi => Mdi,
Mdc => Mdc,
s_axi_araddr => s_axi_araddr,
s_axi_arready => s_axi_arready,
s_axi_arvalid => s_axi_arvalid,
s_axi_awaddr => s_axi_awaddr,
s_axi_awready => s_axi_awready,
s_axi_awvalid => s_axi_awvalid,
s_axi_bready => s_axi_bready,
s_axi_bresp => s_axi_bresp,
s_axi_bvalid => s_axi_bvalid,
s_axi_rdata => s_axi_rdata,
s_axi_rready => s_axi_rready,
s_axi_rresp => s_axi_rresp,
s_axi_rvalid => s_axi_rvalid,
s_axi_wdata => s_axi_wdata,
s_axi_wready => s_axi_wready,
s_axi_wvalid => s_axi_wvalid
);
------------------------ End INSTANTIATION Template ---------

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{
"args": [
"-o",
"gTSE",
"--base_path",
"ip",
"--vlnv",
{
"vendor": "efinixinc.com",
"library": "ethernet",
"name": "efx_tsemac",
"version": "7.3"
}
],
"conf": {
"VERSION": "16",
"TXFIFO_EN": "1'b1",
"RXFIFO_EN": "1'b1",
"TXFIFO_DTH": "4096",
"RXFIFO_DTH": "4096",
"PHY_INTF_MODE": "0",
"AXIS_DW": "8",
"RGMII_RXC_EDGE": "1'b1",
"RGMII_TXC_DLY": "1'b1",
"INTER_PACKET_GAP": "6'd12",
"MTU_FRAME_LENGTH": "16'd1518",
"MAC_SOURCE_ADDRESS": "48'd0",
"ENABLE_BROADCAST_FILTERING": "1'b1",
"LOOPBACK_EN": "1'b1",
"APBIF": "1'b0",
"ONCHIP_PHY": "1'b0"
},
"output": {
"external_testbench_modelsim": [],
"external_source_source": [],
"external_testbench_testbench": [],
"external_testbench_ncsim": [],
"external_testbench_synopsys": [],
"external_testbench_aldec": [],
"external_example_example": [],
"external_example_2": []
},
"ooc_synthesis": {},
"sw_version": "2026.1.132",
"external_path_option": "RELATIVE_PATH"
}

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localparam M_BASE_ADDR = {32'h41000000,32'h40000000,32'h30000000,32'h20000000,32'h11100000,32'h11000000,32'h200,32'h0};
localparam M_ADDR_WIDTH = {32'd20,32'd24,32'd28,32'd28,32'd20,32'd12,32'd8,32'd9};

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// =============================================================================
// Generated by efx_ipmgr
// Version: 2026.1.132
// IP Version: 5.6
// =============================================================================
////////////////////////////////////////////////////////////////////////////////
// Copyright (C) 2013-2026 Efinix Inc. All rights reserved.
//
// This document contains proprietary information which is
// protected by copyright. All rights are reserved. This notice
// refers to original work by Efinix, Inc. which may be derivitive
// of other work distributed under license of the authors. In the
// case of derivative work, nothing in this notice overrides the
// original author's license agreement. Where applicable, the
// original license agreement is included in it's original
// unmodified form immediately below this header.
//
// WARRANTY DISCLAIMER.
// THE DESIGN, CODE, OR INFORMATION ARE PROVIDED “AS IS” AND
// EFINIX MAKES NO WARRANTIES, EXPRESS OR IMPLIED WITH
// RESPECT THERETO, AND EXPRESSLY DISCLAIMS ANY IMPLIED WARRANTIES,
// INCLUDING, WITHOUT LIMITATION, THE IMPLIED WARRANTIES OF
// MERCHANTABILITY, NON-INFRINGEMENT AND FITNESS FOR A PARTICULAR
// PURPOSE. SOME STATES DO NOT ALLOW EXCLUSIONS OF AN IMPLIED
// WARRANTY, SO THIS DISCLAIMER MAY NOT APPLY TO LICENSEE.
//
// LIMITATION OF LIABILITY.
// NOTWITHSTANDING ANYTHING TO THE CONTRARY, EXCEPT FOR BODILY
// INJURY, EFINIX SHALL NOT BE LIABLE WITH RESPECT TO ANY SUBJECT
// MATTER OF THIS AGREEMENT UNDER TORT, CONTRACT, STRICT LIABILITY
// OR ANY OTHER LEGAL OR EQUITABLE THEORY (I) FOR ANY INDIRECT,
// SPECIAL, INCIDENTAL, EXEMPLARY OR CONSEQUENTIAL DAMAGES OF ANY
// CHARACTER INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF
// GOODWILL, DATA OR PROFIT, WORK STOPPAGE, OR COMPUTER FAILURE OR
// MALFUNCTION, OR IN ANY EVENT (II) FOR ANY AMOUNT IN EXCESS, IN
// THE AGGREGATE, OF THE FEE PAID BY LICENSEE TO EFINIX HEREUNDER
// (OR, IF THE FEE HAS BEEN WAIVED, $100), EVEN IF EFINIX SHALL HAVE
// BEEN INFORMED OF THE POSSIBILITY OF SUCH DAMAGES. SOME STATES DO
// NOT ALLOW THE EXCLUSION OR LIMITATION OF INCIDENTAL OR
// CONSEQUENTIAL DAMAGES, SO THIS LIMITATION AND EXCLUSION MAY NOT
// APPLY TO LICENSEE.
//
////////////////////////////////////////////////////////////////////////////////
localparam ARB_MODE = "ROUND_ROBIN_1";
localparam S_PORTS = 1;
localparam DATA_WIDTH = 32;
localparam ADDR_WIDTH = 32;
localparam M_PORTS = 2;
localparam ID_WIDTH = 8;
localparam USER_WIDTH = 3;
localparam PROTOCOL = "AXI4_LITE";

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// =============================================================================
// Generated by efx_ipmgr
// Version: 2026.1.132
// IP Version: 5.6
// =============================================================================
////////////////////////////////////////////////////////////////////////////////
// Copyright (C) 2013-2026 Efinix Inc. All rights reserved.
//
// This document contains proprietary information which is
// protected by copyright. All rights are reserved. This notice
// refers to original work by Efinix, Inc. which may be derivitive
// of other work distributed under license of the authors. In the
// case of derivative work, nothing in this notice overrides the
// original author's license agreement. Where applicable, the
// original license agreement is included in it's original
// unmodified form immediately below this header.
//
// WARRANTY DISCLAIMER.
// THE DESIGN, CODE, OR INFORMATION ARE PROVIDED “AS IS” AND
// EFINIX MAKES NO WARRANTIES, EXPRESS OR IMPLIED WITH
// RESPECT THERETO, AND EXPRESSLY DISCLAIMS ANY IMPLIED WARRANTIES,
// INCLUDING, WITHOUT LIMITATION, THE IMPLIED WARRANTIES OF
// MERCHANTABILITY, NON-INFRINGEMENT AND FITNESS FOR A PARTICULAR
// PURPOSE. SOME STATES DO NOT ALLOW EXCLUSIONS OF AN IMPLIED
// WARRANTY, SO THIS DISCLAIMER MAY NOT APPLY TO LICENSEE.
//
// LIMITATION OF LIABILITY.
// NOTWITHSTANDING ANYTHING TO THE CONTRARY, EXCEPT FOR BODILY
// INJURY, EFINIX SHALL NOT BE LIABLE WITH RESPECT TO ANY SUBJECT
// MATTER OF THIS AGREEMENT UNDER TORT, CONTRACT, STRICT LIABILITY
// OR ANY OTHER LEGAL OR EQUITABLE THEORY (I) FOR ANY INDIRECT,
// SPECIAL, INCIDENTAL, EXEMPLARY OR CONSEQUENTIAL DAMAGES OF ANY
// CHARACTER INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF
// GOODWILL, DATA OR PROFIT, WORK STOPPAGE, OR COMPUTER FAILURE OR
// MALFUNCTION, OR IN ANY EVENT (II) FOR ANY AMOUNT IN EXCESS, IN
// THE AGGREGATE, OF THE FEE PAID BY LICENSEE TO EFINIX HEREUNDER
// (OR, IF THE FEE HAS BEEN WAIVED, $100), EVEN IF EFINIX SHALL HAVE
// BEEN INFORMED OF THE POSSIBILITY OF SUCH DAMAGES. SOME STATES DO
// NOT ALLOW THE EXCLUSION OR LIMITATION OF INCIDENTAL OR
// CONSEQUENTIAL DAMAGES, SO THIS LIMITATION AND EXCLUSION MAY NOT
// APPLY TO LICENSEE.
//
////////////////////////////////////////////////////////////////////////////////
gTSE_1to2_switch u_gTSE_1to2_switch
(
.rst_n ( rst_n ),
.clk ( clk ),
.s_axi_awvalid ( s_axi_awvalid ),
.s_axi_awaddr ( s_axi_awaddr ),
.s_axi_awlock ( s_axi_awlock ),
.s_axi_awready ( s_axi_awready ),
.s_axi_arvalid ( s_axi_arvalid ),
.s_axi_araddr ( s_axi_araddr ),
.s_axi_arlock ( s_axi_arlock ),
.s_axi_arready ( s_axi_arready ),
.s_axi_wvalid ( s_axi_wvalid ),
.s_axi_wlast ( s_axi_wlast ),
.s_axi_wid ( s_axi_wid ),
.s_axi_bready ( s_axi_bready ),
.s_axi_bresp ( s_axi_bresp ),
.s_axi_rready ( s_axi_rready ),
.s_axi_bid ( s_axi_bid ),
.s_axi_rid ( s_axi_rid ),
.s_axi_wdata ( s_axi_wdata ),
.s_axi_rdata ( s_axi_rdata ),
.s_axi_rresp ( s_axi_rresp ),
.s_axi_bvalid ( s_axi_bvalid ),
.s_axi_rvalid ( s_axi_rvalid ),
.s_axi_rlast ( s_axi_rlast ),
.s_axi_wstrb ( s_axi_wstrb ),
.m_axi_awvalid ( m_axi_awvalid ),
.m_axi_awaddr ( m_axi_awaddr ),
.m_axi_awlock ( m_axi_awlock ),
.m_axi_awready ( m_axi_awready ),
.m_axi_arvalid ( m_axi_arvalid ),
.m_axi_araddr ( m_axi_araddr ),
.m_axi_arlock ( m_axi_arlock ),
.m_axi_arready ( m_axi_arready ),
.m_axi_wvalid ( m_axi_wvalid ),
.m_axi_wlast ( m_axi_wlast ),
.m_axi_bready ( m_axi_bready ),
.m_axi_bresp ( m_axi_bresp ),
.m_axi_rready ( m_axi_rready ),
.m_axi_bid ( m_axi_bid ),
.m_axi_rid ( m_axi_rid ),
.m_axi_wdata ( m_axi_wdata ),
.m_axi_rdata ( m_axi_rdata ),
.m_axi_rresp ( m_axi_rresp ),
.m_axi_bvalid ( m_axi_bvalid ),
.m_axi_rvalid ( m_axi_rvalid ),
.m_axi_rlast ( m_axi_rlast ),
.m_axi_wstrb ( m_axi_wstrb ),
.m_axi_wready ( m_axi_wready ),
.s_axi_wready ( s_axi_wready )
);

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--------------------------------------------------------------------------------
-- Copyright (C) 2013-2026 Efinix Inc. All rights reserved.
--
-- This document contains proprietary information which is
-- protected by copyright. All rights are reserved. This notice
-- refers to original work by Efinix, Inc. which may be derivitive
-- of other work distributed under license of the authors. In the
-- case of derivative work, nothing in this notice overrides the
-- original author's license agreement. Where applicable, the
-- original license agreement is included in it's original
-- unmodified form immediately below this header.
--
-- WARRANTY DISCLAIMER.
-- THE DESIGN, CODE, OR INFORMATION ARE PROVIDED “AS IS” AND
-- EFINIX MAKES NO WARRANTIES, EXPRESS OR IMPLIED WITH
-- RESPECT THERETO, AND EXPRESSLY DISCLAIMS ANY IMPLIED WARRANTIES,
-- INCLUDING, WITHOUT LIMITATION, THE IMPLIED WARRANTIES OF
-- MERCHANTABILITY, NON-INFRINGEMENT AND FITNESS FOR A PARTICULAR
-- PURPOSE. SOME STATES DO NOT ALLOW EXCLUSIONS OF AN IMPLIED
-- WARRANTY, SO THIS DISCLAIMER MAY NOT APPLY TO LICENSEE.
--
-- LIMITATION OF LIABILITY.
-- NOTWITHSTANDING ANYTHING TO THE CONTRARY, EXCEPT FOR BODILY
-- INJURY, EFINIX SHALL NOT BE LIABLE WITH RESPECT TO ANY SUBJECT
-- MATTER OF THIS AGREEMENT UNDER TORT, CONTRACT, STRICT LIABILITY
-- OR ANY OTHER LEGAL OR EQUITABLE THEORY (I) FOR ANY INDIRECT,
-- SPECIAL, INCIDENTAL, EXEMPLARY OR CONSEQUENTIAL DAMAGES OF ANY
-- CHARACTER INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF
-- GOODWILL, DATA OR PROFIT, WORK STOPPAGE, OR COMPUTER FAILURE OR
-- MALFUNCTION, OR IN ANY EVENT (II) FOR ANY AMOUNT IN EXCESS, IN
-- THE AGGREGATE, OF THE FEE PAID BY LICENSEE TO EFINIX HEREUNDER
-- (OR, IF THE FEE HAS BEEN WAIVED, $100), EVEN IF EFINIX SHALL HAVE
-- BEEN INFORMED OF THE POSSIBILITY OF SUCH DAMAGES. SOME STATES DO
-- NOT ALLOW THE EXCLUSION OR LIMITATION OF INCIDENTAL OR
-- CONSEQUENTIAL DAMAGES, SO THIS LIMITATION AND EXCLUSION MAY NOT
-- APPLY TO LICENSEE.
--
--------------------------------------------------------------------------------
------------- Begin Cut here for COMPONENT Declaration ------
component gTSE_1to2_switch is
port (
rst_n : in std_logic;
clk : in std_logic;
s_axi_awvalid : in std_logic_vector(0 to 0);
s_axi_awaddr : in std_logic_vector(31 downto 0);
s_axi_awlock : in std_logic_vector(1 downto 0);
s_axi_awready : out std_logic_vector(0 to 0);
s_axi_arvalid : in std_logic_vector(0 to 0);
s_axi_araddr : in std_logic_vector(31 downto 0);
s_axi_arlock : in std_logic_vector(1 downto 0);
s_axi_arready : out std_logic_vector(0 to 0);
s_axi_wvalid : in std_logic_vector(0 to 0);
s_axi_wlast : in std_logic_vector(0 to 0);
s_axi_wid : in std_logic_vector(7 downto 0);
s_axi_bready : in std_logic_vector(0 to 0);
s_axi_bresp : out std_logic_vector(1 downto 0);
s_axi_rready : in std_logic_vector(0 to 0);
s_axi_bid : out std_logic_vector(7 downto 0);
s_axi_rid : out std_logic_vector(7 downto 0);
s_axi_wdata : in std_logic_vector(31 downto 0);
s_axi_rdata : out std_logic_vector(31 downto 0);
s_axi_rresp : out std_logic_vector(1 downto 0);
s_axi_bvalid : out std_logic_vector(0 to 0);
s_axi_rvalid : out std_logic_vector(0 to 0);
s_axi_rlast : out std_logic_vector(0 to 0);
s_axi_wstrb : in std_logic_vector(3 downto 0);
m_axi_awvalid : out std_logic_vector(1 downto 0);
m_axi_awaddr : out std_logic_vector(63 downto 0);
m_axi_awlock : out std_logic_vector(3 downto 0);
m_axi_awready : in std_logic_vector(1 downto 0);
m_axi_arvalid : out std_logic_vector(1 downto 0);
m_axi_araddr : out std_logic_vector(63 downto 0);
m_axi_arlock : out std_logic_vector(3 downto 0);
m_axi_arready : in std_logic_vector(1 downto 0);
m_axi_wvalid : out std_logic_vector(1 downto 0);
m_axi_wlast : out std_logic_vector(1 downto 0);
m_axi_bready : out std_logic_vector(1 downto 0);
m_axi_bresp : in std_logic_vector(3 downto 0);
m_axi_rready : out std_logic_vector(1 downto 0);
m_axi_bid : in std_logic_vector(15 downto 0);
m_axi_rid : in std_logic_vector(15 downto 0);
m_axi_wdata : out std_logic_vector(63 downto 0);
m_axi_rdata : in std_logic_vector(63 downto 0);
m_axi_rresp : in std_logic_vector(3 downto 0);
m_axi_bvalid : in std_logic_vector(1 downto 0);
m_axi_rvalid : in std_logic_vector(1 downto 0);
m_axi_rlast : in std_logic_vector(1 downto 0);
m_axi_wstrb : out std_logic_vector(7 downto 0);
m_axi_wready : in std_logic_vector(1 downto 0);
s_axi_wready : out std_logic_vector(0 to 0)
);
end component gTSE_1to2_switch;
---------------------- End COMPONENT Declaration ------------
------------- Begin Cut here for INSTANTIATION Template -----
u_gTSE_1to2_switch : gTSE_1to2_switch
port map (
rst_n => rst_n,
clk => clk,
s_axi_awvalid => s_axi_awvalid,
s_axi_awaddr => s_axi_awaddr,
s_axi_awlock => s_axi_awlock,
s_axi_awready => s_axi_awready,
s_axi_arvalid => s_axi_arvalid,
s_axi_araddr => s_axi_araddr,
s_axi_arlock => s_axi_arlock,
s_axi_arready => s_axi_arready,
s_axi_wvalid => s_axi_wvalid,
s_axi_wlast => s_axi_wlast,
s_axi_wid => s_axi_wid,
s_axi_bready => s_axi_bready,
s_axi_bresp => s_axi_bresp,
s_axi_rready => s_axi_rready,
s_axi_bid => s_axi_bid,
s_axi_rid => s_axi_rid,
s_axi_wdata => s_axi_wdata,
s_axi_rdata => s_axi_rdata,
s_axi_rresp => s_axi_rresp,
s_axi_bvalid => s_axi_bvalid,
s_axi_rvalid => s_axi_rvalid,
s_axi_rlast => s_axi_rlast,
s_axi_wstrb => s_axi_wstrb,
m_axi_awvalid => m_axi_awvalid,
m_axi_awaddr => m_axi_awaddr,
m_axi_awlock => m_axi_awlock,
m_axi_awready => m_axi_awready,
m_axi_arvalid => m_axi_arvalid,
m_axi_araddr => m_axi_araddr,
m_axi_arlock => m_axi_arlock,
m_axi_arready => m_axi_arready,
m_axi_wvalid => m_axi_wvalid,
m_axi_wlast => m_axi_wlast,
m_axi_bready => m_axi_bready,
m_axi_bresp => m_axi_bresp,
m_axi_rready => m_axi_rready,
m_axi_bid => m_axi_bid,
m_axi_rid => m_axi_rid,
m_axi_wdata => m_axi_wdata,
m_axi_rdata => m_axi_rdata,
m_axi_rresp => m_axi_rresp,
m_axi_bvalid => m_axi_bvalid,
m_axi_rvalid => m_axi_rvalid,
m_axi_rlast => m_axi_rlast,
m_axi_wstrb => m_axi_wstrb,
m_axi_wready => m_axi_wready,
s_axi_wready => s_axi_wready
);
------------------------ End INSTANTIATION Template ---------

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{
"args": [
"-o",
"gTSE_1to2_switch",
"--base_path",
"ip",
"--vlnv",
{
"vendor": "efinixinc.com",
"library": "axi_infra",
"name": "efx_axi_interconnect",
"version": "5.6"
}
],
"conf": {
"ARB_MODE": "\"ROUND_ROBIN_1\"",
"S_PORTS": "1",
"TABLE0_AXI_S0__MIN": "32'd0",
"TABLE0_AXI_S1__MIN": "32'd512",
"TABLE0_AXI_S2__MIN": "32'd285212672",
"TABLE0_AXI_S3__MIN": "32'd286261248",
"TABLE0_AXI_S4__MIN": "32'd536870912",
"TABLE0_AXI_S5__MIN": "32'd805306368",
"TABLE0_AXI_S6__MIN": "32'd1073741824",
"TABLE0_AXI_S7__MIN": "32'd1090519040",
"TABLE0_AXI_S0__MAX": "32'd9",
"TABLE0_AXI_S1__MAX": "32'd8",
"TABLE0_AXI_S2__MAX": "32'd12",
"TABLE0_AXI_S3__MAX": "32'd20",
"TABLE0_AXI_S4__MAX": "32'd28",
"TABLE0_AXI_S5__MAX": "32'd28",
"TABLE0_AXI_S6__MAX": "32'd24",
"TABLE0_AXI_S7__MAX": "32'd20",
"DATA_WIDTH": "32",
"ADDR_WIDTH": "32",
"M_PORTS": "2",
"ID_WIDTH": "8",
"USER_WIDTH": "3",
"PROTOCOL": "\"AXI4_LITE\""
},
"output": {
"external_script_generator": [],
"external_source_source": [],
"external_example_example": [],
"external_testbench_synopsys": [],
"external_testbench_modelsim": [],
"external_testbench_ncsim": [],
"external_testbench_aldec": [],
"external_testbench_testbench": []
},
"ooc_synthesis": {},
"sw_version": "2026.1.132",
"external_path_option": "RELATIVE_PATH"
}

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// =============================================================================
// Generated by efx_ipmgr
// Version: 2025.2.272
// IP Version: 8.1
// =============================================================================
////////////////////////////////////////////////////////////////////////////////
// Copyright (C) 2013-2025 Efinix Inc. All rights reserved.
//
// This document contains proprietary information which is
// protected by copyright. All rights are reserved. This notice
// refers to original work by Efinix, Inc. which may be derivitive
// of other work distributed under license of the authors. In the
// case of derivative work, nothing in this notice overrides the
// original author's license agreement. Where applicable, the
// original license agreement is included in it's original
// unmodified form immediately below this header.
//
// WARRANTY DISCLAIMER.
// THE DESIGN, CODE, OR INFORMATION ARE PROVIDED “AS IS” AND
// EFINIX MAKES NO WARRANTIES, EXPRESS OR IMPLIED WITH
// RESPECT THERETO, AND EXPRESSLY DISCLAIMS ANY IMPLIED WARRANTIES,
// INCLUDING, WITHOUT LIMITATION, THE IMPLIED WARRANTIES OF
// MERCHANTABILITY, NON-INFRINGEMENT AND FITNESS FOR A PARTICULAR
// PURPOSE. SOME STATES DO NOT ALLOW EXCLUSIONS OF AN IMPLIED
// WARRANTY, SO THIS DISCLAIMER MAY NOT APPLY TO LICENSEE.
//
// LIMITATION OF LIABILITY.
// NOTWITHSTANDING ANYTHING TO THE CONTRARY, EXCEPT FOR BODILY
// INJURY, EFINIX SHALL NOT BE LIABLE WITH RESPECT TO ANY SUBJECT
// MATTER OF THIS AGREEMENT UNDER TORT, CONTRACT, STRICT LIABILITY
// OR ANY OTHER LEGAL OR EQUITABLE THEORY (I) FOR ANY INDIRECT,
// SPECIAL, INCIDENTAL, EXEMPLARY OR CONSEQUENTIAL DAMAGES OF ANY
// CHARACTER INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF
// GOODWILL, DATA OR PROFIT, WORK STOPPAGE, OR COMPUTER FAILURE OR
// MALFUNCTION, OR IN ANY EVENT (II) FOR ANY AMOUNT IN EXCESS, IN
// THE AGGREGATE, OF THE FEE PAID BY LICENSEE TO EFINIX HEREUNDER
// (OR, IF THE FEE HAS BEEN WAIVED, $100), EVEN IF EFINIX SHALL HAVE
// BEEN INFORMED OF THE POSSIBILITY OF SUCH DAMAGES. SOME STATES DO
// NOT ALLOW THE EXCLUSION OR LIMITATION OF INCIDENTAL OR
// CONSEQUENTIAL DAMAGES, SO THIS LIMITATION AND EXCLUSION MAY NOT
// APPLY TO LICENSEE.
//
////////////////////////////////////////////////////////////////////////////////
localparam SYNC_CLK = 0;
localparam SYNC_STAGE = 2;
localparam DATA_WIDTH = 16;
localparam MODE = "FWFT";
localparam OUTPUT_REG = 0;
localparam PROG_FULL_ASSERT = 128;
localparam PROGRAMMABLE_FULL = "NONE";
localparam PROG_FULL_NEGATE = 128;
localparam PROGRAMMABLE_EMPTY = "NONE";
localparam PROG_EMPTY_ASSERT = 2;
localparam PROG_EMPTY_NEGATE = 3;
localparam OPTIONAL_FLAGS = 0;
localparam PIPELINE_REG = 1;
localparam DEPTH = 512;
localparam FAMILY = "TITANIUM";
localparam ASYM_WIDTH_RATIO = 4;
localparam BYPASS_RESET_SYNC = 0;
localparam ENDIANESS = 0;
localparam RAM_STYLE = "block_ram";
localparam OVERFLOW_PROTECT = 0;
localparam UNDERFLOW_PROTECT = 0;

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// =============================================================================
// Generated by efx_ipmgr
// Version: 2025.2.272
// IP Version: 8.1
// =============================================================================
////////////////////////////////////////////////////////////////////////////////
// Copyright (C) 2013-2025 Efinix Inc. All rights reserved.
//
// This document contains proprietary information which is
// protected by copyright. All rights are reserved. This notice
// refers to original work by Efinix, Inc. which may be derivitive
// of other work distributed under license of the authors. In the
// case of derivative work, nothing in this notice overrides the
// original author's license agreement. Where applicable, the
// original license agreement is included in it's original
// unmodified form immediately below this header.
//
// WARRANTY DISCLAIMER.
// THE DESIGN, CODE, OR INFORMATION ARE PROVIDED “AS IS” AND
// EFINIX MAKES NO WARRANTIES, EXPRESS OR IMPLIED WITH
// RESPECT THERETO, AND EXPRESSLY DISCLAIMS ANY IMPLIED WARRANTIES,
// INCLUDING, WITHOUT LIMITATION, THE IMPLIED WARRANTIES OF
// MERCHANTABILITY, NON-INFRINGEMENT AND FITNESS FOR A PARTICULAR
// PURPOSE. SOME STATES DO NOT ALLOW EXCLUSIONS OF AN IMPLIED
// WARRANTY, SO THIS DISCLAIMER MAY NOT APPLY TO LICENSEE.
//
// LIMITATION OF LIABILITY.
// NOTWITHSTANDING ANYTHING TO THE CONTRARY, EXCEPT FOR BODILY
// INJURY, EFINIX SHALL NOT BE LIABLE WITH RESPECT TO ANY SUBJECT
// MATTER OF THIS AGREEMENT UNDER TORT, CONTRACT, STRICT LIABILITY
// OR ANY OTHER LEGAL OR EQUITABLE THEORY (I) FOR ANY INDIRECT,
// SPECIAL, INCIDENTAL, EXEMPLARY OR CONSEQUENTIAL DAMAGES OF ANY
// CHARACTER INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF
// GOODWILL, DATA OR PROFIT, WORK STOPPAGE, OR COMPUTER FAILURE OR
// MALFUNCTION, OR IN ANY EVENT (II) FOR ANY AMOUNT IN EXCESS, IN
// THE AGGREGATE, OF THE FEE PAID BY LICENSEE TO EFINIX HEREUNDER
// (OR, IF THE FEE HAS BEEN WAIVED, $100), EVEN IF EFINIX SHALL HAVE
// BEEN INFORMED OF THE POSSIBILITY OF SUCH DAMAGES. SOME STATES DO
// NOT ALLOW THE EXCLUSION OR LIMITATION OF INCIDENTAL OR
// CONSEQUENTIAL DAMAGES, SO THIS LIMITATION AND EXCLUSION MAY NOT
// APPLY TO LICENSEE.
//
////////////////////////////////////////////////////////////////////////////////
gTSE_core_fifo_ctrl u_gTSE_core_fifo_ctrl
(
.full_o ( full_o ),
.empty_o ( empty_o ),
.wr_clk_i ( wr_clk_i ),
.rd_clk_i ( rd_clk_i ),
.wr_en_i ( wr_en_i ),
.rd_en_i ( rd_en_i ),
.wdata ( wdata ),
.rst_busy ( rst_busy ),
.rdata ( rdata ),
.a_rst_i ( a_rst_i ),
.wr_datacount_o ( wr_datacount_o ),
.rd_datacount_o ( rd_datacount_o )
);

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--------------------------------------------------------------------------------
-- Copyright (C) 2013-2025 Efinix Inc. All rights reserved.
--
-- This document contains proprietary information which is
-- protected by copyright. All rights are reserved. This notice
-- refers to original work by Efinix, Inc. which may be derivitive
-- of other work distributed under license of the authors. In the
-- case of derivative work, nothing in this notice overrides the
-- original author's license agreement. Where applicable, the
-- original license agreement is included in it's original
-- unmodified form immediately below this header.
--
-- WARRANTY DISCLAIMER.
-- THE DESIGN, CODE, OR INFORMATION ARE PROVIDED “AS IS” AND
-- EFINIX MAKES NO WARRANTIES, EXPRESS OR IMPLIED WITH
-- RESPECT THERETO, AND EXPRESSLY DISCLAIMS ANY IMPLIED WARRANTIES,
-- INCLUDING, WITHOUT LIMITATION, THE IMPLIED WARRANTIES OF
-- MERCHANTABILITY, NON-INFRINGEMENT AND FITNESS FOR A PARTICULAR
-- PURPOSE. SOME STATES DO NOT ALLOW EXCLUSIONS OF AN IMPLIED
-- WARRANTY, SO THIS DISCLAIMER MAY NOT APPLY TO LICENSEE.
--
-- LIMITATION OF LIABILITY.
-- NOTWITHSTANDING ANYTHING TO THE CONTRARY, EXCEPT FOR BODILY
-- INJURY, EFINIX SHALL NOT BE LIABLE WITH RESPECT TO ANY SUBJECT
-- MATTER OF THIS AGREEMENT UNDER TORT, CONTRACT, STRICT LIABILITY
-- OR ANY OTHER LEGAL OR EQUITABLE THEORY (I) FOR ANY INDIRECT,
-- SPECIAL, INCIDENTAL, EXEMPLARY OR CONSEQUENTIAL DAMAGES OF ANY
-- CHARACTER INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF
-- GOODWILL, DATA OR PROFIT, WORK STOPPAGE, OR COMPUTER FAILURE OR
-- MALFUNCTION, OR IN ANY EVENT (II) FOR ANY AMOUNT IN EXCESS, IN
-- THE AGGREGATE, OF THE FEE PAID BY LICENSEE TO EFINIX HEREUNDER
-- (OR, IF THE FEE HAS BEEN WAIVED, $100), EVEN IF EFINIX SHALL HAVE
-- BEEN INFORMED OF THE POSSIBILITY OF SUCH DAMAGES. SOME STATES DO
-- NOT ALLOW THE EXCLUSION OR LIMITATION OF INCIDENTAL OR
-- CONSEQUENTIAL DAMAGES, SO THIS LIMITATION AND EXCLUSION MAY NOT
-- APPLY TO LICENSEE.
--
--------------------------------------------------------------------------------
------------- Begin Cut here for COMPONENT Declaration ------
component gTSE_core_fifo_ctrl is
port (
full_o : out std_logic;
empty_o : out std_logic;
wr_clk_i : in std_logic;
rd_clk_i : in std_logic;
wr_en_i : in std_logic;
rd_en_i : in std_logic;
wdata : in std_logic_vector(15 downto 0);
rst_busy : out std_logic;
rdata : out std_logic_vector(15 downto 0);
a_rst_i : in std_logic;
wr_datacount_o : out std_logic_vector(9 downto 0);
rd_datacount_o : out std_logic_vector(9 downto 0)
);
end component gTSE_core_fifo_ctrl;
---------------------- End COMPONENT Declaration ------------
------------- Begin Cut here for INSTANTIATION Template -----
u_gTSE_core_fifo_ctrl : gTSE_core_fifo_ctrl
port map (
full_o => full_o,
empty_o => empty_o,
wr_clk_i => wr_clk_i,
rd_clk_i => rd_clk_i,
wr_en_i => wr_en_i,
rd_en_i => rd_en_i,
wdata => wdata,
rst_busy => rst_busy,
rdata => rdata,
a_rst_i => a_rst_i,
wr_datacount_o => wr_datacount_o,
rd_datacount_o => rd_datacount_o
);
------------------------ End INSTANTIATION Template ---------

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{
"args": [
"-o",
"gTSE_core_fifo_ctrl",
"--base_path",
"/projects/SSE/llching/repo/efx_IP_master/efx_IP/efx_hard_soc/fpga/Ti375C529_devkit/ip",
"--vlnv",
{
"vendor": "efinixinc.com",
"library": "memory",
"name": "efx_fifo_top",
"version": "8.1"
}
],
"conf": {
"SYNC_CLK": "0",
"SYNC_STAGE": "2",
"DEPTH_2": "9",
"DATA_WIDTH": "16",
"MODE": "\"FWFT\"",
"OUTPUT_REG": "0",
"PROG_FULL_ASSERT": "128",
"PROGRAMMABLE_FULL": "\"NONE\"",
"PFN_INTERNAL": "127",
"PEA_INTERNAL": "2",
"PEN_INTERNAL": "3",
"PROGRAMMABLE_EMPTY": "\"NONE\"",
"OPTIONAL_FLAGS": "0",
"PIPELINE_REG": "1",
"ASYM_WIDTH_RATIO": "4",
"BYPASS_RESET_SYNC": "0",
"ENDIANESS": "0",
"RAM_STYLE": "\"block_ram\"",
"OVERFLOW_PROTECT": "0",
"UNDERFLOW_PROTECT": "0"
},
"output": {
"external_source_source": [
"gTSE_core_fifo_ctrl/gTSE_core_fifo_ctrl.sv",
"gTSE_core_fifo_ctrl/gTSE_core_fifo_ctrl_define.svh",
"gTSE_core_fifo_ctrl/gTSE_core_fifo_ctrl_tmpl.sv",
"gTSE_core_fifo_ctrl/gTSE_core_fifo_ctrl_tmpl.vhd"
],
"external_example_example": [
"gTSE_core_fifo_ctrl/T20F256_devkit/fifo_demo.peri.xml",
"gTSE_core_fifo_ctrl/T20F256_devkit/fifo_demo.xml",
"gTSE_core_fifo_ctrl/T20F256_devkit/fifo_demo_top.v",
"gTSE_core_fifo_ctrl/T20F256_devkit/fifo_demo_T20.sdc",
"gTSE_core_fifo_ctrl/T20F256_devkit/efx_symmetric_width_fifo_top.sv",
"gTSE_core_fifo_ctrl/T20F256_devkit/gTSE_core_fifo_ctrl.sv",
"gTSE_core_fifo_ctrl/T20F256_devkit/gTSE_core_fifo_ctrl_define.svh"
],
"external_example_2": [
"gTSE_core_fifo_ctrl/Ti60F225_devkit/fifo_demo.peri.xml",
"gTSE_core_fifo_ctrl/Ti60F225_devkit/fifo_demo.xml",
"gTSE_core_fifo_ctrl/Ti60F225_devkit/fifo_demo_top.v",
"gTSE_core_fifo_ctrl/Ti60F225_devkit/fifo_demo_Ti60.sdc",
"gTSE_core_fifo_ctrl/Ti60F225_devkit/efx_symmetric_width_fifo_top.sv",
"gTSE_core_fifo_ctrl/Ti60F225_devkit/gTSE_core_fifo_ctrl.sv",
"gTSE_core_fifo_ctrl/Ti60F225_devkit/gTSE_core_fifo_ctrl_define.svh"
],
"external_testbench_testbench": [
"gTSE_core_fifo_ctrl/Testbench/fifo_tb.sv",
"gTSE_core_fifo_ctrl/Testbench/xrun.sh",
"gTSE_core_fifo_ctrl/Testbench/msim.sh",
"gTSE_core_fifo_ctrl/Testbench/flist",
"gTSE_core_fifo_ctrl/Testbench/modelsim.do",
"gTSE_core_fifo_ctrl/Testbench/gTSE_core_fifo_ctrl.sv",
"gTSE_core_fifo_ctrl/Testbench/gTSE_core_fifo_ctrl_define.svh"
]
},
"ooc_synthesis": {},
"sw_version": "2025.2.272",
"generated_date": "2025-10-16T09:35:38.547531+00:00"
}

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// =============================================================================
// Generated by efx_ipmgr
// Version: 2025.2.272
// IP Version: 8.1
// =============================================================================
////////////////////////////////////////////////////////////////////////////////
// Copyright (C) 2013-2025 Efinix Inc. All rights reserved.
//
// This document contains proprietary information which is
// protected by copyright. All rights are reserved. This notice
// refers to original work by Efinix, Inc. which may be derivitive
// of other work distributed under license of the authors. In the
// case of derivative work, nothing in this notice overrides the
// original author's license agreement. Where applicable, the
// original license agreement is included in it's original
// unmodified form immediately below this header.
//
// WARRANTY DISCLAIMER.
// THE DESIGN, CODE, OR INFORMATION ARE PROVIDED “AS IS” AND
// EFINIX MAKES NO WARRANTIES, EXPRESS OR IMPLIED WITH
// RESPECT THERETO, AND EXPRESSLY DISCLAIMS ANY IMPLIED WARRANTIES,
// INCLUDING, WITHOUT LIMITATION, THE IMPLIED WARRANTIES OF
// MERCHANTABILITY, NON-INFRINGEMENT AND FITNESS FOR A PARTICULAR
// PURPOSE. SOME STATES DO NOT ALLOW EXCLUSIONS OF AN IMPLIED
// WARRANTY, SO THIS DISCLAIMER MAY NOT APPLY TO LICENSEE.
//
// LIMITATION OF LIABILITY.
// NOTWITHSTANDING ANYTHING TO THE CONTRARY, EXCEPT FOR BODILY
// INJURY, EFINIX SHALL NOT BE LIABLE WITH RESPECT TO ANY SUBJECT
// MATTER OF THIS AGREEMENT UNDER TORT, CONTRACT, STRICT LIABILITY
// OR ANY OTHER LEGAL OR EQUITABLE THEORY (I) FOR ANY INDIRECT,
// SPECIAL, INCIDENTAL, EXEMPLARY OR CONSEQUENTIAL DAMAGES OF ANY
// CHARACTER INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF
// GOODWILL, DATA OR PROFIT, WORK STOPPAGE, OR COMPUTER FAILURE OR
// MALFUNCTION, OR IN ANY EVENT (II) FOR ANY AMOUNT IN EXCESS, IN
// THE AGGREGATE, OF THE FEE PAID BY LICENSEE TO EFINIX HEREUNDER
// (OR, IF THE FEE HAS BEEN WAIVED, $100), EVEN IF EFINIX SHALL HAVE
// BEEN INFORMED OF THE POSSIBILITY OF SUCH DAMAGES. SOME STATES DO
// NOT ALLOW THE EXCLUSION OR LIMITATION OF INCIDENTAL OR
// CONSEQUENTIAL DAMAGES, SO THIS LIMITATION AND EXCLUSION MAY NOT
// APPLY TO LICENSEE.
//
////////////////////////////////////////////////////////////////////////////////
localparam SYNC_CLK = 0;
localparam SYNC_STAGE = 2;
localparam DATA_WIDTH = 13;
localparam MODE = "STANDARD";
localparam OUTPUT_REG = 0;
localparam PROG_FULL_ASSERT = 128;
localparam PROGRAMMABLE_FULL = "NONE";
localparam PROG_FULL_NEGATE = 128;
localparam PROGRAMMABLE_EMPTY = "NONE";
localparam PROG_EMPTY_ASSERT = 2;
localparam PROG_EMPTY_NEGATE = 3;
localparam OPTIONAL_FLAGS = 0;
localparam PIPELINE_REG = 1;
localparam DEPTH = 4096;
localparam FAMILY = "TITANIUM";
localparam ASYM_WIDTH_RATIO = 4;
localparam BYPASS_RESET_SYNC = 0;
localparam ENDIANESS = 0;
localparam RAM_STYLE = "block_ram";
localparam OVERFLOW_PROTECT = 0;
localparam UNDERFLOW_PROTECT = 0;

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// =============================================================================
// Generated by efx_ipmgr
// Version: 2025.2.272
// IP Version: 8.1
// =============================================================================
////////////////////////////////////////////////////////////////////////////////
// Copyright (C) 2013-2025 Efinix Inc. All rights reserved.
//
// This document contains proprietary information which is
// protected by copyright. All rights are reserved. This notice
// refers to original work by Efinix, Inc. which may be derivitive
// of other work distributed under license of the authors. In the
// case of derivative work, nothing in this notice overrides the
// original author's license agreement. Where applicable, the
// original license agreement is included in it's original
// unmodified form immediately below this header.
//
// WARRANTY DISCLAIMER.
// THE DESIGN, CODE, OR INFORMATION ARE PROVIDED “AS IS” AND
// EFINIX MAKES NO WARRANTIES, EXPRESS OR IMPLIED WITH
// RESPECT THERETO, AND EXPRESSLY DISCLAIMS ANY IMPLIED WARRANTIES,
// INCLUDING, WITHOUT LIMITATION, THE IMPLIED WARRANTIES OF
// MERCHANTABILITY, NON-INFRINGEMENT AND FITNESS FOR A PARTICULAR
// PURPOSE. SOME STATES DO NOT ALLOW EXCLUSIONS OF AN IMPLIED
// WARRANTY, SO THIS DISCLAIMER MAY NOT APPLY TO LICENSEE.
//
// LIMITATION OF LIABILITY.
// NOTWITHSTANDING ANYTHING TO THE CONTRARY, EXCEPT FOR BODILY
// INJURY, EFINIX SHALL NOT BE LIABLE WITH RESPECT TO ANY SUBJECT
// MATTER OF THIS AGREEMENT UNDER TORT, CONTRACT, STRICT LIABILITY
// OR ANY OTHER LEGAL OR EQUITABLE THEORY (I) FOR ANY INDIRECT,
// SPECIAL, INCIDENTAL, EXEMPLARY OR CONSEQUENTIAL DAMAGES OF ANY
// CHARACTER INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF
// GOODWILL, DATA OR PROFIT, WORK STOPPAGE, OR COMPUTER FAILURE OR
// MALFUNCTION, OR IN ANY EVENT (II) FOR ANY AMOUNT IN EXCESS, IN
// THE AGGREGATE, OF THE FEE PAID BY LICENSEE TO EFINIX HEREUNDER
// (OR, IF THE FEE HAS BEEN WAIVED, $100), EVEN IF EFINIX SHALL HAVE
// BEEN INFORMED OF THE POSSIBILITY OF SUCH DAMAGES. SOME STATES DO
// NOT ALLOW THE EXCLUSION OR LIMITATION OF INCIDENTAL OR
// CONSEQUENTIAL DAMAGES, SO THIS LIMITATION AND EXCLUSION MAY NOT
// APPLY TO LICENSEE.
//
////////////////////////////////////////////////////////////////////////////////
gTSE_core_fifo_data u_gTSE_core_fifo_data
(
.full_o ( full_o ),
.empty_o ( empty_o ),
.wr_clk_i ( wr_clk_i ),
.rd_clk_i ( rd_clk_i ),
.wr_en_i ( wr_en_i ),
.rd_en_i ( rd_en_i ),
.wdata ( wdata ),
.rst_busy ( rst_busy ),
.rdata ( rdata ),
.a_rst_i ( a_rst_i ),
.wr_datacount_o ( wr_datacount_o ),
.rd_datacount_o ( rd_datacount_o )
);

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--------------------------------------------------------------------------------
-- Copyright (C) 2013-2025 Efinix Inc. All rights reserved.
--
-- This document contains proprietary information which is
-- protected by copyright. All rights are reserved. This notice
-- refers to original work by Efinix, Inc. which may be derivitive
-- of other work distributed under license of the authors. In the
-- case of derivative work, nothing in this notice overrides the
-- original author's license agreement. Where applicable, the
-- original license agreement is included in it's original
-- unmodified form immediately below this header.
--
-- WARRANTY DISCLAIMER.
-- THE DESIGN, CODE, OR INFORMATION ARE PROVIDED “AS IS” AND
-- EFINIX MAKES NO WARRANTIES, EXPRESS OR IMPLIED WITH
-- RESPECT THERETO, AND EXPRESSLY DISCLAIMS ANY IMPLIED WARRANTIES,
-- INCLUDING, WITHOUT LIMITATION, THE IMPLIED WARRANTIES OF
-- MERCHANTABILITY, NON-INFRINGEMENT AND FITNESS FOR A PARTICULAR
-- PURPOSE. SOME STATES DO NOT ALLOW EXCLUSIONS OF AN IMPLIED
-- WARRANTY, SO THIS DISCLAIMER MAY NOT APPLY TO LICENSEE.
--
-- LIMITATION OF LIABILITY.
-- NOTWITHSTANDING ANYTHING TO THE CONTRARY, EXCEPT FOR BODILY
-- INJURY, EFINIX SHALL NOT BE LIABLE WITH RESPECT TO ANY SUBJECT
-- MATTER OF THIS AGREEMENT UNDER TORT, CONTRACT, STRICT LIABILITY
-- OR ANY OTHER LEGAL OR EQUITABLE THEORY (I) FOR ANY INDIRECT,
-- SPECIAL, INCIDENTAL, EXEMPLARY OR CONSEQUENTIAL DAMAGES OF ANY
-- CHARACTER INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF
-- GOODWILL, DATA OR PROFIT, WORK STOPPAGE, OR COMPUTER FAILURE OR
-- MALFUNCTION, OR IN ANY EVENT (II) FOR ANY AMOUNT IN EXCESS, IN
-- THE AGGREGATE, OF THE FEE PAID BY LICENSEE TO EFINIX HEREUNDER
-- (OR, IF THE FEE HAS BEEN WAIVED, $100), EVEN IF EFINIX SHALL HAVE
-- BEEN INFORMED OF THE POSSIBILITY OF SUCH DAMAGES. SOME STATES DO
-- NOT ALLOW THE EXCLUSION OR LIMITATION OF INCIDENTAL OR
-- CONSEQUENTIAL DAMAGES, SO THIS LIMITATION AND EXCLUSION MAY NOT
-- APPLY TO LICENSEE.
--
--------------------------------------------------------------------------------
------------- Begin Cut here for COMPONENT Declaration ------
component gTSE_core_fifo_data is
port (
full_o : out std_logic;
empty_o : out std_logic;
wr_clk_i : in std_logic;
rd_clk_i : in std_logic;
wr_en_i : in std_logic;
rd_en_i : in std_logic;
wdata : in std_logic_vector(12 downto 0);
rst_busy : out std_logic;
rdata : out std_logic_vector(12 downto 0);
a_rst_i : in std_logic;
wr_datacount_o : out std_logic_vector(12 downto 0);
rd_datacount_o : out std_logic_vector(12 downto 0)
);
end component gTSE_core_fifo_data;
---------------------- End COMPONENT Declaration ------------
------------- Begin Cut here for INSTANTIATION Template -----
u_gTSE_core_fifo_data : gTSE_core_fifo_data
port map (
full_o => full_o,
empty_o => empty_o,
wr_clk_i => wr_clk_i,
rd_clk_i => rd_clk_i,
wr_en_i => wr_en_i,
rd_en_i => rd_en_i,
wdata => wdata,
rst_busy => rst_busy,
rdata => rdata,
a_rst_i => a_rst_i,
wr_datacount_o => wr_datacount_o,
rd_datacount_o => rd_datacount_o
);
------------------------ End INSTANTIATION Template ---------

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{
"args": [
"-o",
"gTSE_core_fifo_data",
"--base_path",
"/projects/SSE/llching/repo/efx_IP_master/efx_IP/efx_hard_soc/fpga/Ti375C529_devkit/ip",
"--vlnv",
{
"vendor": "efinixinc.com",
"library": "memory",
"name": "efx_fifo_top",
"version": "8.1"
}
],
"conf": {
"SYNC_CLK": "0",
"SYNC_STAGE": "2",
"DEPTH_2": "12",
"DATA_WIDTH": "13",
"MODE": "\"STANDARD\"",
"OUTPUT_REG": "0",
"PROG_FULL_ASSERT": "128",
"PROGRAMMABLE_FULL": "\"NONE\"",
"PFN_INTERNAL": "127",
"PEA_INTERNAL": "2",
"PEN_INTERNAL": "3",
"PROGRAMMABLE_EMPTY": "\"NONE\"",
"OPTIONAL_FLAGS": "0",
"PIPELINE_REG": "1",
"ASYM_WIDTH_RATIO": "4",
"BYPASS_RESET_SYNC": "0",
"ENDIANESS": "0",
"RAM_STYLE": "\"block_ram\"",
"OVERFLOW_PROTECT": "0",
"UNDERFLOW_PROTECT": "0"
},
"output": {
"external_source_source": [
"gTSE_core_fifo_data/gTSE_core_fifo_data.sv",
"gTSE_core_fifo_data/gTSE_core_fifo_data_define.svh",
"gTSE_core_fifo_data/gTSE_core_fifo_data_tmpl.sv",
"gTSE_core_fifo_data/gTSE_core_fifo_data_tmpl.vhd"
],
"external_example_example": [
"gTSE_core_fifo_data/T20F256_devkit/fifo_demo.peri.xml",
"gTSE_core_fifo_data/T20F256_devkit/fifo_demo.xml",
"gTSE_core_fifo_data/T20F256_devkit/fifo_demo_top.v",
"gTSE_core_fifo_data/T20F256_devkit/fifo_demo_T20.sdc",
"gTSE_core_fifo_data/T20F256_devkit/efx_symmetric_width_fifo_top.sv",
"gTSE_core_fifo_data/T20F256_devkit/gTSE_core_fifo_data.sv",
"gTSE_core_fifo_data/T20F256_devkit/gTSE_core_fifo_data_define.svh"
],
"external_example_2": [
"gTSE_core_fifo_data/Ti60F225_devkit/fifo_demo.peri.xml",
"gTSE_core_fifo_data/Ti60F225_devkit/fifo_demo.xml",
"gTSE_core_fifo_data/Ti60F225_devkit/fifo_demo_top.v",
"gTSE_core_fifo_data/Ti60F225_devkit/fifo_demo_Ti60.sdc",
"gTSE_core_fifo_data/Ti60F225_devkit/efx_symmetric_width_fifo_top.sv",
"gTSE_core_fifo_data/Ti60F225_devkit/gTSE_core_fifo_data.sv",
"gTSE_core_fifo_data/Ti60F225_devkit/gTSE_core_fifo_data_define.svh"
],
"external_testbench_testbench": [
"gTSE_core_fifo_data/Testbench/fifo_tb.sv",
"gTSE_core_fifo_data/Testbench/xrun.sh",
"gTSE_core_fifo_data/Testbench/msim.sh",
"gTSE_core_fifo_data/Testbench/flist",
"gTSE_core_fifo_data/Testbench/modelsim.do",
"gTSE_core_fifo_data/Testbench/gTSE_core_fifo_data.sv",
"gTSE_core_fifo_data/Testbench/gTSE_core_fifo_data_define.svh"
]
},
"ooc_synthesis": {},
"sw_version": "2025.2.272",
"generated_date": "2025-10-16T09:35:27.104449+00:00"
}

460
Ti375C529_devkit/source/MacRxCheckSumChecker.v Normal file
View File

@@ -0,0 +1,460 @@
`timescale 1ns/1ps
`define IP_MODULE_NAME(name) name
module `IP_MODULE_NAME(MacRxCheckSumChecker) (
input wire io_input_valid,
output reg io_input_ready,
input wire io_input_payload_last,
input wire io_input_payload_fragment_error,
input wire [7:0] io_input_payload_fragment_data,
output reg io_output_valid,
input wire io_output_ready,
output reg io_output_payload_last,
output reg io_output_payload_fragment_error,
output reg [7:0] io_output_payload_fragment_data,
input wire clk,
input wire reset
);
//pragma protect
//pragma protect begin
/* Encryption Envelope */
`pragma protect begin_protected
`pragma protect version = 1
`pragma protect encrypt_agent = "QuestaSim" , encrypt_agent_info = "2021.1"
`pragma protect key_keyowner = "Efinix Inc." , key_keyname = "EFX_K01"
`pragma protect key_method = "rsa"
`pragma protect encoding = ( enctype = "base64" , line_length = 64 , bytes = 256 )
`pragma protect key_block
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`pragma protect encoding = ( enctype = "base64" , line_length = 64 , bytes = 20032 )
`pragma protect data_block
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`pragma protect end_protected
//pragma protect end
`undef IP_MODULE_NAME

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Ti375C529_devkit/source/MacTxLso.v Normal file
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Ti375C529_devkit/source/design_modules.v Normal file
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Ti375C529_devkit/source/top_soc.v Normal file
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@@ -0,0 +1,888 @@
`define ETH_1000MBPS 1
module top_soc (
output jtagCtrl_tdi,
input jtagCtrl_tdo,
output jtagCtrl_enable,
output jtagCtrl_capture,
output jtagCtrl_shift,
output jtagCtrl_update,
output jtagCtrl_reset,
input ut_jtagCtrl_tdi,
output ut_jtagCtrl_tdo,
input ut_jtagCtrl_enable,
input ut_jtagCtrl_capture,
input ut_jtagCtrl_shift,
input ut_jtagCtrl_update,
input ut_jtagCtrl_reset,
input io_cfuClk,
input io_cfuReset,
input cpu0_customInstruction_cmd_valid,
output cpu0_customInstruction_cmd_ready,
input [9:0] cpu0_customInstruction_function_id,
input [31:0] cpu0_customInstruction_inputs_0,
input [31:0] cpu0_customInstruction_inputs_1,
output cpu0_customInstruction_rsp_valid,
input cpu0_customInstruction_rsp_ready,
output [31:0] cpu0_customInstruction_outputs_0,
input cpu1_customInstruction_cmd_valid,
output cpu1_customInstruction_cmd_ready,
input [9:0] cpu1_customInstruction_function_id,
input [31:0] cpu1_customInstruction_inputs_0,
input [31:0] cpu1_customInstruction_inputs_1,
output cpu1_customInstruction_rsp_valid,
input cpu1_customInstruction_rsp_ready,
output [31:0] cpu1_customInstruction_outputs_0,
input cpu2_customInstruction_cmd_valid,
output cpu2_customInstruction_cmd_ready,
input [9:0] cpu2_customInstruction_function_id,
input [31:0] cpu2_customInstruction_inputs_0,
input [31:0] cpu2_customInstruction_inputs_1,
output cpu2_customInstruction_rsp_valid,
input cpu2_customInstruction_rsp_ready,
output [31:0] cpu2_customInstruction_outputs_0,
input cpu3_customInstruction_cmd_valid,
output cpu3_customInstruction_cmd_ready,
input [9:0] cpu3_customInstruction_function_id,
input [31:0] cpu3_customInstruction_inputs_0,
input [31:0] cpu3_customInstruction_inputs_1,
output cpu3_customInstruction_rsp_valid,
input cpu3_customInstruction_rsp_ready,
output [31:0] cpu3_customInstruction_outputs_0,
output io_ddrMasters_0_aw_valid,
input io_ddrMasters_0_aw_ready,
output [31:0] io_ddrMasters_0_aw_payload_addr,
output [3:0] io_ddrMasters_0_aw_payload_id,
output [3:0] io_ddrMasters_0_aw_payload_region,
output [7:0] io_ddrMasters_0_aw_payload_len,
output [2:0] io_ddrMasters_0_aw_payload_size,
output [1:0] io_ddrMasters_0_aw_payload_burst,
output io_ddrMasters_0_aw_payload_lock,
output [3:0] io_ddrMasters_0_aw_payload_cache,
output [3:0] io_ddrMasters_0_aw_payload_qos,
output [2:0] io_ddrMasters_0_aw_payload_prot,
output io_ddrMasters_0_aw_payload_allStrb,
output io_ddrMasters_0_w_valid,
input io_ddrMasters_0_w_ready,
output [127:0] io_ddrMasters_0_w_payload_data,
output [15:0] io_ddrMasters_0_w_payload_strb,
output io_ddrMasters_0_w_payload_last,
input io_ddrMasters_0_b_valid,
output io_ddrMasters_0_b_ready,
input [3:0] io_ddrMasters_0_b_payload_id,
input [1:0] io_ddrMasters_0_b_payload_resp,
output io_ddrMasters_0_ar_valid,
input io_ddrMasters_0_ar_ready,
output [31:0] io_ddrMasters_0_ar_payload_addr,
output [3:0] io_ddrMasters_0_ar_payload_id,
output [3:0] io_ddrMasters_0_ar_payload_region,
output [7:0] io_ddrMasters_0_ar_payload_len,
output [2:0] io_ddrMasters_0_ar_payload_size,
output [1:0] io_ddrMasters_0_ar_payload_burst,
output io_ddrMasters_0_ar_payload_lock,
output [3:0] io_ddrMasters_0_ar_payload_cache,
output [3:0] io_ddrMasters_0_ar_payload_qos,
output [2:0] io_ddrMasters_0_ar_payload_prot,
input io_ddrMasters_0_r_valid,
output io_ddrMasters_0_r_ready,
input [127:0] io_ddrMasters_0_r_payload_data,
input [3:0] io_ddrMasters_0_r_payload_id,
input [1:0] io_ddrMasters_0_r_payload_resp,
input io_ddrMasters_0_r_payload_last,
input io_ddrMasters_0_clk,
input io_ddrMasters_0_reset,
output io_ddrMasters_memCheck_pass,
output userInterruptA,
output userInterruptB,
output userInterruptC,
output userInterruptD,
output userInterruptE,
output userInterruptF,
output userInterruptH,
output userInterruptG,
output userInterruptI,
input [3:0] system_gpio_0_io_read,
output [3:0] system_gpio_0_io_write,
output [3:0] system_gpio_0_io_writeEnable,
output system_uart_0_io_txd,
input system_uart_0_io_rxd,
output system_spi_0_io_sclk_write,
output system_spi_0_io_data_0_writeEnable,
input system_spi_0_io_data_0_read,
output system_spi_0_io_data_0_write,
output system_spi_0_io_data_1_writeEnable,
input system_spi_0_io_data_1_read,
output system_spi_0_io_data_1_write,
output system_spi_0_io_data_2_writeEnable,
input system_spi_0_io_data_2_read,
output system_spi_0_io_data_2_write,
output system_spi_0_io_data_3_writeEnable,
input system_spi_0_io_data_3_read,
output system_spi_0_io_data_3_write,
output [3:0] system_spi_0_io_ss,
output system_i2c_0_io_sda_writeEnable,
output system_i2c_0_io_sda_write,
input system_i2c_0_io_sda_read,
output system_i2c_0_io_scl_writeEnable,
output system_i2c_0_io_scl_write,
input system_i2c_0_io_scl_read,
input [31:0] axiA_awaddr,
input [7:0] axiA_awlen,
input [2:0] axiA_awsize,
input [1:0] axiA_awburst,
input axiA_awlock,
input [3:0] axiA_awcache,
input [2:0] axiA_awprot,
input [3:0] axiA_awqos,
input [3:0] axiA_awregion,
input axiA_awvalid,
output axiA_awready,
input [31:0] axiA_wdata,
input [3:0] axiA_wstrb,
input axiA_wvalid,
input axiA_wlast,
output axiA_wready,
output [1:0] axiA_bresp,
output axiA_bvalid,
input axiA_bready,
input [31:0] axiA_araddr,
input [7:0] axiA_arlen,
input [2:0] axiA_arsize,
input [1:0] axiA_arburst,
input axiA_arlock,
input [3:0] axiA_arcache,
input [2:0] axiA_arprot,
input [3:0] axiA_arqos,
input [3:0] axiA_arregion,
input axiA_arvalid,
output axiA_arready,
output [31:0] axiA_rdata,
output [1:0] axiA_rresp,
output axiA_rlast,
output axiA_rvalid,
input axiA_rready,
output axiAInterrupt,
input cfg_done,
output cfg_start,
output cfg_sel,
output cfg_reset,
input io_peripheralClk,
input io_peripheralReset,
output io_asyncReset,
input io_gpio_sw_n,
input pll_peripheral_locked,
input pll_system_locked,
input pll_tse_locked,
// SDHC
input sd_base_clk,
output sd_clk_hi,
output sd_clk_lo,
input sd_cmd_i,
output sd_cmd_o,
output sd_cmd_oe,
input [3:0] sd_dat_i,
output [3:0] sd_dat_o,
output [3:0] sd_dat_oe,
input sd_cd_n,
input sd_wp,
// TSEMAC
input io_tseClk,
// MAC
output [3:0] rgmii_txd_HI,
output [3:0] rgmii_txd_LO,
output rgmii_tx_ctl_HI,
output rgmii_tx_ctl_LO,
output rgmii_txc_HI,
output rgmii_txc_LO,
input [3:0] rgmii_rxd_HI,
input [3:0] rgmii_rxd_LO,
input rgmii_rx_ctl_HI,
input rgmii_rx_ctl_LO,
input mux_clk,
output [1:0] mux_clk_sw,
// PHY
output phy_rst,
input phy_mdi,
output phy_mdo,
output phy_mdo_en,
output phy_mdc,
input rgmii_rxc,
input rgmii_rxc_slow
);
////////////////////////////////////////////////////////////////////////////
localparam PERI_FREQ = 200;
localparam AXIS_DEV = 3;
localparam AXIM_DEV = 2;
localparam SLB = 0;
// SDHC
localparam SDHC = 1;
localparam MSDHC = 0;
// TSEMAC
localparam TSE = 2;
localparam MTSE = 1;
////////////////////////////////////////////////////////////////////////////
// Switch between sdhc and slb
wire [(AXIS_DEV*32)-1:0] gAXIS_m_awaddr;
wire [(AXIS_DEV*8)-1:0] gAXIS_m_awlen;
wire [(AXIS_DEV*3)-1:0] gAXIS_m_awsize;
wire [(AXIS_DEV*2)-1:0] gAXIS_m_awburst;
wire [(AXIS_DEV*2)-1:0] gAXIS_m_awlock;
wire [(AXIS_DEV*4)-1:0] gAXIS_m_awcache;
wire [(AXIS_DEV*4)-1:0] gAXIS_m_awprot;
wire [(AXIS_DEV*4)-1:0] gAXIS_m_awqos;
wire [(AXIS_DEV*4)-1:0] gAXIS_m_awregion;
wire [AXIS_DEV-1:0] gAXIS_m_awvalid;
wire [AXIS_DEV-1:0] gAXIS_m_awready;
wire [(AXIS_DEV*32)-1:0] gAXIS_m_wdata;
wire [(AXIS_DEV*4)-1:0] gAXIS_m_wstrb;
wire [AXIS_DEV-1:0] gAXIS_m_wvalid;
wire [AXIS_DEV-1:0] gAXIS_m_wlast;
wire [AXIS_DEV-1:0] gAXIS_m_wready;
wire [(AXIS_DEV*2)-1:0] gAXIS_m_bresp;
wire [AXIS_DEV-1:0] gAXIS_m_bvalid;
wire [AXIS_DEV-1:0] gAXIS_m_bready;
wire [(AXIS_DEV*32)-1:0] gAXIS_m_araddr;
wire [(AXIS_DEV*8)-1:0] gAXIS_m_arlen;
wire [(AXIS_DEV*3)-1:0] gAXIS_m_arsize;
wire [(AXIS_DEV*2)-1:0] gAXIS_m_arburst;
wire [(AXIS_DEV*2)-1:0] gAXIS_m_arlock;
wire [(AXIS_DEV*4)-1:0] gAXIS_m_arcache;
wire [(AXIS_DEV*4)-1:0] gAXIS_m_arprot;
wire [(AXIS_DEV*4)-1:0] gAXIS_m_arqos;
wire [(AXIS_DEV*4)-1:0] gAXIS_m_arregion;
wire [AXIS_DEV-1:0] gAXIS_m_arvalid;
wire [AXIS_DEV-1:0] gAXIS_m_arready;
wire [(AXIS_DEV*32)-1:0] gAXIS_m_rdata;
wire [(AXIS_DEV*2)-1:0] gAXIS_m_rresp;
wire [AXIS_DEV-1:0] gAXIS_m_rlast;
wire [AXIS_DEV-1:0] gAXIS_m_rvalid;
wire [AXIS_DEV-1:0] gAXIS_m_rready;
// Switch between sdhc and tsemac
wire [(AXIM_DEV*32)-1:0] gAXIM_s_awaddr;
wire [(AXIM_DEV*8)-1:0] gAXIM_s_awlen;
wire [(AXIM_DEV*3)-1:0] gAXIM_s_awsize;
wire [(AXIM_DEV*2)-1:0] gAXIM_s_awburst;
wire [(AXIM_DEV*2)-1:0] gAXIM_s_awlock;
wire [(AXIM_DEV*4)-1:0] gAXIM_s_awcache;
wire [(AXIM_DEV*4)-1:0] gAXIM_s_awprot;
wire [(AXIM_DEV*4)-1:0] gAXIM_s_awqos;
wire [(AXIM_DEV*4)-1:0] gAXIM_s_awregion;
wire [AXIM_DEV-1:0] gAXIM_s_awvalid;
wire [AXIM_DEV-1:0] gAXIM_s_awready;
wire [(AXIM_DEV*128)-1:0] gAXIM_s_wdata;
wire [(AXIM_DEV*16)-1:0] gAXIM_s_wstrb;
wire [AXIM_DEV-1:0] gAXIM_s_wvalid;
wire [AXIM_DEV-1:0] gAXIM_s_wlast;
wire [AXIM_DEV-1:0] gAXIM_s_wready;
wire [(AXIM_DEV*2)-1:0] gAXIM_s_bresp;
wire [AXIM_DEV-1:0] gAXIM_s_bvalid;
wire [AXIM_DEV-1:0] gAXIM_s_bready;
wire [(AXIM_DEV*32)-1:0] gAXIM_s_araddr;
wire [(AXIM_DEV*8)-1:0] gAXIM_s_arlen;
wire [(AXIM_DEV*3)-1:0] gAXIM_s_arsize;
wire [(AXIM_DEV*2)-1:0] gAXIM_s_arburst;
wire [(AXIM_DEV*2)-1:0] gAXIM_s_arlock;
wire [(AXIM_DEV*4)-1:0] gAXIM_s_arcache;
wire [(AXIM_DEV*4)-1:0] gAXIM_s_arprot;
wire [(AXIM_DEV*4)-1:0] gAXIM_s_arqos;
wire [(AXIM_DEV*4)-1:0] gAXIM_s_arregion;
wire [AXIM_DEV-1:0] gAXIM_s_arvalid;
wire [AXIM_DEV-1:0] gAXIM_s_arready;
wire [(AXIM_DEV*128)-1:0] gAXIM_s_rdata;
wire [(AXIM_DEV*2)-1:0] gAXIM_s_rresp;
wire [AXIM_DEV-1:0] gAXIM_s_rlast;
wire [AXIM_DEV-1:0] gAXIM_s_rvalid;
wire [AXIM_DEV-1:0] gAXIM_s_rready;
// SDHC
wire sd_rst;
wire sd_int;
wire sd_dat_oe_i;
// DMA
wire dma_tx_rst;
wire dma_rx_rst;
wire dma_tx_descriptorUpdate;
wire [1:0] dma_interrupts;
wire [31:0] dma_apb3_paddr;
wire dma_apb3_psel;
wire dma_apb3_penable;
wire dma_apb3_pready;
wire dma_apb3_pwrite;
wire [31:0] dma_apb3_pwdata;
wire [31:0] dma_apb3_prdata;
wire dma_apb3_pslverror;
// TSE
wire tse_pll_ok;
wire phy_sw_rst;
wire mac_ext_rst;
wire [2:0] eth_speed;
wire s_eth_tx_tvalid;
wire s_eth_tx_tready;
wire [7:0] s_eth_tx_tdata;
wire [0:0] s_eth_tx_tkeep;
wire [3:0] s_eth_tx_tdest;
wire s_eth_tx_tlast;
wire m_eth_rx_tvalid;
wire m_eth_rx_tready;
wire [7:0] m_eth_rx_tdata;
wire [0:0] m_eth_rx_tkeep;
wire [3:0] m_eth_rx_tdest;
wire m_eth_rx_tlast;
//reset
wire io_asyncReset_soc;
wire watchdog_reset;
gAXIS_1to3_switch u_AXIS_1to3_switch
(
.rst_n ( ~io_peripheralReset ),
.clk ( io_peripheralClk ),
.m_axi_awvalid ( gAXIS_m_awvalid ),
.m_axi_awready ( gAXIS_m_awready ),
.m_axi_awid ( ),
.m_axi_awaddr ( gAXIS_m_awaddr ),
.m_axi_awburst ( gAXIS_m_awburst ),
.m_axi_awlen ( gAXIS_m_awlen ),
.m_axi_awsize ( gAXIS_m_awsize ),
.m_axi_awcache ( gAXIS_m_awcache ),
.m_axi_awqos ( gAXIS_m_awqos ),
.m_axi_awprot ( gAXIS_m_awprot ),
.m_axi_awuser ( ),
.m_axi_awlock ( gAXIS_m_awlock ),
.m_axi_awregion ( gAXIS_m_awregion ),
.m_axi_wvalid ( gAXIS_m_wvalid ),
.m_axi_wready ( gAXIS_m_wready ),
.m_axi_wdata ( gAXIS_m_wdata ),
.m_axi_wstrb ( gAXIS_m_wstrb ),
.m_axi_wlast ( gAXIS_m_wlast ),
.m_axi_wuser ( ),
.m_axi_bready ( gAXIS_m_bready ),
.m_axi_bvalid ( gAXIS_m_bvalid ),
.m_axi_bresp ( gAXIS_m_bresp ),
.m_axi_buser ( {AXIS_DEV{3'h0}} ),
.m_axi_bid ( {AXIS_DEV{8'h0}} ),
.m_axi_arvalid ( gAXIS_m_arvalid ),
.m_axi_arready ( gAXIS_m_arready ),
.m_axi_arid ( ),
.m_axi_araddr ( gAXIS_m_araddr ),
.m_axi_arburst ( gAXIS_m_arburst ),
.m_axi_arlen ( gAXIS_m_arlen ),
.m_axi_arsize ( gAXIS_m_arsize ),
.m_axi_arlock ( gAXIS_m_arlock ),
.m_axi_arprot ( gAXIS_m_arprot ),
.m_axi_arcache ( gAXIS_m_arcache ),
.m_axi_arqos ( gAXIS_m_arqos ),
.m_axi_aruser ( ),
.m_axi_arregion ( gAXIS_m_arregion ),
.m_axi_ruser ( {AXIS_DEV{3'h0}}),
.m_axi_rvalid ( gAXIS_m_rvalid ),
.m_axi_rready ( gAXIS_m_rready ),
.m_axi_rid ( {AXIS_DEV{8'h0}}),
.m_axi_rdata ( gAXIS_m_rdata ),
.m_axi_rresp ( gAXIS_m_rresp ),
.m_axi_rlast ( gAXIS_m_rlast ),
.s_axi_awvalid ( axiA_awvalid ),
.s_axi_awready ( axiA_awready ),
.s_axi_awaddr ( {7'h00, axiA_awaddr[24:0]} ),
.s_axi_awid ( 8'h00 ),
.s_axi_awburst ( axiA_awburst ),
.s_axi_awlen ( axiA_awlen ),
.s_axi_awsize ( axiA_awsize ),
.s_axi_awprot ( {1'b0, axiA_awprot} ),
.s_axi_awlock ( {1'b0, axiA_awlock} ),
.s_axi_awcache ( axiA_awcache ),
.s_axi_awqos ( axiA_awqos ),
.s_axi_awuser ( 3'h0 ),
.s_axi_wvalid ( axiA_wvalid ),
.s_axi_wready ( axiA_wready ),
.s_axi_wid ( 8'h00 ),
.s_axi_wdata ( axiA_wdata ),
.s_axi_wlast ( axiA_wlast ),
.s_axi_wstrb ( axiA_wstrb ),
.s_axi_wuser ( 3'h0 ),
.s_axi_bvalid ( axiA_bvalid ),
.s_axi_bready ( axiA_bready ),
.s_axi_bresp ( axiA_bresp ),
.s_axi_bid ( ),
.s_axi_buser ( ),
.s_axi_arvalid ( axiA_arvalid ),
.s_axi_arready ( axiA_arready ),
.s_axi_araddr ( {7'h00, axiA_araddr[24:0]} ),
.s_axi_arid ( 8'h00 ),
.s_axi_arburst ( axiA_arburst ),
.s_axi_arlen ( axiA_arlen ),
.s_axi_arsize ( axiA_arsize ),
.s_axi_arprot ( { 1'b0, axiA_arprot} ),
.s_axi_arlock ( { 1'b0, axiA_arlock} ),
.s_axi_arcache ( axiA_arcache ),
.s_axi_arqos ( axiA_arqos ),
.s_axi_aruser ( 3'h0 ),
.s_axi_rready ( axiA_rready ),
.s_axi_rvalid ( axiA_rvalid ),
.s_axi_rdata ( axiA_rdata ),
.s_axi_rresp ( axiA_rresp ),
.s_axi_rlast ( axiA_rlast ),
.s_axi_rid ( ),
.s_axi_ruser ( )
);
gAXIM_2to1_switch u_AXIM_2to1_switch
(
.rst_n ( ~io_ddrMasters_0_reset ),
.clk ( io_ddrMasters_0_clk ),
.m_axi_awvalid ( io_ddrMasters_0_aw_valid ),
.m_axi_awready ( io_ddrMasters_0_aw_ready ),
.m_axi_awid ( io_ddrMasters_0_aw_payload_id ),
.m_axi_awaddr ( io_ddrMasters_0_aw_payload_addr ),
.m_axi_awburst ( io_ddrMasters_0_aw_payload_burst ),
.m_axi_awlen ( io_ddrMasters_0_aw_payload_len ),
.m_axi_awsize ( io_ddrMasters_0_aw_payload_size ),
.m_axi_awcache ( io_ddrMasters_0_aw_payload_cache ),
.m_axi_awqos ( io_ddrMasters_0_aw_payload_qos ),
.m_axi_awprot ( io_ddrMasters_0_aw_payload_prot ),
.m_axi_awuser ( ),
.m_axi_awlock ( io_ddrMasters_0_aw_payload_lock ),
.m_axi_awregion ( io_ddrMasters_0_aw_payload_region ),
.m_axi_wvalid ( io_ddrMasters_0_w_valid ),
.m_axi_wready ( io_ddrMasters_0_w_ready ),
.m_axi_wdata ( io_ddrMasters_0_w_payload_data ),
.m_axi_wstrb ( io_ddrMasters_0_w_payload_strb ),
.m_axi_wlast ( io_ddrMasters_0_w_payload_last ),
.m_axi_wuser ( ),
.m_axi_bready ( io_ddrMasters_0_b_ready ),
.m_axi_bvalid ( io_ddrMasters_0_b_valid ),
.m_axi_bresp ( io_ddrMasters_0_b_payload_resp ),
.m_axi_buser ( 3'h0 ),
.m_axi_bid ( {4'h0, io_ddrMasters_0_b_payload_id} ),
.m_axi_arvalid ( io_ddrMasters_0_ar_valid ),
.m_axi_arready ( io_ddrMasters_0_ar_ready ),
.m_axi_arid ( io_ddrMasters_0_ar_payload_id ),
.m_axi_araddr ( io_ddrMasters_0_ar_payload_addr ),
.m_axi_arburst ( io_ddrMasters_0_ar_payload_burst ),
.m_axi_arlen ( io_ddrMasters_0_ar_payload_len ),
.m_axi_arsize ( io_ddrMasters_0_ar_payload_size ),
.m_axi_arlock ( io_ddrMasters_0_ar_payload_lock ),
.m_axi_arprot ( io_ddrMasters_0_ar_payload_prot ),
.m_axi_arcache ( io_ddrMasters_0_ar_payload_cache ),
.m_axi_arqos ( io_ddrMasters_0_ar_payload_qos ),
.m_axi_aruser ( ),
.m_axi_arregion ( io_ddrMasters_0_ar_payload_region ),
.m_axi_ruser ( 3'h0),
.m_axi_rvalid ( io_ddrMasters_0_r_valid ),
.m_axi_rready ( io_ddrMasters_0_r_ready ),
.m_axi_rid ( 8'h0 ),
.m_axi_rdata ( io_ddrMasters_0_r_payload_data ),
.m_axi_rresp ( io_ddrMasters_0_r_payload_resp ),
.m_axi_rlast ( io_ddrMasters_0_r_payload_last ),
.s_axi_awvalid ( gAXIM_s_awvalid ),
.s_axi_awready ( gAXIM_s_awready ),
.s_axi_awaddr ( gAXIM_s_awaddr ),
.s_axi_awid ( {AXIM_DEV{8'h00}} ),
.s_axi_awburst ( gAXIM_s_awburst ),
.s_axi_awlen ( gAXIM_s_awlen ),
.s_axi_awsize ( gAXIM_s_awsize ),
.s_axi_awprot ( gAXIM_s_awprot ),
.s_axi_awlock ( gAXIM_s_awlock ),
.s_axi_awcache ( gAXIM_s_awcache ),
.s_axi_awqos ( gAXIM_s_awqos ),
.s_axi_awuser ( {AXIM_DEV{3'h0}} ),
.s_axi_wvalid ( gAXIM_s_wvalid ),
.s_axi_wready ( gAXIM_s_wready ),
.s_axi_wid ( {AXIM_DEV{8'h00}} ),
.s_axi_wdata ( gAXIM_s_wdata ),
.s_axi_wlast ( gAXIM_s_wlast ),
.s_axi_wstrb ( gAXIM_s_wstrb ),
.s_axi_wuser ( {AXIM_DEV{3'h0}} ),
.s_axi_bvalid ( gAXIM_s_bvalid ),
.s_axi_bready ( gAXIM_s_bready ),
.s_axi_bresp ( gAXIM_s_bresp ),
.s_axi_bid ( ),
.s_axi_buser ( ),
.s_axi_arvalid ( gAXIM_s_arvalid ),
.s_axi_arready ( gAXIM_s_arready ),
.s_axi_araddr ( gAXIM_s_araddr ),
.s_axi_arid ( {AXIM_DEV{8'h00}} ),
.s_axi_arburst ( gAXIM_s_arburst ),
.s_axi_arlen ( gAXIM_s_arlen ),
.s_axi_arsize ( gAXIM_s_arsize ),
.s_axi_arprot ( gAXIM_s_axiA_arprot ),
.s_axi_arlock ( gAXIM_s_axiA_arlock ),
.s_axi_arcache ( gAXIM_s_arcache ),
.s_axi_arqos ( gAXIM_s_arqos ),
.s_axi_aruser ( {AXIM_DEV{3'h0}} ),
.s_axi_rready ( gAXIM_s_rready ),
.s_axi_rvalid ( gAXIM_s_rvalid ),
.s_axi_rdata ( gAXIM_s_rdata ),
.s_axi_rresp ( gAXIM_s_rresp ),
.s_axi_rlast ( gAXIM_s_rlast ),
.s_axi_rid ( ),
.s_axi_ruser ( )
);
assign sd_rst = io_peripheralReset;
assign gAXIS_m_rlast[SDHC*1 +: 1] = 1'b1;
assign sd_dat_oe = {4{sd_dat_oe_i}};
assign userInterruptI = sd_int;
gSDHC u_gSDHC
(
.sd_rst ( sd_rst ),
.sd_base_clk ( sd_base_clk ),
.sd_int ( sd_int ),
.sd_cd_n ( sd_cd_n ),
.sd_wp ( sd_wp ),
.s_axi_aclk ( io_peripheralClk ),
.s_axi_awaddr ( gAXIS_m_awaddr[SDHC*32 +: 32] ),
.s_axi_awready ( gAXIS_m_awready[SDHC*1 +: 1] ),
.s_axi_awvalid ( gAXIS_m_awvalid[SDHC*1 +: 1] ),
.s_axi_wstrb ( gAXIS_m_wstrb[SDHC*4 +: 4]),
.s_axi_wdata ( gAXIS_m_wdata[SDHC*32 +: 32] ),
.s_axi_wready ( gAXIS_m_wready[SDHC*1 +: 1] ),
.s_axi_wvalid ( gAXIS_m_wvalid[SDHC*1 +: 1] ),
.s_axi_bresp ( gAXIS_m_bresp[SDHC*2 +: 2] ),
.s_axi_bvalid ( gAXIS_m_bvalid[SDHC*1 +: 1] ),
.s_axi_araddr ( gAXIS_m_araddr[SDHC*32 +: 32] ),
.s_axi_bready ( gAXIS_m_bready[SDHC*1 +: 1] ),
.s_axi_arready ( gAXIS_m_arready[SDHC*1 +: 1] ),
.s_axi_arvalid ( gAXIS_m_arvalid[SDHC*1 +: 1] ),
.s_axi_rresp ( gAXIS_m_rresp[SDHC*2 +: 2] ),
.s_axi_rdata ( gAXIS_m_rdata[SDHC*32 +: 32]),
.s_axi_rvalid ( gAXIS_m_rvalid[SDHC*1 +: 1] ),
.s_axi_rready ( gAXIS_m_rready[SDHC*1 +: 1] ),
.m_axi_clk ( io_ddrMasters_0_clk ),
.m_axi_awaddr ( gAXIM_s_awaddr[MSDHC*32 +: 32] ),
.m_axi_awvalid ( gAXIM_s_awvalid[MSDHC*1 +: 1] ),
.m_axi_awlen ( gAXIM_s_awlen[MSDHC*8 +: 8] ),
.m_axi_awready ( gAXIM_s_awready[MSDHC*1 +: 1] ),
.m_axi_awburst ( gAXIM_s_awburst[MSDHC*2 +: 2] ),
.m_axi_awsize ( gAXIM_s_awsize[MSDHC*3 +: 3] ),
.m_axi_awcache ( gAXIM_s_awcache[MSDHC*4 +: 4] ),
.m_axi_awlock ( gAXIM_s_awlock[MSDHC*2 +: 2] ),
.m_axi_awprot ( gAXIM_s_awprot[MSDHC*4 +: 4] ),
.m_axi_wdata ( gAXIM_s_wdata[MSDHC*128 +: 128] ),
.m_axi_wstrb ( gAXIM_s_wstrb[MSDHC*16 +: 16] ),
.m_axi_wlast ( gAXIM_s_wlast[MSDHC*1 +: 1] ),
.m_axi_wvalid ( gAXIM_s_wvalid[MSDHC*1 +: 1] ),
.m_axi_wready ( gAXIM_s_wready[MSDHC*1 +:1] ),
.m_axi_bresp ( gAXIM_s_bresp[MSDHC*2 +: 2] ),
.m_axi_bvalid ( gAXIM_s_bvalid[MSDHC*1 +: 1] ),
.m_axi_bready ( gAXIM_s_bready[MSDHC*1 +: 1] ),
.m_axi_arvalid ( gAXIM_s_arvalid[MSDHC*1 +: 1] ),
.m_axi_araddr ( gAXIM_s_araddr[MSDHC*32 +: 32] ),
.m_axi_arlen ( gAXIM_s_arlen[MSDHC*8 +: 8] ),
.m_axi_arsize ( gAXIM_s_arsize[MSDHC*3 +: 3] ),
.m_axi_arburst ( gAXIM_s_arburst[MSDHC*2 +: 2] ),
.m_axi_arprot ( gAXIM_s_arprot[MSDHC*4 +: 4] ),
.m_axi_arlock ( gAXIM_s_arlock[MSDHC*2 +: 2] ),
.m_axi_arcache ( gAXIM_s_arcache[MSDHC*4 +: 4] ),
.m_axi_arready ( gAXIM_s_arready[MSDHC*1 +: 1] ),
.m_axi_rvalid ( gAXIM_s_rvalid[MSDHC*1 +: 1] ),
.m_axi_rdata ( gAXIM_s_rdata[MSDHC*128 +: 128] ),
.m_axi_rlast ( gAXIM_s_rlast[MSDHC*1 +: 1] ),
.m_axi_rresp ( gAXIM_s_rresp[MSDHC*2 +: 2] ),
.m_axi_rready ( gAXIM_s_rready[MSDHC*1 +: 1] ),
.sd_clk_hi ( sd_clk_hi ),
.sd_clk_lo ( sd_clk_lo ),
.sd_cmd_i ( sd_cmd_i ),
.sd_cmd_o ( sd_cmd_o ),
.sd_cmd_oe ( sd_cmd_oe ),
.sd_dat_i ( sd_dat_i ),
.sd_dat_o ( sd_dat_o ),
.sd_dat_oe ( sd_dat_oe_i )
);
assign m_eth_rx_tdest = 4'h0;
assign phy_rst = phy_sw_rst;
assign tse_pll_ok = pll_tse_locked & pll_peripheral_locked;
tseCore u_tseCore (
.io_peripheralClk ( io_peripheralClk ),
.io_peripheralReset ( io_peripheralReset ),
.io_tseClk ( io_tseClk ),
.pll_locked ( tse_pll_ok ),
.phy_sw_rst ( phy_sw_rst ),
.mac_ext_rst ( mac_ext_rst ),
.dma_rx_rst ( dma_rx_rst ),
.dma_tx_rst ( dma_tx_rst ),
.dma_tx_descriptorUpdate ( dma_tx_descriptorUpdate ),
.dma_interrupts ( dma_interrupts ),
.eth_speed ( eth_speed ),
.rgmii_txd_HI ( rgmii_txd_HI ),
.rgmii_txd_LO ( rgmii_txd_LO ),
.rgmii_tx_ctl_HI ( rgmii_tx_ctl_HI ),
.rgmii_tx_ctl_LO ( rgmii_tx_ctl_LO ),
.rgmii_txc_HI ( rgmii_txc_HI ),
.rgmii_txc_LO ( rgmii_txc_LO ),
.rgmii_rxd_HI ( rgmii_rxd_HI ),
.rgmii_rxd_LO ( rgmii_rxd_LO ),
.rgmii_rx_ctl_HI ( rgmii_rx_ctl_HI ),
.rgmii_rx_ctl_LO ( rgmii_rx_ctl_LO ),
`ifdef ETH_1000MBPS
.rgmii_rxc ( rgmii_rxc ),
`else
.rgmii_rxc ( rgmii_rxc_slow ),
`endif
.phy_mdi ( phy_mdi ),
.phy_mdo ( phy_mdo ),
.phy_mdo_en ( phy_mdo_en ),
.phy_mdc ( phy_mdc ),
.s_axi_awaddr ( gAXIS_m_awaddr[TSE*32 +: 32] ),
.s_axi_awvalid ( gAXIS_m_awvalid[TSE*1 +: 1] ),
.s_axi_awready ( gAXIS_m_awready[TSE*1 +: 1] ),
.s_axi_wdata ( gAXIS_m_wdata[TSE*32 +: 32] ),
.s_axi_wstrb ( gAXIS_m_wstrb[TSE*4 +: 4] ),
.s_axi_wlast ( gAXIS_m_wlast[TSE*1 +: 1] ),
.s_axi_wvalid ( gAXIS_m_wvalid[TSE*1 +: 1] ),
.s_axi_wready ( gAXIS_m_wready[TSE*1 +: 1] ),
.s_axi_bresp ( gAXIS_m_bresp[TSE*2 +: 2] ),
.s_axi_bvalid ( gAXIS_m_bvalid[TSE*1 +: 1] ),
.s_axi_bready ( gAXIS_m_bready[TSE*1 +: 1] ),
.s_axi_araddr ( gAXIS_m_araddr[TSE*32 +: 32] ),
.s_axi_arvalid ( gAXIS_m_arvalid[TSE*1 +: 1] ),
.s_axi_arready ( gAXIS_m_arready[TSE*1 +: 1] ),
.s_axi_rresp ( gAXIS_m_rresp[TSE*2 +: 2] ),
.s_axi_rdata ( gAXIS_m_rdata[TSE*32 +: 32] ),
.s_axi_rlast ( gAXIS_m_rlast[TSE*1 +: 1] ),
.s_axi_rvalid ( gAXIS_m_rvalid[TSE*1 +: 1] ),
.s_axi_rready ( gAXIS_m_rready[TSE*1 +: 1] ),
.s_eth_tx_tvalid ( s_eth_tx_tvalid ),
.s_eth_tx_tready ( s_eth_tx_tready ),
.s_eth_tx_tdata ( s_eth_tx_tdata ),
.s_eth_tx_tkeep ( s_eth_tx_tkeep ),
.s_eth_tx_tdest ( s_eth_tx_tdest ),
.s_eth_tx_tlast ( s_eth_tx_tlast ),
.m_eth_rx_tvalid ( m_eth_rx_tvalid ),
.m_eth_rx_tready ( m_eth_rx_tready ),
.m_eth_rx_tdata ( m_eth_rx_tdata ),
.m_eth_rx_tstrb ( m_eth_rx_tstrb ),
.m_eth_rx_tlast ( m_eth_rx_tlast )
);
assign userInterruptG = dma_interrupts[0];
assign userInterruptH = dma_interrupts[1];
gDMA u_gDMA (
.clk ( io_ddrMasters_0_clk ),
.reset ( io_ddrMasters_0_reset ),
.ctrl_clk ( io_peripheralClk ),
.ctrl_reset ( io_peripheralReset ),
.ctrl_PADDR ( dma_apb3_paddr ),
.ctrl_PREADY ( dma_apb3_pready ),
.ctrl_PENABLE ( dma_apb3_penable ),
.ctrl_PSEL ( dma_apb3_psel ),
.ctrl_PWRITE ( dma_apb3_pwrite ),
.ctrl_PWDATA ( dma_apb3_pwdata ),
.ctrl_PRDATA ( dma_apb3_prdata ),
.ctrl_PSLVERROR ( dma_apb3_pslverror ),
.ctrl_interrupts ( dma_interrupts ),
.read_arvalid ( gAXIM_s_arvalid[MTSE*1 +: 1] ),
.read_araddr ( gAXIM_s_araddr[MTSE*32 +: 32] ),
.read_arready ( gAXIM_s_arready[MTSE*1 +: 1] ),
.read_arregion ( gAXIM_s_arregion[MTSE*4 +: 4] ),
.read_arlen ( gAXIM_s_arlen[MTSE*8 +: 8] ),
.read_arsize ( gAXIM_s_arsize[MTSE*3 +: 3] ),
.read_arburst ( gAXIM_s_arburst[MTSE*2 +: 2] ),
.read_arlock ( gAXIM_s_arlock[MTSE*2 +: 2] ),
.read_arcache ( gAXIM_s_arcache[MTSE*4 +: 4] ),
.read_arqos ( gAXIM_s_arqos[MTSE*4 +: 4] ),
.read_arprot ( gAXIM_s_arprot[MTSE*4 +: 4] ),
.read_rready ( gAXIM_s_rready[MTSE*1 +: 1] ),
.read_rvalid ( gAXIM_s_rvalid[MTSE*1 +: 1] ),
.read_rdata ( gAXIM_s_rdata[MTSE*128 +: 128] ),
.read_rlast ( gAXIM_s_rlast[MTSE*1 +: 1] ),
.read_rresp ( gAXIM_s_rresp[MTSE*2 +: 2] ),
.write_awvalid ( gAXIM_s_awvalid[MTSE*1 +: 1] ),
.write_awready ( gAXIM_s_awready[MTSE*1 +: 1] ),
.write_awaddr ( gAXIM_s_awaddr[MTSE*32 +: 32] ),
.write_awregion ( gAXIM_s_awregion[MTSE*4 +: 4] ),
.write_awlen ( gAXIM_s_awlen[MTSE*8 +: 8] ),
.write_awsize ( gAXIM_s_awsize[MTSE*3 +: 3] ),
.write_awburst ( gAXIM_s_awburst[MTSE*2 +: 2] ),
.write_awlock ( gAXIM_s_awlock[MTSE*2 +: 2] ),
.write_awcache ( gAXIM_s_awcache[MTSE*4 +: 4] ),
.write_awqos ( gAXIM_s_awqos[MTSE*4 +: 4] ),
.write_awprot ( gAXIM_s_awprot[MTSE*4 +: 4] ),
.write_wvalid ( gAXIM_s_wvalid[MTSE*1 +: 1] ),
.write_wready ( gAXIM_s_wready[MTSE*1 +: 1] ),
.write_wdata ( gAXIM_s_wdata[MTSE*128 +: 128] ),
.write_wstrb ( gAXIM_s_wstrb[MTSE*16 +: 16] ),
.write_wlast ( gAXIM_s_wlast[MTSE*1 +: 1] ),
.write_bvalid ( gAXIM_s_bvalid[MTSE*1 +: 1] ),
.write_bready ( gAXIM_s_bready[MTSE*1 +: 1] ),
.write_bresp ( gAXIM_s_bresp[MTSE*2 +: 2] ),
.dat1_o_clk ( io_tseClk ),
.dat1_o_reset ( mac_ext_rst | dma_tx_rst),
.dat1_o_tvalid ( s_eth_tx_tvalid ),
.dat1_o_tready ( s_eth_tx_tready ),
.dat1_o_tdata ( s_eth_tx_tdata ),
.dat1_o_tkeep ( s_eth_tx_tkeep ),
.dat1_o_tdest ( s_eth_tx_tdest ),
.dat1_o_tlast ( s_eth_tx_tlast ),
`ifdef ETH_1000MBPS
.dat0_i_clk ( rgmii_rxc ),
`else
.dat0_i_clk ( rgmii_rxc_slow ),
`endif
.dat0_i_reset ( mac_ext_rst | dma_rx_rst ),
.dat0_i_tvalid ( m_eth_rx_tvalid ),
.dat0_i_tready ( m_eth_rx_tready ),
.dat0_i_tdata ( m_eth_rx_tdata ),
.dat0_i_tkeep ( 1'b1),
.dat0_i_tdest ( m_eth_rx_tdest ),
.dat0_i_tlast ( m_eth_rx_tlast ),
.io_1_descriptorUpdate ( ),
.io_0_descriptorUpdate (dma_tx_descriptorUpdate)
);
////////////////////////////////////////////////////////////////////////////
custom_instruction_tea cpu0_custom_instruction_tea_inst(
.clk(io_cfuClk),
.reset(io_cfuReset),
.cmd_valid(cpu0_customInstruction_cmd_valid),
.cmd_ready(cpu0_customInstruction_cmd_ready),
.cmd_function_id(cpu0_customInstruction_function_id),
.cmd_inputs_0(cpu0_customInstruction_inputs_0),
.cmd_inputs_1(cpu0_customInstruction_inputs_1),
.rsp_valid(cpu0_customInstruction_rsp_valid),
.rsp_ready(cpu0_customInstruction_rsp_ready),
.rsp_outputs_0(cpu0_customInstruction_outputs_0));
custom_instruction_tea cpu1_custom_instruction_tea_inst(
.clk(io_cfuClk),
.reset(io_cfuReset),
.cmd_valid(cpu1_customInstruction_cmd_valid),
.cmd_ready(cpu1_customInstruction_cmd_ready),
.cmd_function_id(cpu1_customInstruction_function_id),
.cmd_inputs_0(cpu1_customInstruction_inputs_0),
.cmd_inputs_1(cpu1_customInstruction_inputs_1),
.rsp_valid(cpu1_customInstruction_rsp_valid),
.rsp_ready(cpu1_customInstruction_rsp_ready),
.rsp_outputs_0(cpu1_customInstruction_outputs_0));
custom_instruction_tea cpu2_custom_instruction_tea_inst(
.clk(io_cfuClk),
.reset(io_cfuReset),
.cmd_valid(cpu2_customInstruction_cmd_valid),
.cmd_ready(cpu2_customInstruction_cmd_ready),
.cmd_function_id(cpu2_customInstruction_function_id),
.cmd_inputs_0(cpu2_customInstruction_inputs_0),
.cmd_inputs_1(cpu2_customInstruction_inputs_1),
.rsp_valid(cpu2_customInstruction_rsp_valid),
.rsp_ready(cpu2_customInstruction_rsp_ready),
.rsp_outputs_0(cpu2_customInstruction_outputs_0));
custom_instruction_tea cpu3_custom_instruction_tea_inst(
.clk(io_cfuClk),
.reset(io_cfuReset),
.cmd_valid(cpu3_customInstruction_cmd_valid),
.cmd_ready(cpu3_customInstruction_cmd_ready),
.cmd_function_id(cpu3_customInstruction_function_id),
.cmd_inputs_0(cpu3_customInstruction_inputs_0),
.cmd_inputs_1(cpu3_customInstruction_inputs_1),
.rsp_valid(cpu3_customInstruction_rsp_valid),
.rsp_ready(cpu3_customInstruction_rsp_ready),
.rsp_outputs_0(cpu3_customInstruction_outputs_0));
assign io_asyncReset = io_asyncReset_soc | watchdog_reset;
//axi4 bridge to various I/O
EfxSapphireHpSoc_slb u_top_peripherals(
.io_apbSlave_0_PADDR ( dma_apb3_paddr ),
.io_apbSlave_0_PENABLE ( dma_apb3_penable ),
.io_apbSlave_0_PRDATA ( dma_apb3_prdata ),
.io_apbSlave_0_PREADY ( dma_apb3_pready ),
.io_apbSlave_0_PSEL ( dma_apb3_psel ),
.io_apbSlave_0_PSLVERROR ( dma_apb3_pslverror ),
.io_apbSlave_0_PWDATA ( dma_apb3_pwdata ),
.io_apbSlave_0_PWRITE ( dma_apb3_pwrite ),
.system_spi_0_io_sclk_write ( system_spi_0_io_sclk_write ),
.system_spi_0_io_data_0_writeEnable ( system_spi_0_io_data_0_writeEnable ),
.system_spi_0_io_data_0_read ( system_spi_0_io_data_0_read ),
.system_spi_0_io_data_0_write ( system_spi_0_io_data_0_write ),
.system_spi_0_io_data_1_writeEnable ( system_spi_0_io_data_1_writeEnable ),
.system_spi_0_io_data_1_read ( system_spi_0_io_data_1_read ),
.system_spi_0_io_data_1_write ( system_spi_0_io_data_1_write ),
.system_spi_0_io_data_2_writeEnable ( system_spi_0_io_data_2_writeEnable ),
.system_spi_0_io_data_2_read ( system_spi_0_io_data_2_read ),
.system_spi_0_io_data_2_write ( system_spi_0_io_data_2_write ),
.system_spi_0_io_data_3_writeEnable ( system_spi_0_io_data_3_writeEnable ),
.system_spi_0_io_data_3_read ( system_spi_0_io_data_3_read ),
.system_spi_0_io_data_3_write ( system_spi_0_io_data_3_write ),
.system_spi_0_io_ss ( system_spi_0_io_ss ),
.system_uart_0_io_txd ( system_uart_0_io_txd ),
.system_uart_0_io_rxd ( system_uart_0_io_rxd ),
.system_i2c_0_io_sda_writeEnable ( system_i2c_0_io_sda_writeEnable ),
.system_i2c_0_io_sda_write ( system_i2c_0_io_sda_write ),
.system_i2c_0_io_sda_read ( system_i2c_0_io_sda_read ),
.system_i2c_0_io_scl_writeEnable ( system_i2c_0_io_scl_writeEnable ),
.system_i2c_0_io_scl_write ( system_i2c_0_io_scl_write ),
.system_i2c_0_io_scl_read ( system_i2c_0_io_scl_read ),
.jtagCtrl_tdi ( jtagCtrl_tdi ),
.jtagCtrl_tdo ( jtagCtrl_tdo ),
.jtagCtrl_enable ( jtagCtrl_enable ),
.jtagCtrl_capture ( jtagCtrl_capture ),
.jtagCtrl_shift ( jtagCtrl_shift ),
.jtagCtrl_update ( jtagCtrl_update ),
.jtagCtrl_reset ( jtagCtrl_reset ),
.ut_jtagCtrl_tdi ( ut_jtagCtrl_tdi ),
.ut_jtagCtrl_tdo ( ut_jtagCtrl_tdo ),
.ut_jtagCtrl_enable ( ut_jtagCtrl_enable ),
.ut_jtagCtrl_capture ( ut_jtagCtrl_capture ),
.ut_jtagCtrl_shift ( ut_jtagCtrl_shift ),
.ut_jtagCtrl_update ( ut_jtagCtrl_update ),
.ut_jtagCtrl_reset ( ut_jtagCtrl_reset ),
.system_gpio_0_io_read ( system_gpio_0_io_read ),
.system_gpio_0_io_write ( system_gpio_0_io_write ),
.system_gpio_0_io_writeEnable ( system_gpio_0_io_writeEnable ),
.system_watchdog_hardPanic_reset ( watchdog_reset ),
.userInterruptA ( userInterruptA ),
.userInterruptB ( userInterruptB ),
.userInterruptC ( userInterruptC ),
.userInterruptD ( userInterruptD ),
.userInterruptE ( userInterruptE ),
.userInterruptF ( userInterruptF ),
.axiA_awvalid ( gAXIS_m_awvalid[SLB*1 +: 1] ),
.axiA_awready ( gAXIS_m_awready[SLB*1 +: 1] ),
.axiA_awaddr ( gAXIS_m_awaddr[SLB*32 +: 32] ),
.axiA_awlen ( gAXIS_m_awlen[SLB*8 +: 8] ),
.axiA_awburst ( gAXIS_m_awburst[SLB*2 +: 2] ),
.axiA_awsize ( gAXIS_m_awsize[SLB*3 +: 3] ),
.axiA_awcache ( gAXIS_m_awcache[SLB*4 +: 4] ),
.axiA_awprot ( gAXIS_m_awprot[SLB*3 +: 3] ),
.axiA_wvalid ( gAXIS_m_wvalid[SLB*1 +: 1] ),
.axiA_wready ( gAXIS_m_wready[SLB*1 +: 1] ),
.axiA_wdata ( gAXIS_m_wdata[SLB*32 +: 32] ),
.axiA_wstrb ( gAXIS_m_wstrb[SLB*4 +: 4] ),
.axiA_wlast ( gAXIS_m_wlast[SLB*1 +: 1] ),
.axiA_bvalid ( gAXIS_m_bvalid[SLB*1 +: 1] ),
.axiA_bready ( gAXIS_m_bready[SLB*1 +: 1] ),
.axiA_bresp ( gAXIS_m_bresp[SLB*2 +: 2] ),
.axiA_arvalid ( gAXIS_m_arvalid[SLB*1 +: 1] ),
.axiA_arready ( gAXIS_m_arready[SLB*1 +: 1] ),
.axiA_araddr ( gAXIS_m_araddr[SLB*32 +: 32] ),
.axiA_arlen ( gAXIS_m_arlen[SLB*8 +: 8] ),
.axiA_arburst ( gAXIS_m_arburst[SLB*2 +: 2]),
.axiA_arsize ( gAXIS_m_arsize[SLB*3 +: 3] ),
.axiA_arcache ( gAXIS_m_arcache[SLB*4 +: 4] ),
.axiA_arprot ( gAXIS_m_arprot[SLB*3 +: 3] ),
.axiA_rvalid ( gAXIS_m_rvalid[SLB*1 +: 1] ),
.axiA_rready ( gAXIS_m_rready[SLB*1 +: 1] ),
.axiA_rdata ( gAXIS_m_rdata[SLB*32 +: 32] ),
.axiA_rresp ( gAXIS_m_rresp[SLB*2 +: 2] ),
.axiA_rlast ( gAXIS_m_rlast[SLB*1 +: 1] ),
.axiAInterrupt ( axiAInterrupt ),
.cfg_done ( cfg_done ),
.cfg_start ( cfg_start ),
.cfg_sel ( cfg_sel ),
.cfg_reset ( cfg_reset ),
.io_peripheralClk ( io_peripheralClk ),
.io_peripheralReset ( io_peripheralReset ),
.io_asyncReset ( io_asyncReset_soc ),
.io_gpio_sw_n ( io_gpio_sw_n ),
.pll_peripheral_locked ( pll_peripheral_locked ),
.pll_system_locked ( pll_system_locked )
);
endmodule

996
Ti375C529_devkit/source/tseCore.v Normal file
View File

@@ -0,0 +1,996 @@
`timescale 1 ns / 1 ns
module tseCore #(
parameter ADDR_WIDTH = 10
) (
input io_peripheralClk,
input io_peripheralReset,
input io_tseClk,
input pll_locked,
output phy_sw_rst,
output mac_ext_rst,
output dma_rx_rst,
output dma_tx_rst,
input dma_tx_descriptorUpdate,
output [1:0] dma_interrupts,
output [2:0] eth_speed,
// MAC RGMII Interface
output [3:0] rgmii_txd_HI,
output [3:0] rgmii_txd_LO,
output rgmii_tx_ctl_HI,
output rgmii_tx_ctl_LO,
output rgmii_txc_HI,
output rgmii_txc_LO,
input [3:0] rgmii_rxd_HI,
input [3:0] rgmii_rxd_LO,
input rgmii_rx_ctl_HI,
input rgmii_rx_ctl_LO,
input rgmii_rxc,
// PHY MDIO Interface
input phy_mdi,
output phy_mdo,
output phy_mdo_en,
output phy_mdc,
// AXI CSR
input [31:0] s_axi_awaddr,
input s_axi_awvalid,
output s_axi_awready,
input [31:0] s_axi_wdata,
input [3:0] s_axi_wstrb,
output s_axi_wlast,
input s_axi_wvalid,
output s_axi_wready,
output [1:0] s_axi_bresp,
output s_axi_bvalid,
input s_axi_bready,
input [31:0] s_axi_araddr,
input s_axi_arvalid,
output s_axi_arready,
output [1:0] s_axi_rresp,
output [31:0] s_axi_rdata,
output s_axi_rlast,
output s_axi_rvalid,
input s_axi_rready,
// MAC Stream
input s_eth_tx_tvalid,
output s_eth_tx_tready,
input [7:0] s_eth_tx_tdata,
input [0:0] s_eth_tx_tkeep,
input [3:0] s_eth_tx_tdest,
input s_eth_tx_tlast,
output m_eth_rx_tvalid,
input m_eth_rx_tready,
output [7:0] m_eth_rx_tdata,
output [0:0] m_eth_rx_tstrb,
output m_eth_rx_tlast
);
////////////////////////////////////////////////////////////////////////////////////////////
localparam TSE_DEV = 2;
localparam MAC = 0;
localparam CMN = 1;
// Switch between MAC and CMN
wire [(TSE_DEV*32)-1:0] gTSE_m_awaddr;
wire [(TSE_DEV*8)-1:0] gTSE_m_awlen;
wire [(TSE_DEV*3)-1:0] gTSE_m_awsize;
wire [(TSE_DEV*2)-1:0] gTSE_m_awburst;
wire [(TSE_DEV*2)-1:0] gTSE_m_awlock;
wire [TSE_DEV-1:0] gTSE_m_awvalid;
wire [TSE_DEV-1:0] gTSE_m_awready;
wire [(TSE_DEV*32)-1:0] gTSE_m_wdata;
wire [(TSE_DEV*4)-1:0] gTSE_m_wstrb;
wire [TSE_DEV-1:0] gTSE_m_wvalid;
wire [TSE_DEV-1:0] gTSE_m_wlast;
wire [TSE_DEV-1:0] gTSE_m_wready;
wire [(TSE_DEV*2)-1:0] gTSE_m_bresp;
wire [TSE_DEV-1:0] gTSE_m_bvalid;
wire [TSE_DEV-1:0] gTSE_m_bready;
wire [(TSE_DEV*32)-1:0] gTSE_m_araddr;
wire [(TSE_DEV*8)-1:0] gTSE_m_arlen;
wire [(TSE_DEV*3)-1:0] gTSE_m_arsize;
wire [(TSE_DEV*2)-1:0] gTSE_m_arburst;
wire [(TSE_DEV*2)-1:0] gTSE_m_arlock;
wire [TSE_DEV-1:0] gTSE_m_arvalid;
wire [TSE_DEV-1:0] gTSE_m_arready;
wire [(TSE_DEV*32)-1:0] gTSE_m_rdata;
wire [(TSE_DEV*2)-1:0] gTSE_m_rresp;
wire [TSE_DEV-1:0] gTSE_m_rlast;
wire [TSE_DEV-1:0] gTSE_m_rvalid;
wire [TSE_DEV-1:0] gTSE_m_rready;
// clock reset
wire mac_sw_rst;
wire proto_reset;
wire mac_ext_srst;
wire rx_axis_clk;
wire tx_axis_clk;
// Stream control
wire m_eth_tx_tvalid;
wire m_eth_tx_tready;
wire [7:0] m_eth_tx_tdata;
wire [3:0] m_eth_tx_tdest;
wire m_eth_tx_tlast;
wire s_eth_rx_tvalid;
wire s_eth_rx_tready;
wire [7:0] s_eth_rx_tdata;
wire [0:0] s_eth_rx_tkeep;
wire [3:0] s_eth_rx_tdest;
wire s_eth_rx_tlast;
////////////////////////////////////////////////////////////////////////////////////////////
assign mac_ext_rst = ~pll_locked;
assign rx_axis_clk = io_tseClk;
assign tx_axis_clk = io_tseClk;
reset_ctrl #(
.NUM_RST (2),
.CYCLE (2),
.IN_RST_ACTIVE (2'b11),
.OUT_RST_ACTIVE (2'b11)
) inst_reset_ctrl (
.i_arst ({mac_sw_rst, mac_ext_rst}),
.i_clk ({2{io_tseClk}}),
.o_srst ({proto_reset, mac_ext_srst})
);
gTSE_1to2_switch u_gTSE_1to2_switch
(
.rst_n ( ~io_peripheralReset ),
.clk ( io_peripheralClk ),
.s_axi_awvalid ( s_axi_awvalid ),
.s_axi_awready ( s_axi_awready ),
.s_axi_awaddr ( {16'd0, s_axi_awaddr[15:0]} ),
.s_axi_awlock ( 2'b00 ),
.s_axi_wready ( s_axi_wready ),
.s_axi_wvalid ( s_axi_wvalid ),
.s_axi_wstrb ( s_axi_wstrb ),
.s_axi_wdata ( s_axi_wdata ),
.s_axi_wlast ( s_axi_wlast ),
.s_axi_wid ( 8'h00 ),
.s_axi_bvalid ( s_axi_bvalid ),
.s_axi_bready ( s_axi_bready ),
.s_axi_bid ( ),
.s_axi_bresp ( s_axi_bresp ),
.s_axi_arvalid ( s_axi_arvalid ),
.s_axi_arready ( s_axi_arready ),
.s_axi_araddr ( {16'd0, s_axi_araddr[15:0]} ),
.s_axi_arlock ( 2'b00 ),
.s_axi_rvalid ( s_axi_rvalid ),
.s_axi_rready ( s_axi_rready ),
.s_axi_rid ( ),
.s_axi_rdata ( s_axi_rdata ),
.s_axi_rlast ( ),
.s_axi_rresp ( s_axi_rresp ),
.m_axi_awvalid ( gTSE_m_awvalid ),
.m_axi_awready ( gTSE_m_awready ),
.m_axi_awaddr ( gTSE_m_awaddr ),
.m_axi_awlock ( ),
.m_axi_wvalid ( gTSE_m_wvalid ),
.m_axi_wready ( gTSE_m_wready ),
.m_axi_wlast ( gTSE_m_wlast ),
.m_axi_wstrb ( gTSE_m_wstrb ),
.m_axi_wdata ( gTSE_m_wdata ),
.m_axi_bvalid ( gTSE_m_bvalid ),
.m_axi_bready ( gTSE_m_bready ),
.m_axi_bresp ( gTSE_m_bresp ),
.m_axi_bid ( {TSE_DEV{8'h00}} ),
.m_axi_arvalid ( gTSE_m_arvalid ),
.m_axi_araddr ( gTSE_m_araddr ),
.m_axi_arlock ( ),
.m_axi_arready ( gTSE_m_arready ),
.m_axi_rvalid ( gTSE_m_rvalid ),
.m_axi_rready ( gTSE_m_rready ),
.m_axi_rid ( {TSE_DEV{8'h00}} ),
.m_axi_rdata ( gTSE_m_rdata ),
.m_axi_rlast ( gTSE_m_rlast ),
.m_axi_rresp ( gTSE_m_rresp )
);
assign s_axi_rlast = 1'b1;
assign gTSE_m_wlast = 2'b11;
assign gTSE_m_rlast = 2'b11;
gTSE_streamControl #(
.ADDR_WIDTH (ADDR_WIDTH)
) u_gTSE_streamControl (
.s_axi_aclk ( io_peripheralClk ),
.s_axi_aresetn ( ~io_peripheralReset ),
.s_axi_awaddr ( gTSE_m_awaddr[CMN*32 +: ADDR_WIDTH] ),
.s_axi_awvalid ( gTSE_m_awvalid[CMN*1 +: 1] ),
.s_axi_awready ( gTSE_m_awready[CMN*1 +: 1] ),
.s_axi_wdata ( gTSE_m_wdata[CMN*32 +: 32] ),
.s_axi_wvalid ( gTSE_m_wvalid[CMN*1 +: 1] ),
.s_axi_wready ( gTSE_m_wready[CMN*1 +: 1] ),
.s_axi_bvalid ( gTSE_m_bvalid[CMN*1 +: 1] ),
.s_axi_bready ( gTSE_m_bready[CMN*1 +: 1 ]),
.s_axi_bresp ( gTSE_m_bresp[CMN*2 +: 2] ),
.s_axi_araddr ( gTSE_m_araddr[CMN*32 +: ADDR_WIDTH] ),
.s_axi_arvalid ( gTSE_m_arvalid[CMN*1 +: 1] ),
.s_axi_arready ( gTSE_m_arready[CMN*1 +: 1] ),
.s_axi_rdata ( gTSE_m_rdata[CMN*32 +: 32] ),
.s_axi_rvalid ( gTSE_m_rvalid[CMN*1 +: 1] ),
.s_axi_rready ( gTSE_m_rready[CMN*1 +: 1] ),
.s_axi_rresp ( gTSE_m_rresp[CMN*2 +: 2] ),
.mac_ext_rst ( mac_ext_rst || mac_sw_rst ),
.s_eth_tx_clk ( tx_axis_clk ),
.s_eth_tx_tvalid ( s_eth_tx_tvalid ),
.s_eth_tx_tready ( s_eth_tx_tready ),
.s_eth_tx_tdata ( s_eth_tx_tdata ),
.s_eth_tx_tkeep ( s_eth_tx_tkeep ),
.s_eth_tx_tdest ( s_eth_tx_tdest ),
.s_eth_tx_tlast ( s_eth_tx_tlast ),
.m_eth_tx_tvalid ( m_eth_tx_tvalid ),
.m_eth_tx_tready ( m_eth_tx_tready ),
.m_eth_tx_tdata ( m_eth_tx_tdata ),
.m_eth_tx_tdest ( m_eth_tx_tdest ),
.m_eth_tx_tlast ( m_eth_tx_tlast ),
.mac_sw_rst ( mac_sw_rst ),
.phy_sw_rst ( phy_sw_rst ),
.dma_rx_rst ( dma_rx_rst ),
.dma_tx_rst ( dma_tx_rst ),
.error ( ),
.dma_descriptor_update (dma_tx_descriptorUpdate)
);
wire lso_eth_tx_tvalid;
wire lso_eth_tx_tready;
wire [7:0] lso_eth_tx_tdata;
wire lso_eth_tx_tlast;
MacTxLso lso0
(
.io_input_valid(m_eth_tx_tvalid),
.io_input_ready(m_eth_tx_tready),
.io_input_payload_last(m_eth_tx_tlast),
.io_input_payload_fragment_data(m_eth_tx_tdata),
.io_output_valid(lso_eth_tx_tvalid),
.io_output_ready(lso_eth_tx_tready),
.io_output_payload_last(lso_eth_tx_tlast),
.io_output_payload_fragment_data(lso_eth_tx_tdata),
.clk(tx_axis_clk),
.reset(mac_ext_srst)
);
wire rx0_eth_rx_tvalid;
wire rx0_eth_rx_tready;
wire [7:0] rx0_eth_rx_tdata;
wire rx0_eth_rx_tlast;
MacRxCheckSumChecker rx0
(
.io_input_valid(rx0_eth_rx_tvalid),
.io_input_ready(rx0_eth_rx_tready),
.io_input_payload_last(rx0_eth_rx_tlast),
.io_input_payload_fragment_error(1'b0),
.io_input_payload_fragment_data(rx0_eth_rx_tdata),
.io_output_valid(s_eth_rx_tvalid),
.io_output_ready(s_eth_rx_tready),
.io_output_payload_last(s_eth_rx_tlast),
.io_output_payload_fragment_error(),
.io_output_payload_fragment_data(s_eth_rx_tdata),
.clk(rgmii_rxc),
.reset(mac_ext_srst)
);
gTSE u_gTSE (
.mac_reset ( mac_ext_srst ),
.proto_reset ( mac_ext_srst || proto_reset ),
.tx_mac_aclk ( io_tseClk ),
.rx_mac_aclk (),
.eth_speed ( eth_speed ),
// MAC RX
.rx_axis_clk ( rgmii_rxc ),
.rx_axis_mac_tdata ( rx0_eth_rx_tdata ),
.rx_axis_mac_tvalid ( rx0_eth_rx_tvalid ),
.rx_axis_mac_tstrb ( s_eth_rx_tstrb ),
.rx_axis_mac_tlast ( rx0_eth_rx_tlast ),
.rx_axis_mac_tuser ( ),
.rx_axis_mac_tready ( rx0_eth_rx_tready ),
// MAC TX
.tx_axis_clk ( tx_axis_clk ),
.tx_axis_mac_tdata ( lso_eth_tx_tdata ),
.tx_axis_mac_tvalid ( lso_eth_tx_tvalid ),
.tx_axis_mac_tstrb ( 1'b1 ),
.tx_axis_mac_tlast ( lso_eth_tx_tlast ),
.tx_axis_mac_tuser ( 1'b0 ),
.tx_axis_mac_tready ( lso_eth_tx_tready ),
// AXI CSR
.s_axi_aclk ( io_peripheralClk ),
.s_axi_awaddr ( gTSE_m_awaddr[MAC*32 +: ADDR_WIDTH] ),
.s_axi_awvalid ( gTSE_m_awvalid[MAC*1 +:1 ] ),
.s_axi_awready ( gTSE_m_awready[MAC*1 +: 1] ),
.s_axi_wdata ( gTSE_m_wdata[MAC*32 +: 32] ),
.s_axi_wvalid ( gTSE_m_wvalid[MAC*1 +: 1] ),
.s_axi_wready ( gTSE_m_wready[MAC*1 +: 1] ),
.s_axi_bresp ( gTSE_m_bresp[MAC*2 +: 2] ),
.s_axi_bvalid ( gTSE_m_bvalid[MAC*1 +: 1] ),
.s_axi_bready ( gTSE_m_bready[MAC*1 +: 1] ),
.s_axi_araddr ( gTSE_m_araddr[MAC*32 +: ADDR_WIDTH] ),
.s_axi_arvalid ( gTSE_m_arvalid[MAC*1 +: 1] ),
.s_axi_arready ( gTSE_m_arready[MAC*1 +: 1] ),
.s_axi_rresp ( gTSE_m_rresp[MAC*2 +: 2] ),
.s_axi_rdata ( gTSE_m_rdata[MAC*32 +: 32] ),
.s_axi_rvalid ( gTSE_m_rvalid[MAC*1 +: 1] ),
.s_axi_rready ( gTSE_m_rready[MAC*1 +: 1] ),
// RGMII
.rgmii_txd_HI ( rgmii_txd_HI ),
.rgmii_txd_LO ( rgmii_txd_LO ),
.rgmii_tx_ctl_HI ( rgmii_tx_ctl_HI ),
.rgmii_tx_ctl_LO ( rgmii_tx_ctl_LO ),
.rgmii_txc_HI ( rgmii_txc_HI ),
.rgmii_txc_LO ( rgmii_txc_LO ),
.rgmii_rxd_HI ( rgmii_rxd_HI ),
.rgmii_rxd_LO ( rgmii_rxd_LO ),
.rgmii_rx_ctl_HI ( rgmii_rx_ctl_HI ),
.rgmii_rx_ctl_LO ( rgmii_rx_ctl_LO ),
.rgmii_rxc ( rgmii_rxc ),
// MDIO
.Mdo ( phy_mdo ),
.MdoEn ( phy_mdo_en ),
.Mdi ( phy_mdi ),
.Mdc ( phy_mdc )
);
assign m_eth_rx_tvalid = s_eth_rx_tvalid;
assign m_eth_rx_tdata = s_eth_rx_tdata;
assign m_eth_rx_tkeep = 1'b1;
assign m_eth_rx_tlast = s_eth_rx_tlast;
assign s_eth_rx_tready = m_eth_rx_tready;
endmodule
module gTSE_streamControl#(
parameter ADDR_WIDTH = 10,
parameter NUM_REG = 5,
parameter NUM_FRAME = 10,
parameter MAC_RX_CLK_FREQ = 100,
parameter COALESCE_US = 4000
)
(
input s_axi_aclk, //AXI Bus Clock.
input s_axi_aresetn, //AXI Reset. Active-Low.
input [ADDR_WIDTH-1:0] s_axi_awaddr, //Write Address. byte address.
input s_axi_awvalid, //Write address valid.
output reg s_axi_awready, //Write address ready.
input [31:0] s_axi_wdata, //Write data bus.
input s_axi_wvalid, //Write valid.
output reg s_axi_wready, //Write ready.
output wire [1:0] s_axi_bresp, //Write response.
output reg s_axi_bvalid, //Write response valid.
input s_axi_bready, //Response ready.
input [ADDR_WIDTH-1:0] s_axi_araddr, //Read address. byte address.
input s_axi_arvalid, //Read address valid.
output reg s_axi_arready, //Read address ready.
output wire [1:0] s_axi_rresp, //Read response.
output reg [31:0] s_axi_rdata, //Read data.
output reg s_axi_rvalid, //Read valid.
input s_axi_rready, //Read ready.
input s_eth_tx_clk,
input s_eth_tx_tvalid,
output s_eth_tx_tready,
input [7:0] s_eth_tx_tdata,
input [0:0] s_eth_tx_tkeep,
input [3:0] s_eth_tx_tdest,
input s_eth_tx_tlast,
output m_eth_tx_tvalid,
input m_eth_tx_tready,
output [7:0] m_eth_tx_tdata,
output [3:0] m_eth_tx_tdest,
output m_eth_tx_tlast,
input mac_ext_rst,
output reg mac_sw_rst,
output reg phy_sw_rst,
output reg dma_rx_rst,
output reg dma_tx_rst,
output reg error,
input dma_descriptor_update
);
// Parameter Define
localparam DATA_DEPTH = NUM_FRAME*1540;
localparam SIZE_DEPTH = NUM_FRAME*5;
localparam DATA_DEPTH_WID = $clog2(DATA_DEPTH);
localparam SIZE_DEPTH_WID = $clog2(SIZE_DEPTH);
localparam COALESCE_CNT = (COALESCE_US * MAC_RX_CLK_FREQ);
// Register Define
// Cfg Space Registers
// Other Registers
reg [ADDR_WIDTH-3:0] loc_waddr;
reg loc_waddr_vld;
reg [31:0] loc_wdata;
reg loc_wdata_vld;
reg [ADDR_WIDTH-3:0] loc_raddr;
reg loc_raddr_vld;
// Wire Define
wire loc_wrdy;
wire loc_rrdy;
wire w_eth_mac_rst;
wire [9:0] w_trans_rdcnt;
wire w_trans_rst_busy;
wire w_trans_full;
wire w_trans_empty;
wire [12:0] w_txdata_rd_datacount;
wire w_tx_full;
wire w_tx_empty;
wire w_eth_tx_tlast;
wire w_eth_tx_tkeep;
wire [3:0] w_eth_tx_tdest;
wire [7:0] w_eth_tx_tdata;
reg r_eth_tx_tlast;
reg [3:0] r_eth_tx_tdest;
reg [7:0] r_eth_tx_tdata;
reg r_eth_tx_tvalid;
wire w_rd_en;
reg [15:0] write_cnt;
wire [15:0] write_cnt_rd;
wire [15:0] write_cnt_next;
reg [15:0] read_cnt;
reg [1:0] rd_state;
reg [1:0] next_rd_state;
/*----------------------------------------------------------------------------------*\
The main code
\*----------------------------------------------------------------------------------*/
//axi4-lite interface
always @(posedge s_axi_aclk or negedge s_axi_aresetn)
begin
if(s_axi_aresetn == 1'b0)
loc_waddr <= {ADDR_WIDTH-2{1'b0}};
else if((s_axi_awvalid == 1'b1) && (s_axi_awready == 1'b1))
loc_waddr <= s_axi_awaddr[2+:ADDR_WIDTH-2];
end
always @(posedge s_axi_aclk or negedge s_axi_aresetn)
begin
if(s_axi_aresetn == 1'b0)
loc_waddr_vld <= 1'b0;
else if((s_axi_awvalid == 1'b1) && (s_axi_awready == 1'b1))
loc_waddr_vld <= 1'b1;
else if((loc_waddr_vld == 1'b1) && (loc_wdata_vld == 1'b1) && (loc_wrdy == 1'b1))
loc_waddr_vld <= 1'b0;
end
assign loc_wrdy = 1'b1;
always @(posedge s_axi_aclk or negedge s_axi_aresetn)
begin
if(s_axi_aresetn == 1'b0)
s_axi_awready <= 1'b0;
else if((s_axi_awvalid == 1'b1) && (s_axi_awready == 1'b1))
s_axi_awready <= 1'b0;
else if(loc_waddr_vld == 1'b0)
s_axi_awready <= 1'b1;
end
always @(posedge s_axi_aclk or negedge s_axi_aresetn)
begin
if(s_axi_aresetn == 1'b0)
loc_wdata <= 32'h0;
else if((s_axi_wvalid == 1'b1) && (s_axi_wready == 1'b1))
loc_wdata <= s_axi_wdata;
end
always @(posedge s_axi_aclk or negedge s_axi_aresetn)
begin
if(s_axi_aresetn == 1'b0)
loc_wdata_vld <= 1'b0;
else if((s_axi_wvalid == 1'b1) && (s_axi_wready == 1'b1))
loc_wdata_vld <= 1'b1;
else if((loc_waddr_vld == 1'b1) && (loc_wdata_vld == 1'b1) && (loc_wrdy == 1'b1))
loc_wdata_vld <= 1'b0;
end
always @(posedge s_axi_aclk or negedge s_axi_aresetn)
begin
if(s_axi_aresetn == 1'b0)
s_axi_wready <= 1'b0;
else if((s_axi_wvalid == 1'b1) && (s_axi_wready == 1'b1))
s_axi_wready <= 1'b0;
else if(loc_wdata_vld == 1'b0)
s_axi_wready <= 1'b1;
end
always @(posedge s_axi_aclk or negedge s_axi_aresetn)
begin
if(s_axi_aresetn == 1'b0)
s_axi_bvalid <= 1'b0;
else if((loc_waddr_vld == 1'b1) && (loc_wdata_vld == 1'b1) && (loc_wrdy == 1'b1))
s_axi_bvalid <= 1'b1;
else if(s_axi_bready == 1'b1)
s_axi_bvalid <= 1'b0;
end
assign s_axi_bresp = 2'h0;
always @(posedge s_axi_aclk or negedge s_axi_aresetn)
begin
if(s_axi_aresetn == 1'b0)
loc_raddr <= {ADDR_WIDTH-2{1'b0}};
else if((s_axi_arvalid == 1'b1) && (s_axi_arready == 1'b1))
loc_raddr <= s_axi_araddr[2+:ADDR_WIDTH-2];
end
always @(posedge s_axi_aclk or negedge s_axi_aresetn)
begin
if(s_axi_aresetn == 1'b0)
loc_raddr_vld <= 1'b0;
else if((s_axi_arvalid == 1'b1) && (s_axi_arready == 1'b1))
loc_raddr_vld <= 1'b1;
else if((loc_raddr_vld == 1'b1) && (loc_rrdy == 1'b1))
loc_raddr_vld <= 1'b0;
end
assign loc_rrdy = 1'b1;
always @(posedge s_axi_aclk or negedge s_axi_aresetn)
begin
if(s_axi_aresetn == 1'b0)
s_axi_arready <= 1'b0;
else if((s_axi_arvalid == 1'b1) && (s_axi_arready == 1'b1))
s_axi_arready <= 1'b0;
else if(loc_raddr_vld == 1'b0)
s_axi_arready <= 1'b1;
end
always @(posedge s_axi_aclk or negedge s_axi_aresetn)
begin
if(s_axi_aresetn == 1'b0)
s_axi_rdata <= 32'h0;
else if((loc_raddr_vld == 1'b1) && (loc_rrdy == 1'b1))
begin
case(loc_raddr)
//Base Configuration Registers Field
'h080:s_axi_rdata <= {31'd0, mac_sw_rst};
'h081:s_axi_rdata <= {31'd0, phy_sw_rst};
'h082:s_axi_rdata <= {31'd0, dma_rx_rst};
'h083:s_axi_rdata <= {31'd0, dma_tx_rst};
default:s_axi_rdata <= 32'hEEEE_1111;
endcase
end
end
always @(posedge s_axi_aclk or negedge s_axi_aresetn)
begin
if(s_axi_aresetn == 1'b0)
s_axi_rvalid <= 1'b0;
else if((loc_raddr_vld == 1'b1) && (loc_rrdy == 1'b1))
s_axi_rvalid <= 1'b1;
else if(s_axi_rready == 1'b1)
s_axi_rvalid <= 1'b0;
end
assign s_axi_rresp = 2'h0;
/*----------------------------------------------------------------------------------*\
Register Space -- Base Configuration Registers Field
\*----------------------------------------------------------------------------------*/
//loc_addr = 0x000; axi_addr = 0x000; RW;
always @(posedge s_axi_aclk or negedge s_axi_aresetn)
begin
if(s_axi_aresetn == 1'b0)
begin
mac_sw_rst <= 1'b0;
end
else if((s_axi_bvalid == 1'b1) && (loc_waddr == 'h080))
begin
mac_sw_rst <= loc_wdata[0];
end
end
//loc_addr = 0x001; axi_addr = 0x004; RW;
always @(posedge s_axi_aclk or negedge s_axi_aresetn)
begin
if(s_axi_aresetn == 1'b0)
begin
phy_sw_rst <= 1'b0;
end
else if((s_axi_bvalid == 1'b1) && (loc_waddr == 'h081))
begin
phy_sw_rst <= loc_wdata[0];
end
end
//loc_addr = 0x002; axi_addr = 0x008; RW;
always @(posedge s_axi_aclk or negedge s_axi_aresetn)
begin
if(s_axi_aresetn == 1'b0)
begin
dma_rx_rst <= 1'b0;
end
else if((s_axi_bvalid == 1'b1) && (loc_waddr == 'h082))
begin
dma_rx_rst <= loc_wdata[0];
end
end
//loc_addr = 0x003; axi_addr = 0x00C; RW;
always @(posedge s_axi_aclk or negedge s_axi_aresetn)
begin
if(s_axi_aresetn == 1'b0)
begin
dma_tx_rst <= 1'b0;
end
else if((s_axi_bvalid == 1'b1) && (loc_waddr == 'h083))
begin
dma_tx_rst <= loc_wdata[0];
end
end
/*----------------------------------------------------------------------------------*\
Register Space -- The End
\*----------------------------------------------------------------------------------*/
reset #(
.IN_RST_ACTIVE ("HIGH"),
.OUT_RST_ACTIVE ("HIGH"),
.CYCLE (2)
) inst_reset (
.i_arst (mac_ext_rst),
.i_clk (s_eth_tx_clk),
.o_srst (w_eth_mac_rst)
);
assign w_rd_en = (next_rd_state == 1);
assign write_cnt_next = (s_eth_tx_tkeep ? write_cnt + 1 : write_cnt);
assign s_eth_tx_tready = !w_tx_full;
assign m_eth_tx_tvalid = rd_state != 0;
assign m_eth_tx_tdata = w_eth_tx_tdata;
assign m_eth_tx_tdest = w_eth_tx_tdest;
assign m_eth_tx_tlast = r_eth_tx_tlast;
always @(posedge s_eth_tx_clk or posedge w_eth_mac_rst)
begin
if (w_eth_mac_rst)
begin
write_cnt <= 16'd0;
end
else begin
if (s_eth_tx_tvalid && s_eth_tx_tready)
begin
if (s_eth_tx_tlast)
begin
write_cnt <= 16'd0;
end
else if (s_eth_tx_tkeep)
begin
write_cnt <= write_cnt + 1'b1;
end
end
end
end
always @(*)
begin
case (rd_state)
2'b00:
begin
if (!w_trans_empty)
begin
next_rd_state = 2'b01;
end else
begin
next_rd_state = 2'b00;
end
end
2'b01:
begin
if (!m_eth_tx_tready)
begin
next_rd_state = 2'b10;
end else if (m_eth_tx_tlast)
begin
next_rd_state = 2'b00;
end else
begin
next_rd_state = 2'b01;
end
end
2'b10:
begin
if (m_eth_tx_tvalid && m_eth_tx_tready)
begin
if (m_eth_tx_tlast)
next_rd_state = 2'b00;
else
next_rd_state = 2'b01;
end else
begin
next_rd_state = 2'b10;
end
end
default:
begin
next_rd_state = 2'b00;
end
endcase
end
always @(posedge s_eth_tx_clk or posedge w_eth_mac_rst)
begin
if (w_eth_mac_rst)
begin
rd_state = 2'b00;
read_cnt = 16'd0;
r_eth_tx_tlast <= 1'b0;
end
else
begin
rd_state <= next_rd_state;
if (next_rd_state == 2'b00)
begin
read_cnt <= 16'd0;
r_eth_tx_tlast <= 1'b0;
end
else
begin
if (w_rd_en)
begin
read_cnt <= read_cnt + 1'b1;
if ((read_cnt + 1'b1) == write_cnt_rd)
begin
r_eth_tx_tlast <= 1'b1;
end
end
end
end
end
gTSE_core_fifo_data u_standard_tx_fifo_trans (
.a_rst_i (w_eth_mac_rst),
.wr_clk_i (s_eth_tx_clk),
.wr_en_i (s_eth_tx_tvalid && s_eth_tx_tready && s_eth_tx_tkeep),
.wdata ({s_eth_tx_tkeep,s_eth_tx_tdest, s_eth_tx_tdata}),
.rd_clk_i (s_eth_tx_clk),
.rd_en_i (w_rd_en),
.rdata ({w_eth_tx_tkeep, w_eth_tx_tdest, w_eth_tx_tdata}),
.full_o (w_tx_full),
.empty_o (w_tx_empty),
.wr_datacount_o (),
.rd_datacount_o (w_txdata_rd_datacount),
.rst_busy (w_tx_size_busy)
);
gTSE_core_fifo_ctrl u_fwft_tx_fifo_data (
.a_rst_i (w_eth_mac_rst),
.wr_clk_i (s_eth_tx_clk),
.wr_en_i (s_eth_tx_tvalid && s_eth_tx_tready && s_eth_tx_tlast),
.wdata (write_cnt_next),
.rd_clk_i (s_eth_tx_clk),
.rd_en_i (m_eth_tx_tvalid && m_eth_tx_tready && m_eth_tx_tlast),
.rdata (write_cnt_rd),
.full_o (w_trans_full),
.empty_o (w_trans_empty),
.wr_datacount_o (),
.rd_datacount_o (w_trans_rdcnt),
.rst_busy (w_trans_rst_busy)
);
always @(posedge s_eth_tx_clk or posedge w_eth_mac_rst)
begin
if (w_eth_mac_rst)
begin
error <= 1'b0;
end else
begin
if ((w_trans_full && s_eth_tx_tvalid && s_eth_tx_tready && s_eth_tx_tlast ) || w_trans_rst_busy || (w_trans_empty && w_rd_en))
error <= 1'b1;
end
end
endmodule
////////////////////////////////////////////////////////////////////////////////////////////
module reset
#(
parameter IN_RST_ACTIVE = "LOW",
parameter OUT_RST_ACTIVE = "HIGH",
parameter CYCLE = 1
)
(
input i_arst,
input i_clk,
output o_srst
);
(* async_reg = "true" *) reg [CYCLE-1:0]r_srst_1P;
genvar i;
generate
if (IN_RST_ACTIVE == "LOW")
begin
if (OUT_RST_ACTIVE == "LOW")
begin
always@(negedge i_arst or posedge i_clk)
begin
if (~i_arst)
r_srst_1P[0] <= 1'b0;
else
r_srst_1P[0] <= 1'b1;
end
for (i=0; i<CYCLE-1; i=i+1)
begin
always@(negedge i_arst or posedge i_clk)
begin
if (~i_arst)
r_srst_1P[i+1] <= 1'b0;
else
r_srst_1P[i+1] <= r_srst_1P[i];
end
end
end
else
begin
always@(negedge i_arst or posedge i_clk)
begin
if (~i_arst)
r_srst_1P[0] <= 1'b1;
else
r_srst_1P[0] <= 1'b0;
end
for (i=0; i<CYCLE-1; i=i+1)
begin
always@(negedge i_arst or posedge i_clk)
begin
if (~i_arst)
r_srst_1P[i+1] <= 1'b1;
else
r_srst_1P[i+1] <= r_srst_1P[i];
end
end
end
end
else
begin
if (OUT_RST_ACTIVE == "LOW")
begin
always@(posedge i_arst or posedge i_clk)
begin
if (i_arst)
r_srst_1P[0] <= 1'b0;
else
r_srst_1P[0] <= 1'b1;
end
for (i=0; i<CYCLE-1; i=i+1)
begin
always@(posedge i_arst or posedge i_clk)
begin
if (i_arst)
r_srst_1P[i+1] <= 1'b0;
else
r_srst_1P[i+1] <= r_srst_1P[i];
end
end
end
else
begin
always@(posedge i_arst or posedge i_clk)
begin
if (i_arst)
r_srst_1P[0] <= 1'b1;
else
r_srst_1P[0] <= 1'b0;
end
for (i=0; i<CYCLE-1; i=i+1)
begin
always@(posedge i_arst or posedge i_clk)
begin
if (i_arst)
r_srst_1P[i+1] <= 1'b1;
else
r_srst_1P[i+1] <= r_srst_1P[i];
end
end
end
end
endgenerate
assign o_srst = r_srst_1P[CYCLE-1];
endmodule
module reset_ctrl
#(
parameter NUM_RST = 1,
parameter CYCLE = 1,
parameter IN_RST_ACTIVE = 1'b1,
parameter OUT_RST_ACTIVE = 1'b1
)
(
input [NUM_RST-1:0] i_arst,
input [NUM_RST-1:0] i_clk,
output [NUM_RST-1:0] o_srst
);
genvar i;
generate
for (i=0; i<NUM_RST; i=i+1)
begin
if (IN_RST_ACTIVE & (1'b1 << i))
begin
if (OUT_RST_ACTIVE & (1'b1 << i))
begin
reset
#(
.IN_RST_ACTIVE ("HIGH"),
.OUT_RST_ACTIVE ("HIGH"),
.CYCLE (CYCLE)
)
inst_sysclk_rstn
(
.i_arst (i_arst[i]),
.i_clk (i_clk[i]),
.o_srst (o_srst[i])
);
end
else
begin
reset
#(
.IN_RST_ACTIVE ("HIGH"),
.OUT_RST_ACTIVE ("LOW"),
.CYCLE (CYCLE)
)
inst_sysclk_rstn
(
.i_arst (i_arst[i]),
.i_clk (i_clk[i]),
.o_srst (o_srst[i])
);
end
end
else
begin
if (OUT_RST_ACTIVE & (1'b1 << i))
begin
reset
#(
.IN_RST_ACTIVE ("LOW"),
.OUT_RST_ACTIVE ("HIGH"),
.CYCLE (CYCLE)
)
inst_sysclk_rstn
(
.i_arst (i_arst[i]),
.i_clk (i_clk[i]),
.o_srst (o_srst[i])
);
end
else
begin
reset
#(
.IN_RST_ACTIVE ("LOW"),
.OUT_RST_ACTIVE ("LOW"),
.CYCLE (CYCLE)
)
inst_sysclk_rstn
(
.i_arst (i_arst[i]),
.i_clk (i_clk[i]),
.o_srst (o_srst[i])
);
end
end
end
endgenerate
endmodule
////////////////////////////////////////////////////////////////////////////////////////////

2
init_env.sh
View File

@@ -1,7 +1,7 @@
PYTHON=python3
module load verilator
# module load vivado/2024.2
module load efinity
$PYTHON -m venv .venv/${HOSTNAME}
source .venv/${HOSTNAME}/bin/activate

2
sim/sim.yaml
View File

@@ -1,2 +0,0 @@
yaml:
- ../src/sub/upstream_path/sim/upstream_path.yaml

3
sim/verilator.vlt
View File

@@ -1,3 +0,0 @@
`verilator_config
lint_off -rule TIMESCALEMOD

2
src/common/crypto

Submodule src/common/crypto updated: 2fd1136154...f5e7b843b1

1
src/common/fifo Submodule

Submodule src/common/fifo added at 9f35e490dc

1
src/common/taxi

Submodule src/common/taxi deleted from 62da198a76

1
src/common/taxi-bsl Submodule

Submodule src/common/taxi-bsl added at 788ce5e982

684
src/common/taxi_sources.list
View File

@@ -1,342 +1,342 @@
taxi/src/cndm_proto/tb/cndm_proto_pcie_us/test_cndm_proto_pcie_us.sv
taxi/src/cndm_proto/rtl/cndm_proto_desc_rd.sv
taxi/src/cndm_proto/rtl/cndm_proto_tx.sv
taxi/src/cndm_proto/rtl/cndm_proto_core.sv
taxi/src/cndm_proto/rtl/cndm_proto_rx.sv
taxi/src/cndm_proto/rtl/cndm_proto_pcie_us.sv
taxi/src/cndm_proto/rtl/cndm_proto_port.sv
taxi/src/cndm_proto/rtl/cndm_proto_cpl_wr.sv
taxi/src/axi/tb/taxi_axi_adapter/test_taxi_axi_adapter.sv
taxi/src/axi/tb/taxi_axi_axil_adapter/test_taxi_axi_axil_adapter.sv
taxi/src/axi/tb/taxi_axil_dp_ram/test_taxi_axil_dp_ram.sv
taxi/src/axi/tb/taxi_axil_crossbar/test_taxi_axil_crossbar.sv
taxi/src/axi/tb/taxi_axi_interconnect/test_taxi_axi_interconnect.sv
taxi/src/axi/tb/taxi_axil_interconnect/test_taxi_axil_interconnect.sv
taxi/src/axi/tb/taxi_axi_ram/test_taxi_axi_ram.sv
taxi/src/axi/tb/taxi_axil_adapter/test_taxi_axil_adapter.sv
taxi/src/axi/tb/taxi_axi_fifo/test_taxi_axi_fifo.sv
taxi/src/axi/tb/taxi_axil_interconnect_1s/test_taxi_axil_interconnect_1s.sv
taxi/src/axi/tb/taxi_axil_ram/test_taxi_axil_ram.sv
taxi/src/axi/tb/taxi_axi_crossbar_1s/test_taxi_axi_crossbar_1s.sv
taxi/src/axi/tb/taxi_axi_interconnect_1s/test_taxi_axi_interconnect_1s.sv
taxi/src/axi/tb/taxi_axi_crossbar/test_taxi_axi_crossbar.sv
taxi/src/axi/tb/taxi_axi_register/test_taxi_axi_register.sv
taxi/src/axi/tb/taxi_axil_register/test_taxi_axil_register.sv
taxi/src/axi/tb/taxi_axil_apb_adapter/test_taxi_axil_apb_adapter.sv
taxi/src/axi/tb/taxi_axil_crossbar_1s/test_taxi_axil_crossbar_1s.sv
taxi/src/axi/tb/taxi_axil_axi_adapter/test_taxi_axil_axi_adapter.sv
taxi/src/axi/rtl/taxi_axil_axi_adapter_wr.sv
taxi/src/axi/rtl/taxi_axil_crossbar_1s_wr.sv
taxi/src/axi/rtl/taxi_axi_crossbar_wr.sv
taxi/src/axi/rtl/taxi_axil_crossbar_wr.sv
taxi/src/axi/rtl/taxi_axi_interconnect_rd.sv
taxi/src/axi/rtl/taxi_axil_ram.sv
taxi/src/axi/rtl/taxi_axi_axil_adapter_rd.sv
taxi/src/axi/rtl/taxi_axil_dp_ram.sv
taxi/src/axi/rtl/taxi_axi_adapter_rd.sv
taxi/src/axi/rtl/taxi_axi_axil_adapter.sv
taxi/src/axi/rtl/taxi_axil_register_wr.sv
taxi/src/axi/rtl/taxi_axi_tie_wr.sv
taxi/src/axi/rtl/taxi_axil_adapter_rd.sv
taxi/src/axi/rtl/taxi_axil_interconnect_1s_rd.sv
taxi/src/axi/rtl/taxi_axil_tie.sv
taxi/src/axi/rtl/taxi_axil_crossbar_rd.sv
taxi/src/axi/rtl/taxi_axil_adapter_wr.sv
taxi/src/axi/rtl/taxi_axil_if.sv
taxi/src/axi/rtl/taxi_axi_tie.sv
taxi/src/axi/rtl/taxi_axil_tie_rd.sv
taxi/src/axi/rtl/taxi_axi_interconnect_wr.sv
taxi/src/axi/rtl/taxi_axil_interconnect_wr.sv
taxi/src/axi/rtl/taxi_axil_apb_adapter.sv
taxi/src/axi/rtl/taxi_axi_interconnect_1s.sv
taxi/src/axi/rtl/taxi_axil_interconnect_rd.sv
taxi/src/axi/rtl/taxi_axi_crossbar_1s.sv
taxi/src/axi/rtl/taxi_axi_crossbar_1s_rd.sv
taxi/src/axi/rtl/taxi_axi_fifo_wr.sv
taxi/src/axi/rtl/taxi_axil_interconnect.sv
taxi/src/axi/rtl/taxi_axil_crossbar_addr.sv
taxi/src/axi/rtl/taxi_axil_tie_wr.sv
taxi/src/axi/rtl/taxi_axi_register_rd.sv
taxi/src/axi/rtl/taxi_axi_interconnect.sv
taxi/src/axi/rtl/taxi_axi_adapter_wr.sv
taxi/src/axi/rtl/taxi_axi_crossbar_addr.sv
taxi/src/axi/rtl/taxi_axil_axi_adapter.sv
taxi/src/axi/rtl/taxi_axil_register_rd.sv
taxi/src/axi/rtl/taxi_axi_ram.sv
taxi/src/axi/rtl/taxi_axil_crossbar.sv
taxi/src/axi/rtl/taxi_axi_crossbar_rd.sv
taxi/src/axi/rtl/taxi_axil_crossbar_1s_rd.sv
taxi/src/axi/rtl/taxi_axi_tie_rd.sv
taxi/src/axi/rtl/taxi_axil_register.sv
taxi/src/axi/rtl/taxi_axi_interconnect_1s_rd.sv
taxi/src/axi/rtl/taxi_axi_axil_adapter_wr.sv
taxi/src/axi/rtl/taxi_axi_crossbar_1s_wr.sv
taxi/src/axi/rtl/taxi_axi_crossbar.sv
taxi/src/axi/rtl/taxi_axi_interconnect_1s_wr.sv
taxi/src/axi/rtl/taxi_axil_interconnect_1s.sv
taxi/src/axi/rtl/taxi_axi_if.sv
taxi/src/axi/rtl/taxi_axi_fifo.sv
taxi/src/axi/rtl/taxi_axil_adapter.sv
taxi/src/axi/rtl/taxi_axi_adapter.sv
taxi/src/axi/rtl/taxi_axil_interconnect_1s_wr.sv
taxi/src/axi/rtl/taxi_axi_register_wr.sv
taxi/src/axi/rtl/taxi_axi_register.sv
taxi/src/axi/rtl/taxi_axil_axi_adapter_rd.sv
taxi/src/axi/rtl/taxi_axi_fifo_rd.sv
taxi/src/axi/rtl/taxi_axil_crossbar_1s.sv
taxi/src/sync/rtl/taxi_sync_reset.sv
taxi/src/sync/rtl/taxi_sync_signal.sv
taxi/src/lfsr/rtl/taxi_lfsr_crc.sv
taxi/src/lfsr/rtl/taxi_lfsr_prbs_gen.sv
taxi/src/lfsr/rtl/taxi_lfsr_scramble.sv
taxi/src/lfsr/rtl/taxi_lfsr.sv
taxi/src/lfsr/rtl/taxi_lfsr_prbs_check.sv
taxi/src/lfsr/rtl/taxi_lfsr_descramble.sv
taxi/src/axis/tb/taxi_axis_register/test_taxi_axis_register.sv
taxi/src/axis/tb/taxi_axis_pipeline_register/test_taxi_axis_pipeline_register.sv
taxi/src/axis/tb/taxi_axis_fifo/test_taxi_axis_fifo.sv
taxi/src/axis/tb/taxi_axis_async_fifo_adapter/test_taxi_axis_async_fifo_adapter.sv
taxi/src/axis/tb/taxi_axis_cobs_decode/test_taxi_axis_cobs_decode.sv
taxi/src/axis/tb/taxi_axis_adapter/test_taxi_axis_adapter.sv
taxi/src/axis/tb/taxi_axis_mux/test_taxi_axis_mux.sv
taxi/src/axis/tb/taxi_axis_concat/test_taxi_axis_concat.sv
taxi/src/axis/tb/taxi_axis_fifo_adapter/test_taxi_axis_fifo_adapter.sv
taxi/src/axis/tb/taxi_axis_demux/test_taxi_axis_demux.sv
taxi/src/axis/tb/taxi_axis_pipeline_fifo/test_taxi_axis_pipeline_fifo.sv
taxi/src/axis/tb/taxi_axis_switch/test_taxi_axis_switch.sv
taxi/src/axis/tb/taxi_axis_cobs_encode/test_taxi_axis_cobs_encode.sv
taxi/src/axis/tb/taxi_axis_async_fifo/test_taxi_axis_async_fifo.sv
taxi/src/axis/tb/taxi_axis_broadcast/test_taxi_axis_broadcast.sv
taxi/src/axis/tb/taxi_axis_arb_mux/test_taxi_axis_arb_mux.sv
taxi/src/axis/rtl/taxi_axis_switch.sv
taxi/src/axis/rtl/taxi_axis_async_fifo.sv
taxi/src/axis/rtl/taxi_axis_broadcast.sv
taxi/src/axis/rtl/taxi_axis_demux.sv
taxi/src/axis/rtl/taxi_axis_async_fifo_adapter.sv
taxi/src/axis/rtl/taxi_axis_cobs_encode.sv
taxi/src/axis/rtl/taxi_axis_tie.sv
taxi/src/axis/rtl/taxi_axis_pipeline_fifo.sv
taxi/src/axis/rtl/taxi_axis_arb_mux.sv
taxi/src/axis/rtl/taxi_axis_cobs_decode.sv
taxi/src/axis/rtl/taxi_axis_pipeline_register.sv
taxi/src/axis/rtl/taxi_axis_fifo_adapter.sv
taxi/src/axis/rtl/taxi_axis_mux.sv
taxi/src/axis/rtl/taxi_axis_concat.sv
taxi/src/axis/rtl/taxi_axis_fifo.sv
taxi/src/axis/rtl/taxi_axis_null_snk.sv
taxi/src/axis/rtl/taxi_axis_if.sv
taxi/src/axis/rtl/taxi_axis_adapter.sv
taxi/src/axis/rtl/taxi_axis_register.sv
taxi/src/axis/rtl/taxi_axis_null_src.sv
taxi/src/prim/rtl/taxi_arbiter.sv
taxi/src/prim/rtl/taxi_penc.sv
taxi/src/zircon/tb/zircon_ip_tx_deparse/test_zircon_ip_tx_deparse.sv
taxi/src/zircon/tb/zircon_ip_len_cksum/test_zircon_ip_len_cksum.sv
taxi/src/zircon/tb/zircon_ip_rx_parse/test_zircon_ip_rx_parse.sv
taxi/src/zircon/rtl/zircon_ip_tx_deparse.sv
taxi/src/zircon/rtl/zircon_ip_tx_ingress.sv
taxi/src/zircon/rtl/zircon_ip_rx_egress.sv
taxi/src/zircon/rtl/zircon_ip_len_cksum.sv
taxi/src/zircon/rtl/zircon_ip_tx_buffer.sv
taxi/src/zircon/rtl/zircon_ip_rx_ingress.sv
taxi/src/zircon/rtl/zircon_ip_rx_parse.sv
taxi/src/zircon/rtl/zircon_ip_tx_egress.sv
taxi/src/dma/tb/taxi_dma_if_pcie_us/test_taxi_dma_if_pcie_us.sv
taxi/src/dma/tb/taxi_dma_if_axi/test_taxi_dma_if_axi.sv
taxi/src/dma/tb/taxi_dma_psdpram_async/test_taxi_dma_psdpram_async.sv
taxi/src/dma/tb/taxi_dma_if_pcie_us_rd/test_taxi_dma_if_pcie_us_rd.sv
taxi/src/dma/tb/taxi_dma_if_axi_rd/test_taxi_dma_if_axi_rd.sv
taxi/src/dma/tb/taxi_axi_cdma/test_taxi_axi_cdma.sv
taxi/src/dma/tb/taxi_dma_psdpram/test_taxi_dma_psdpram.sv
taxi/src/dma/tb/taxi_dma_client_axis_source/test_taxi_dma_client_axis_source.sv
taxi/src/dma/tb/taxi_axi_dma/test_taxi_axi_dma.sv
taxi/src/dma/tb/taxi_dma_if_pcie_us_wr/test_taxi_dma_if_pcie_us_wr.sv
taxi/src/dma/tb/taxi_dma_if_axi_wr/test_taxi_dma_if_axi_wr.sv
taxi/src/dma/tb/taxi_dma_client_axis_sink/test_taxi_dma_client_axis_sink.sv
taxi/src/dma/rtl/taxi_axi_dma_rd.sv
taxi/src/dma/rtl/taxi_dma_if_pcie_us_wr.sv
taxi/src/dma/rtl/taxi_dma_ram_demux_rd.sv
taxi/src/dma/rtl/taxi_dma_desc_if.sv
taxi/src/dma/rtl/taxi_dma_if_pcie_us_rd.sv
taxi/src/dma/rtl/taxi_dma_desc_mux.sv
taxi/src/dma/rtl/taxi_dma_ram_demux_wr.sv
taxi/src/dma/rtl/taxi_axi_cdma.sv
taxi/src/dma/rtl/taxi_dma_client_axis_source.sv
taxi/src/dma/rtl/taxi_dma_psdpram_async.sv
taxi/src/dma/rtl/taxi_dma_ram_demux.sv
taxi/src/dma/rtl/taxi_axi_dma.sv
taxi/src/dma/rtl/taxi_dma_if_mux.sv
taxi/src/dma/rtl/taxi_dma_psdpram.sv
taxi/src/dma/rtl/taxi_dma_client_axis_sink.sv
taxi/src/dma/rtl/taxi_dma_if_mux_rd.sv
taxi/src/dma/rtl/taxi_dma_if_axi_wr.sv
taxi/src/dma/rtl/taxi_axi_dma_wr.sv
taxi/src/dma/rtl/taxi_dma_if_mux_wr.sv
taxi/src/dma/rtl/taxi_dma_if_pcie_us.sv
taxi/src/dma/rtl/taxi_dma_if_axi.sv
taxi/src/dma/rtl/taxi_dma_ram_if.sv
taxi/src/dma/rtl/taxi_dma_if_axi_rd.sv
taxi/src/pcie/tb/taxi_pcie_axil_master/test_taxi_pcie_axil_master.sv
taxi/src/pcie/tb/taxi_pcie_us_axil_master/test_taxi_pcie_us_axil_master.sv
taxi/src/pcie/tb/taxi_pcie_axil_master_minimal/test_taxi_pcie_axil_master_minimal.sv
taxi/src/pcie/rtl/taxi_pcie_us_axil_master.sv
taxi/src/pcie/rtl/taxi_pcie_axil_master.sv
taxi/src/pcie/rtl/taxi_pcie_tlp_if.sv
taxi/src/pcie/rtl/taxi_pcie_us_msi.sv
taxi/src/pcie/rtl/taxi_pcie_axil_master_minimal.sv
taxi/src/xfcp/tb/taxi_xfcp_if_uart/test_taxi_xfcp_if_uart.sv
taxi/src/xfcp/tb/taxi_xfcp_mod_i2c_master/test_taxi_xfcp_mod_i2c_master.sv
taxi/src/xfcp/tb/taxi_xfcp_switch/test_taxi_xfcp_switch.sv
taxi/src/xfcp/tb/taxi_xfcp_mod_axi/test_taxi_xfcp_mod_axi.sv
taxi/src/xfcp/tb/taxi_xfcp_mod_apb/test_taxi_xfcp_mod_apb.sv
taxi/src/xfcp/tb/taxi_xfcp_mod_axil/test_taxi_xfcp_mod_axil.sv
taxi/src/xfcp/rtl/taxi_xfcp_mod_axi.sv
taxi/src/xfcp/rtl/taxi_xfcp_switch.sv
taxi/src/xfcp/rtl/taxi_xfcp_if_uart.sv
taxi/src/xfcp/rtl/taxi_xfcp_mod_axil.sv
taxi/src/xfcp/rtl/taxi_xfcp_mod_apb.sv
taxi/src/xfcp/rtl/taxi_xfcp_mod_i2c_master.sv
taxi/src/xfcp/rtl/taxi_xfcp_mod_stats.sv
taxi/src/math/tb/taxi_mt19937/test_taxi_mt19937.sv
taxi/src/math/rtl/taxi_mt19937.sv
taxi/src/hip/rtl/us/taxi_gt_qpll_reset.sv
taxi/src/hip/rtl/us/taxi_gt_rx_reset.sv
taxi/src/hip/rtl/us/taxi_gt_tx_reset.sv
taxi/src/hip/rtl/us/taxi_mmcm_frac.sv
taxi/src/cndm/board/AS02MC04/fpga/tb/fpga_core/test_fpga_core.sv
taxi/src/cndm/board/AS02MC04/fpga/rtl/fpga_core.sv
taxi/src/cndm/board/AS02MC04/fpga/rtl/fpga.sv
taxi/src/cndm/tb/cndm_micro_pcie_us/test_cndm_micro_pcie_us.sv
taxi/src/cndm/rtl/cndm_micro_core.sv
taxi/src/cndm/rtl/cndm_micro_tx.sv
taxi/src/cndm/rtl/cndm_micro_pcie_us.sv
taxi/src/cndm/rtl/cndm_micro_desc_rd.sv
taxi/src/cndm/rtl/cndm_micro_cpl_wr.sv
taxi/src/cndm/rtl/cndm_micro_rx.sv
taxi/src/cndm/rtl/cndm_micro_port.sv
taxi/src/stats/tb/taxi_stats_collect/test_taxi_stats_collect.sv
taxi/src/stats/tb/taxi_stats_strings_full/test_taxi_stats_strings_full.sv
taxi/src/stats/tb/taxi_stats_counter/test_taxi_stats_counter.sv
taxi/src/stats/rtl/taxi_stats_counter.sv
taxi/src/stats/rtl/taxi_stats_collect.sv
taxi/src/stats/rtl/taxi_stats_strings_full.sv
taxi/src/io/rtl/taxi_ssio_sdr_out_diff.sv
taxi/src/io/rtl/taxi_iddr.sv
taxi/src/io/rtl/taxi_ssio_sdr_in.sv
taxi/src/io/rtl/taxi_ssio_ddr_in.sv
taxi/src/io/rtl/taxi_ssio_sdr_in_diff.sv
taxi/src/io/rtl/taxi_led_sreg.sv
taxi/src/io/rtl/taxi_ssio_ddr_out_diff.sv
taxi/src/io/rtl/taxi_debounce_switch.sv
taxi/src/io/rtl/taxi_ssio_ddr_out.sv
taxi/src/io/rtl/taxi_ssio_sdr_out.sv
taxi/src/io/rtl/taxi_ssio_ddr_in_diff.sv
taxi/src/io/rtl/taxi_oddr.sv
taxi/src/eth/tb/taxi_axis_xgmii_tx_64/test_taxi_axis_xgmii_tx_64.sv
taxi/src/eth/tb/taxi_axis_baser_tx_32/test_taxi_axis_baser_tx_32.sv
taxi/src/eth/tb/taxi_eth_mac_25g_us/test_taxi_eth_mac_25g_us.sv
taxi/src/eth/tb/taxi_mac_ctrl_tx/test_taxi_mac_ctrl_tx.sv
taxi/src/eth/tb/taxi_eth_mac_1g_gmii_fifo/test_taxi_eth_mac_1g_gmii_fifo.sv
taxi/src/eth/tb/taxi_eth_mac_1g_rgmii_fifo/test_taxi_eth_mac_1g_rgmii_fifo.sv
taxi/src/eth/tb/taxi_axis_baser_rx_32/test_taxi_axis_baser_rx_32.sv
taxi/src/eth/tb/taxi_eth_mac_mii/test_taxi_eth_mac_mii.sv
taxi/src/eth/tb/taxi_mac_ctrl_rx/test_taxi_mac_ctrl_rx.sv
taxi/src/eth/tb/taxi_eth_mac_1g_gmii/test_taxi_eth_mac_1g_gmii.sv
taxi/src/eth/tb/taxi_axis_gmii_rx/test_taxi_axis_gmii_rx.sv
taxi/src/eth/tb/taxi_eth_mac_phy_10g_fifo/test_taxi_eth_mac_phy_10g_fifo.sv
taxi/src/eth/tb/taxi_axis_xgmii_rx_32/test_taxi_axis_xgmii_rx_32.sv
taxi/src/eth/tb/taxi_eth_mac_mii_fifo/test_taxi_eth_mac_mii_fifo.sv
taxi/src/eth/tb/taxi_axis_baser_rx_64/test_taxi_axis_baser_rx_64.sv
taxi/src/eth/tb/taxi_eth_mac_1g_rgmii/test_taxi_eth_mac_1g_rgmii.sv
taxi/src/eth/tb/taxi_eth_mac_phy_10g/test_taxi_eth_mac_phy_10g.sv
taxi/src/eth/tb/taxi_axis_xgmii_rx_64/test_taxi_axis_xgmii_rx_64.sv
taxi/src/eth/tb/taxi_axis_gmii_tx/test_taxi_axis_gmii_tx.sv
taxi/src/eth/tb/taxi_eth_mac_1g_fifo/test_taxi_eth_mac_1g_fifo.sv
taxi/src/eth/tb/taxi_eth_mac_10g_fifo/test_taxi_eth_mac_10g_fifo.sv
taxi/src/eth/tb/taxi_axis_xgmii_tx_32/test_taxi_axis_xgmii_tx_32.sv
taxi/src/eth/tb/taxi_axis_baser_tx_64/test_taxi_axis_baser_tx_64.sv
taxi/src/eth/tb/taxi_eth_mac_10g/test_taxi_eth_mac_10g.sv
taxi/src/eth/tb/taxi_eth_mac_1g/test_taxi_eth_mac_1g.sv
taxi/src/eth/rtl/taxi_axis_baser_rx_64.sv
taxi/src/eth/rtl/taxi_eth_mac_1g_gmii_fifo.sv
taxi/src/eth/rtl/taxi_eth_mac_mii_fifo.sv
taxi/src/eth/rtl/taxi_eth_phy_10g_rx_frame_sync.sv
taxi/src/eth/rtl/taxi_xgmii_baser_dec.sv
taxi/src/eth/rtl/taxi_eth_phy_10g_tx.sv
taxi/src/eth/rtl/taxi_eth_phy_10g_rx_ber_mon.sv
taxi/src/eth/rtl/taxi_eth_phy_10g_rx_watchdog.sv
taxi/src/eth/rtl/taxi_axis_baser_rx_32.sv
taxi/src/eth/rtl/taxi_axis_xgmii_rx_32.sv
taxi/src/eth/rtl/taxi_eth_phy_10g_rx.sv
taxi/src/eth/rtl/us/taxi_eth_mac_25g_us.sv
taxi/src/eth/rtl/us/taxi_eth_phy_10g_us_gt_ll.sv
taxi/src/eth/rtl/us/taxi_eth_phy_25g_us_gt_ll.sv
taxi/src/eth/rtl/us/taxi_eth_phy_10g_7_gt.sv
taxi/src/eth/rtl/us/taxi_eth_phy_25g_us_gt_apb.sv
taxi/src/eth/rtl/us/taxi_eth_phy_10g_us_gt.sv
taxi/src/eth/rtl/us/taxi_eth_mac_25g_us_ch.sv
taxi/src/eth/rtl/us/taxi_eth_phy_25g_us_gt.sv
taxi/src/eth/rtl/taxi_eth_mac_1g_fifo.sv
taxi/src/eth/rtl/taxi_xgmii_baser_enc.sv
taxi/src/eth/rtl/taxi_eth_mac_10g_fifo.sv
taxi/src/eth/rtl/taxi_eth_phy_10g_rx_if.sv
taxi/src/eth/rtl/taxi_eth_mac_stats.sv
taxi/src/eth/rtl/taxi_axis_baser_tx_32.sv
taxi/src/eth/rtl/taxi_eth_mac_phy_10g_rx.sv
taxi/src/eth/rtl/taxi_mac_ctrl_rx.sv
taxi/src/eth/rtl/taxi_eth_mac_phy_10g_tx.sv
taxi/src/eth/rtl/taxi_axis_gmii_rx.sv
taxi/src/eth/rtl/taxi_eth_phy_10g.sv
taxi/src/eth/rtl/taxi_axis_xgmii_rx_64.sv
taxi/src/eth/rtl/taxi_axis_xgmii_tx_64.sv
taxi/src/eth/rtl/taxi_rgmii_phy_if.sv
taxi/src/eth/rtl/taxi_eth_phy_10g_tx_if.sv
taxi/src/eth/rtl/taxi_eth_mac_phy_10g.sv
taxi/src/eth/rtl/taxi_axis_xgmii_tx_32.sv
taxi/src/eth/rtl/taxi_mac_pause_ctrl_tx.sv
taxi/src/eth/rtl/taxi_eth_mac_mii.sv
taxi/src/eth/rtl/taxi_eth_mac_1g_gmii.sv
taxi/src/eth/rtl/taxi_mac_ctrl_tx.sv
taxi/src/eth/rtl/taxi_eth_mac_1g_rgmii.sv
taxi/src/eth/rtl/taxi_mac_pause_ctrl_rx.sv
taxi/src/eth/rtl/taxi_eth_mac_1g_rgmii_fifo.sv
taxi/src/eth/rtl/taxi_eth_mac_10g.sv
taxi/src/eth/rtl/taxi_eth_mac_1g.sv
taxi/src/eth/rtl/taxi_mii_phy_if.sv
taxi/src/eth/rtl/taxi_axis_gmii_tx.sv
taxi/src/eth/rtl/taxi_axis_baser_tx_64.sv
taxi/src/eth/rtl/taxi_gmii_phy_if.sv
taxi/src/eth/rtl/taxi_eth_mac_phy_10g_fifo.sv
taxi/src/lss/tb/taxi_i2c_master/test_taxi_i2c_master.sv
taxi/src/lss/tb/taxi_uart/test_taxi_uart.sv
taxi/src/lss/tb/taxi_i2c_slave_apb_master/test_taxi_i2c_slave_apb_master.sv
taxi/src/lss/tb/taxi_i2c_slave_axil_master/test_taxi_i2c_slave_axil_master.sv
taxi/src/lss/tb/taxi_i2c_single_reg/test_taxi_i2c_single_reg.sv
taxi/src/lss/tb/taxi_i2c_slave/test_taxi_i2c_slave.sv
taxi/src/lss/rtl/taxi_mdio_master.sv
taxi/src/lss/rtl/taxi_i2c_slave_axil_master.sv
taxi/src/lss/rtl/taxi_i2c_single_reg.sv
taxi/src/lss/rtl/taxi_i2c_master.sv
taxi/src/lss/rtl/taxi_i2c_slave.sv
taxi/src/lss/rtl/taxi_i2c_slave_apb_master.sv
taxi/src/lss/rtl/taxi_uart_brg.sv
taxi/src/lss/rtl/taxi_i2c_init.sv
taxi/src/lss/rtl/taxi_uart_rx.sv
taxi/src/lss/rtl/taxi_uart.sv
taxi/src/lss/rtl/taxi_uart_tx.sv
taxi/src/ptp/tb/taxi_ptp_td_rel2tod/test_taxi_ptp_td_rel2tod.sv
taxi/src/ptp/rtl/taxi_ptp_clock_cdc.sv
taxi/src/ptp/rtl/taxi_ptp_clock.sv
taxi/src/ptp/rtl/taxi_ptp_td_leaf.sv
taxi/src/ptp/rtl/taxi_ptp_td_phc.sv
taxi/src/ptp/rtl/taxi_ptp_td_rel2tod.sv
taxi/src/ptp/rtl/taxi_ptp_perout.sv
taxi/src/apb/tb/taxi_apb_adapter/test_taxi_apb_adapter.sv
taxi/src/apb/tb/taxi_apb_dp_ram/test_taxi_apb_dp_ram.sv
taxi/src/apb/tb/taxi_apb_ram/test_taxi_apb_ram.sv
taxi/src/apb/tb/taxi_apb_interconnect/test_taxi_apb_interconnect.sv
taxi/src/apb/rtl/taxi_apb_interconnect.sv
taxi/src/apb/rtl/taxi_apb_ram.sv
taxi/src/apb/rtl/taxi_apb_if.sv
taxi/src/apb/rtl/taxi_apb_adapter.sv
taxi/src/apb/rtl/taxi_apb_dp_ram.sv
taxi-bsl/src/cndm_proto/tb/cndm_proto_pcie_us/test_cndm_proto_pcie_us.sv
taxi-bsl/src/cndm_proto/rtl/cndm_proto_desc_rd.sv
taxi-bsl/src/cndm_proto/rtl/cndm_proto_tx.sv
taxi-bsl/src/cndm_proto/rtl/cndm_proto_core.sv
taxi-bsl/src/cndm_proto/rtl/cndm_proto_rx.sv
taxi-bsl/src/cndm_proto/rtl/cndm_proto_pcie_us.sv
taxi-bsl/src/cndm_proto/rtl/cndm_proto_port.sv
taxi-bsl/src/cndm_proto/rtl/cndm_proto_cpl_wr.sv
taxi-bsl/src/axi/tb/taxi_axi_adapter/test_taxi_axi_adapter.sv
taxi-bsl/src/axi/tb/taxi_axi_axil_adapter/test_taxi_axi_axil_adapter.sv
taxi-bsl/src/axi/tb/taxi_axil_dp_ram/test_taxi_axil_dp_ram.sv
taxi-bsl/src/axi/tb/taxi_axil_crossbar/test_taxi_axil_crossbar.sv
taxi-bsl/src/axi/tb/taxi_axi_interconnect/test_taxi_axi_interconnect.sv
taxi-bsl/src/axi/tb/taxi_axil_interconnect/test_taxi_axil_interconnect.sv
taxi-bsl/src/axi/tb/taxi_axi_ram/test_taxi_axi_ram.sv
taxi-bsl/src/axi/tb/taxi_axil_adapter/test_taxi_axil_adapter.sv
taxi-bsl/src/axi/tb/taxi_axi_fifo/test_taxi_axi_fifo.sv
taxi-bsl/src/axi/tb/taxi_axil_interconnect_1s/test_taxi_axil_interconnect_1s.sv
taxi-bsl/src/axi/tb/taxi_axil_ram/test_taxi_axil_ram.sv
taxi-bsl/src/axi/tb/taxi_axi_crossbar_1s/test_taxi_axi_crossbar_1s.sv
taxi-bsl/src/axi/tb/taxi_axi_interconnect_1s/test_taxi_axi_interconnect_1s.sv
taxi-bsl/src/axi/tb/taxi_axi_crossbar/test_taxi_axi_crossbar.sv
taxi-bsl/src/axi/tb/taxi_axi_register/test_taxi_axi_register.sv
taxi-bsl/src/axi/tb/taxi_axil_register/test_taxi_axil_register.sv
taxi-bsl/src/axi/tb/taxi_axil_apb_adapter/test_taxi_axil_apb_adapter.sv
taxi-bsl/src/axi/tb/taxi_axil_crossbar_1s/test_taxi_axil_crossbar_1s.sv
taxi-bsl/src/axi/tb/taxi_axil_axi_adapter/test_taxi_axil_axi_adapter.sv
taxi-bsl/src/axi/rtl/taxi_axil_axi_adapter_wr.sv
taxi-bsl/src/axi/rtl/taxi_axil_crossbar_1s_wr.sv
taxi-bsl/src/axi/rtl/taxi_axi_crossbar_wr.sv
taxi-bsl/src/axi/rtl/taxi_axil_crossbar_wr.sv
taxi-bsl/src/axi/rtl/taxi_axi_interconnect_rd.sv
taxi-bsl/src/axi/rtl/taxi_axil_ram.sv
taxi-bsl/src/axi/rtl/taxi_axi_axil_adapter_rd.sv
taxi-bsl/src/axi/rtl/taxi_axil_dp_ram.sv
taxi-bsl/src/axi/rtl/taxi_axi_adapter_rd.sv
taxi-bsl/src/axi/rtl/taxi_axi_axil_adapter.sv
taxi-bsl/src/axi/rtl/taxi_axil_register_wr.sv
taxi-bsl/src/axi/rtl/taxi_axi_tie_wr.sv
taxi-bsl/src/axi/rtl/taxi_axil_adapter_rd.sv
taxi-bsl/src/axi/rtl/taxi_axil_interconnect_1s_rd.sv
taxi-bsl/src/axi/rtl/taxi_axil_tie.sv
taxi-bsl/src/axi/rtl/taxi_axil_crossbar_rd.sv
taxi-bsl/src/axi/rtl/taxi_axil_adapter_wr.sv
taxi-bsl/src/axi/rtl/taxi_axil_if.sv
taxi-bsl/src/axi/rtl/taxi_axi_tie.sv
taxi-bsl/src/axi/rtl/taxi_axil_tie_rd.sv
taxi-bsl/src/axi/rtl/taxi_axi_interconnect_wr.sv
taxi-bsl/src/axi/rtl/taxi_axil_interconnect_wr.sv
taxi-bsl/src/axi/rtl/taxi_axil_apb_adapter.sv
taxi-bsl/src/axi/rtl/taxi_axi_interconnect_1s.sv
taxi-bsl/src/axi/rtl/taxi_axil_interconnect_rd.sv
taxi-bsl/src/axi/rtl/taxi_axi_crossbar_1s.sv
taxi-bsl/src/axi/rtl/taxi_axi_crossbar_1s_rd.sv
taxi-bsl/src/axi/rtl/taxi_axi_fifo_wr.sv
taxi-bsl/src/axi/rtl/taxi_axil_interconnect.sv
taxi-bsl/src/axi/rtl/taxi_axil_crossbar_addr.sv
taxi-bsl/src/axi/rtl/taxi_axil_tie_wr.sv
taxi-bsl/src/axi/rtl/taxi_axi_register_rd.sv
taxi-bsl/src/axi/rtl/taxi_axi_interconnect.sv
taxi-bsl/src/axi/rtl/taxi_axi_adapter_wr.sv
taxi-bsl/src/axi/rtl/taxi_axi_crossbar_addr.sv
taxi-bsl/src/axi/rtl/taxi_axil_axi_adapter.sv
taxi-bsl/src/axi/rtl/taxi_axil_register_rd.sv
taxi-bsl/src/axi/rtl/taxi_axi_ram.sv
taxi-bsl/src/axi/rtl/taxi_axil_crossbar.sv
taxi-bsl/src/axi/rtl/taxi_axi_crossbar_rd.sv
taxi-bsl/src/axi/rtl/taxi_axil_crossbar_1s_rd.sv
taxi-bsl/src/axi/rtl/taxi_axi_tie_rd.sv
taxi-bsl/src/axi/rtl/taxi_axil_register.sv
taxi-bsl/src/axi/rtl/taxi_axi_interconnect_1s_rd.sv
taxi-bsl/src/axi/rtl/taxi_axi_axil_adapter_wr.sv
taxi-bsl/src/axi/rtl/taxi_axi_crossbar_1s_wr.sv
taxi-bsl/src/axi/rtl/taxi_axi_crossbar.sv
taxi-bsl/src/axi/rtl/taxi_axi_interconnect_1s_wr.sv
taxi-bsl/src/axi/rtl/taxi_axil_interconnect_1s.sv
taxi-bsl/src/axi/rtl/taxi_axi_if.sv
taxi-bsl/src/axi/rtl/taxi_axi_fifo.sv
taxi-bsl/src/axi/rtl/taxi_axil_adapter.sv
taxi-bsl/src/axi/rtl/taxi_axi_adapter.sv
taxi-bsl/src/axi/rtl/taxi_axil_interconnect_1s_wr.sv
taxi-bsl/src/axi/rtl/taxi_axi_register_wr.sv
taxi-bsl/src/axi/rtl/taxi_axi_register.sv
taxi-bsl/src/axi/rtl/taxi_axil_axi_adapter_rd.sv
taxi-bsl/src/axi/rtl/taxi_axi_fifo_rd.sv
taxi-bsl/src/axi/rtl/taxi_axil_crossbar_1s.sv
taxi-bsl/src/sync/rtl/taxi_sync_reset.sv
taxi-bsl/src/sync/rtl/taxi_sync_signal.sv
taxi-bsl/src/lfsr/rtl/taxi_lfsr_crc.sv
taxi-bsl/src/lfsr/rtl/taxi_lfsr_prbs_gen.sv
taxi-bsl/src/lfsr/rtl/taxi_lfsr_scramble.sv
taxi-bsl/src/lfsr/rtl/taxi_lfsr.sv
taxi-bsl/src/lfsr/rtl/taxi_lfsr_prbs_check.sv
taxi-bsl/src/lfsr/rtl/taxi_lfsr_descramble.sv
taxi-bsl/src/axis/tb/taxi_axis_register/test_taxi_axis_register.sv
taxi-bsl/src/axis/tb/taxi_axis_pipeline_register/test_taxi_axis_pipeline_register.sv
taxi-bsl/src/axis/tb/taxi_axis_fifo/test_taxi_axis_fifo.sv
taxi-bsl/src/axis/tb/taxi_axis_async_fifo_adapter/test_taxi_axis_async_fifo_adapter.sv
taxi-bsl/src/axis/tb/taxi_axis_cobs_decode/test_taxi_axis_cobs_decode.sv
taxi-bsl/src/axis/tb/taxi_axis_adapter/test_taxi_axis_adapter.sv
taxi-bsl/src/axis/tb/taxi_axis_mux/test_taxi_axis_mux.sv
taxi-bsl/src/axis/tb/taxi_axis_concat/test_taxi_axis_concat.sv
taxi-bsl/src/axis/tb/taxi_axis_fifo_adapter/test_taxi_axis_fifo_adapter.sv
taxi-bsl/src/axis/tb/taxi_axis_demux/test_taxi_axis_demux.sv
taxi-bsl/src/axis/tb/taxi_axis_pipeline_fifo/test_taxi_axis_pipeline_fifo.sv
taxi-bsl/src/axis/tb/taxi_axis_switch/test_taxi_axis_switch.sv
taxi-bsl/src/axis/tb/taxi_axis_cobs_encode/test_taxi_axis_cobs_encode.sv
taxi-bsl/src/axis/tb/taxi_axis_async_fifo/test_taxi_axis_async_fifo.sv
taxi-bsl/src/axis/tb/taxi_axis_broadcast/test_taxi_axis_broadcast.sv
taxi-bsl/src/axis/tb/taxi_axis_arb_mux/test_taxi_axis_arb_mux.sv
taxi-bsl/src/axis/rtl/taxi_axis_switch.sv
taxi-bsl/src/axis/rtl/taxi_axis_async_fifo.sv
taxi-bsl/src/axis/rtl/taxi_axis_broadcast.sv
taxi-bsl/src/axis/rtl/taxi_axis_demux.sv
taxi-bsl/src/axis/rtl/taxi_axis_async_fifo_adapter.sv
taxi-bsl/src/axis/rtl/taxi_axis_cobs_encode.sv
taxi-bsl/src/axis/rtl/taxi_axis_tie.sv
taxi-bsl/src/axis/rtl/taxi_axis_pipeline_fifo.sv
taxi-bsl/src/axis/rtl/taxi_axis_arb_mux.sv
taxi-bsl/src/axis/rtl/taxi_axis_cobs_decode.sv
taxi-bsl/src/axis/rtl/taxi_axis_pipeline_register.sv
taxi-bsl/src/axis/rtl/taxi_axis_fifo_adapter.sv
taxi-bsl/src/axis/rtl/taxi_axis_mux.sv
taxi-bsl/src/axis/rtl/taxi_axis_concat.sv
taxi-bsl/src/axis/rtl/taxi_axis_fifo.sv
taxi-bsl/src/axis/rtl/taxi_axis_null_snk.sv
taxi-bsl/src/axis/rtl/taxi_axis_if.sv
taxi-bsl/src/axis/rtl/taxi_axis_adapter.sv
taxi-bsl/src/axis/rtl/taxi_axis_register.sv
taxi-bsl/src/axis/rtl/taxi_axis_null_src.sv
taxi-bsl/src/prim/rtl/taxi_arbiter.sv
taxi-bsl/src/prim/rtl/taxi_penc.sv
taxi-bsl/src/zircon/tb/zircon_ip_tx_deparse/test_zircon_ip_tx_deparse.sv
taxi-bsl/src/zircon/tb/zircon_ip_len_cksum/test_zircon_ip_len_cksum.sv
taxi-bsl/src/zircon/tb/zircon_ip_rx_parse/test_zircon_ip_rx_parse.sv
taxi-bsl/src/zircon/rtl/zircon_ip_tx_deparse.sv
taxi-bsl/src/zircon/rtl/zircon_ip_tx_ingress.sv
taxi-bsl/src/zircon/rtl/zircon_ip_rx_egress.sv
taxi-bsl/src/zircon/rtl/zircon_ip_len_cksum.sv
taxi-bsl/src/zircon/rtl/zircon_ip_tx_buffer.sv
taxi-bsl/src/zircon/rtl/zircon_ip_rx_ingress.sv
taxi-bsl/src/zircon/rtl/zircon_ip_rx_parse.sv
taxi-bsl/src/zircon/rtl/zircon_ip_tx_egress.sv
taxi-bsl/src/dma/tb/taxi_dma_if_pcie_us/test_taxi_dma_if_pcie_us.sv
taxi-bsl/src/dma/tb/taxi_dma_if_axi/test_taxi_dma_if_axi.sv
taxi-bsl/src/dma/tb/taxi_dma_psdpram_async/test_taxi_dma_psdpram_async.sv
taxi-bsl/src/dma/tb/taxi_dma_if_pcie_us_rd/test_taxi_dma_if_pcie_us_rd.sv
taxi-bsl/src/dma/tb/taxi_dma_if_axi_rd/test_taxi_dma_if_axi_rd.sv
taxi-bsl/src/dma/tb/taxi_axi_cdma/test_taxi_axi_cdma.sv
taxi-bsl/src/dma/tb/taxi_dma_psdpram/test_taxi_dma_psdpram.sv
taxi-bsl/src/dma/tb/taxi_dma_client_axis_source/test_taxi_dma_client_axis_source.sv
taxi-bsl/src/dma/tb/taxi_axi_dma/test_taxi_axi_dma.sv
taxi-bsl/src/dma/tb/taxi_dma_if_pcie_us_wr/test_taxi_dma_if_pcie_us_wr.sv
taxi-bsl/src/dma/tb/taxi_dma_if_axi_wr/test_taxi_dma_if_axi_wr.sv
taxi-bsl/src/dma/tb/taxi_dma_client_axis_sink/test_taxi_dma_client_axis_sink.sv
taxi-bsl/src/dma/rtl/taxi_axi_dma_rd.sv
taxi-bsl/src/dma/rtl/taxi_dma_if_pcie_us_wr.sv
taxi-bsl/src/dma/rtl/taxi_dma_ram_demux_rd.sv
taxi-bsl/src/dma/rtl/taxi_dma_desc_if.sv
taxi-bsl/src/dma/rtl/taxi_dma_if_pcie_us_rd.sv
taxi-bsl/src/dma/rtl/taxi_dma_desc_mux.sv
taxi-bsl/src/dma/rtl/taxi_dma_ram_demux_wr.sv
taxi-bsl/src/dma/rtl/taxi_axi_cdma.sv
taxi-bsl/src/dma/rtl/taxi_dma_client_axis_source.sv
taxi-bsl/src/dma/rtl/taxi_dma_psdpram_async.sv
taxi-bsl/src/dma/rtl/taxi_dma_ram_demux.sv
taxi-bsl/src/dma/rtl/taxi_axi_dma.sv
taxi-bsl/src/dma/rtl/taxi_dma_if_mux.sv
taxi-bsl/src/dma/rtl/taxi_dma_psdpram.sv
taxi-bsl/src/dma/rtl/taxi_dma_client_axis_sink.sv
taxi-bsl/src/dma/rtl/taxi_dma_if_mux_rd.sv
taxi-bsl/src/dma/rtl/taxi_dma_if_axi_wr.sv
taxi-bsl/src/dma/rtl/taxi_axi_dma_wr.sv
taxi-bsl/src/dma/rtl/taxi_dma_if_mux_wr.sv
taxi-bsl/src/dma/rtl/taxi_dma_if_pcie_us.sv
taxi-bsl/src/dma/rtl/taxi_dma_if_axi.sv
taxi-bsl/src/dma/rtl/taxi_dma_ram_if.sv
taxi-bsl/src/dma/rtl/taxi_dma_if_axi_rd.sv
taxi-bsl/src/pcie/tb/taxi_pcie_axil_master/test_taxi_pcie_axil_master.sv
taxi-bsl/src/pcie/tb/taxi_pcie_us_axil_master/test_taxi_pcie_us_axil_master.sv
taxi-bsl/src/pcie/tb/taxi_pcie_axil_master_minimal/test_taxi_pcie_axil_master_minimal.sv
taxi-bsl/src/pcie/rtl/taxi_pcie_us_axil_master.sv
taxi-bsl/src/pcie/rtl/taxi_pcie_axil_master.sv
taxi-bsl/src/pcie/rtl/taxi_pcie_tlp_if.sv
taxi-bsl/src/pcie/rtl/taxi_pcie_us_msi.sv
taxi-bsl/src/pcie/rtl/taxi_pcie_axil_master_minimal.sv
taxi-bsl/src/xfcp/tb/taxi_xfcp_if_uart/test_taxi_xfcp_if_uart.sv
taxi-bsl/src/xfcp/tb/taxi_xfcp_mod_i2c_master/test_taxi_xfcp_mod_i2c_master.sv
taxi-bsl/src/xfcp/tb/taxi_xfcp_switch/test_taxi_xfcp_switch.sv
taxi-bsl/src/xfcp/tb/taxi_xfcp_mod_axi/test_taxi_xfcp_mod_axi.sv
taxi-bsl/src/xfcp/tb/taxi_xfcp_mod_apb/test_taxi_xfcp_mod_apb.sv
taxi-bsl/src/xfcp/tb/taxi_xfcp_mod_axil/test_taxi_xfcp_mod_axil.sv
taxi-bsl/src/xfcp/rtl/taxi_xfcp_mod_axi.sv
taxi-bsl/src/xfcp/rtl/taxi_xfcp_switch.sv
taxi-bsl/src/xfcp/rtl/taxi_xfcp_if_uart.sv
taxi-bsl/src/xfcp/rtl/taxi_xfcp_mod_axil.sv
taxi-bsl/src/xfcp/rtl/taxi_xfcp_mod_apb.sv
taxi-bsl/src/xfcp/rtl/taxi_xfcp_mod_i2c_master.sv
taxi-bsl/src/xfcp/rtl/taxi_xfcp_mod_stats.sv
taxi-bsl/src/math/tb/taxi_mt19937/test_taxi_mt19937.sv
taxi-bsl/src/math/rtl/taxi_mt19937.sv
taxi-bsl/src/hip/rtl/us/taxi_gt_qpll_reset.sv
taxi-bsl/src/hip/rtl/us/taxi_gt_rx_reset.sv
taxi-bsl/src/hip/rtl/us/taxi_gt_tx_reset.sv
taxi-bsl/src/hip/rtl/us/taxi_mmcm_frac.sv
taxi-bsl/src/cndm/board/AS02MC04/fpga/tb/fpga_core/test_fpga_core.sv
taxi-bsl/src/cndm/board/AS02MC04/fpga/rtl/fpga_core.sv
taxi-bsl/src/cndm/board/AS02MC04/fpga/rtl/fpga.sv
taxi-bsl/src/cndm/tb/cndm_micro_pcie_us/test_cndm_micro_pcie_us.sv
taxi-bsl/src/cndm/rtl/cndm_micro_core.sv
taxi-bsl/src/cndm/rtl/cndm_micro_tx.sv
taxi-bsl/src/cndm/rtl/cndm_micro_pcie_us.sv
taxi-bsl/src/cndm/rtl/cndm_micro_desc_rd.sv
taxi-bsl/src/cndm/rtl/cndm_micro_cpl_wr.sv
taxi-bsl/src/cndm/rtl/cndm_micro_rx.sv
taxi-bsl/src/cndm/rtl/cndm_micro_port.sv
taxi-bsl/src/stats/tb/taxi_stats_collect/test_taxi_stats_collect.sv
taxi-bsl/src/stats/tb/taxi_stats_strings_full/test_taxi_stats_strings_full.sv
taxi-bsl/src/stats/tb/taxi_stats_counter/test_taxi_stats_counter.sv
taxi-bsl/src/stats/rtl/taxi_stats_counter.sv
taxi-bsl/src/stats/rtl/taxi_stats_collect.sv
taxi-bsl/src/stats/rtl/taxi_stats_strings_full.sv
taxi-bsl/src/io/rtl/taxi_ssio_sdr_out_diff.sv
taxi-bsl/src/io/rtl/taxi_iddr.sv
taxi-bsl/src/io/rtl/taxi_ssio_sdr_in.sv
taxi-bsl/src/io/rtl/taxi_ssio_ddr_in.sv
taxi-bsl/src/io/rtl/taxi_ssio_sdr_in_diff.sv
taxi-bsl/src/io/rtl/taxi_led_sreg.sv
taxi-bsl/src/io/rtl/taxi_ssio_ddr_out_diff.sv
taxi-bsl/src/io/rtl/taxi_debounce_switch.sv
taxi-bsl/src/io/rtl/taxi_ssio_ddr_out.sv
taxi-bsl/src/io/rtl/taxi_ssio_sdr_out.sv
taxi-bsl/src/io/rtl/taxi_ssio_ddr_in_diff.sv
taxi-bsl/src/io/rtl/taxi_oddr.sv
taxi-bsl/src/eth/tb/taxi_axis_xgmii_tx_64/test_taxi_axis_xgmii_tx_64.sv
taxi-bsl/src/eth/tb/taxi_axis_baser_tx_32/test_taxi_axis_baser_tx_32.sv
taxi-bsl/src/eth/tb/taxi_eth_mac_25g_us/test_taxi_eth_mac_25g_us.sv
taxi-bsl/src/eth/tb/taxi_mac_ctrl_tx/test_taxi_mac_ctrl_tx.sv
taxi-bsl/src/eth/tb/taxi_eth_mac_1g_gmii_fifo/test_taxi_eth_mac_1g_gmii_fifo.sv
taxi-bsl/src/eth/tb/taxi_eth_mac_1g_rgmii_fifo/test_taxi_eth_mac_1g_rgmii_fifo.sv
taxi-bsl/src/eth/tb/taxi_axis_baser_rx_32/test_taxi_axis_baser_rx_32.sv
taxi-bsl/src/eth/tb/taxi_eth_mac_mii/test_taxi_eth_mac_mii.sv
taxi-bsl/src/eth/tb/taxi_mac_ctrl_rx/test_taxi_mac_ctrl_rx.sv
taxi-bsl/src/eth/tb/taxi_eth_mac_1g_gmii/test_taxi_eth_mac_1g_gmii.sv
taxi-bsl/src/eth/tb/taxi_axis_gmii_rx/test_taxi_axis_gmii_rx.sv
taxi-bsl/src/eth/tb/taxi_eth_mac_phy_10g_fifo/test_taxi_eth_mac_phy_10g_fifo.sv
taxi-bsl/src/eth/tb/taxi_axis_xgmii_rx_32/test_taxi_axis_xgmii_rx_32.sv
taxi-bsl/src/eth/tb/taxi_eth_mac_mii_fifo/test_taxi_eth_mac_mii_fifo.sv
taxi-bsl/src/eth/tb/taxi_axis_baser_rx_64/test_taxi_axis_baser_rx_64.sv
taxi-bsl/src/eth/tb/taxi_eth_mac_1g_rgmii/test_taxi_eth_mac_1g_rgmii.sv
taxi-bsl/src/eth/tb/taxi_eth_mac_phy_10g/test_taxi_eth_mac_phy_10g.sv
taxi-bsl/src/eth/tb/taxi_axis_xgmii_rx_64/test_taxi_axis_xgmii_rx_64.sv
taxi-bsl/src/eth/tb/taxi_axis_gmii_tx/test_taxi_axis_gmii_tx.sv
taxi-bsl/src/eth/tb/taxi_eth_mac_1g_fifo/test_taxi_eth_mac_1g_fifo.sv
taxi-bsl/src/eth/tb/taxi_eth_mac_10g_fifo/test_taxi_eth_mac_10g_fifo.sv
taxi-bsl/src/eth/tb/taxi_axis_xgmii_tx_32/test_taxi_axis_xgmii_tx_32.sv
taxi-bsl/src/eth/tb/taxi_axis_baser_tx_64/test_taxi_axis_baser_tx_64.sv
taxi-bsl/src/eth/tb/taxi_eth_mac_10g/test_taxi_eth_mac_10g.sv
taxi-bsl/src/eth/tb/taxi_eth_mac_1g/test_taxi_eth_mac_1g.sv
taxi-bsl/src/eth/rtl/taxi_axis_baser_rx_64.sv
taxi-bsl/src/eth/rtl/taxi_eth_mac_1g_gmii_fifo.sv
taxi-bsl/src/eth/rtl/taxi_eth_mac_mii_fifo.sv
taxi-bsl/src/eth/rtl/taxi_eth_phy_10g_rx_frame_sync.sv
taxi-bsl/src/eth/rtl/taxi_xgmii_baser_dec.sv
taxi-bsl/src/eth/rtl/taxi_eth_phy_10g_tx.sv
taxi-bsl/src/eth/rtl/taxi_eth_phy_10g_rx_ber_mon.sv
taxi-bsl/src/eth/rtl/taxi_eth_phy_10g_rx_watchdog.sv
taxi-bsl/src/eth/rtl/taxi_axis_baser_rx_32.sv
taxi-bsl/src/eth/rtl/taxi_axis_xgmii_rx_32.sv
taxi-bsl/src/eth/rtl/taxi_eth_phy_10g_rx.sv
taxi-bsl/src/eth/rtl/us/taxi_eth_mac_25g_us.sv
taxi-bsl/src/eth/rtl/us/taxi_eth_phy_10g_us_gt_ll.sv
taxi-bsl/src/eth/rtl/us/taxi_eth_phy_25g_us_gt_ll.sv
taxi-bsl/src/eth/rtl/us/taxi_eth_phy_10g_7_gt.sv
taxi-bsl/src/eth/rtl/us/taxi_eth_phy_25g_us_gt_apb.sv
taxi-bsl/src/eth/rtl/us/taxi_eth_phy_10g_us_gt.sv
taxi-bsl/src/eth/rtl/us/taxi_eth_mac_25g_us_ch.sv
taxi-bsl/src/eth/rtl/us/taxi_eth_phy_25g_us_gt.sv
taxi-bsl/src/eth/rtl/taxi_eth_mac_1g_fifo.sv
taxi-bsl/src/eth/rtl/taxi_xgmii_baser_enc.sv
taxi-bsl/src/eth/rtl/taxi_eth_mac_10g_fifo.sv
taxi-bsl/src/eth/rtl/taxi_eth_phy_10g_rx_if.sv
taxi-bsl/src/eth/rtl/taxi_eth_mac_stats.sv
taxi-bsl/src/eth/rtl/taxi_axis_baser_tx_32.sv
taxi-bsl/src/eth/rtl/taxi_eth_mac_phy_10g_rx.sv
taxi-bsl/src/eth/rtl/taxi_mac_ctrl_rx.sv
taxi-bsl/src/eth/rtl/taxi_eth_mac_phy_10g_tx.sv
taxi-bsl/src/eth/rtl/taxi_axis_gmii_rx.sv
taxi-bsl/src/eth/rtl/taxi_eth_phy_10g.sv
taxi-bsl/src/eth/rtl/taxi_axis_xgmii_rx_64.sv
taxi-bsl/src/eth/rtl/taxi_axis_xgmii_tx_64.sv
taxi-bsl/src/eth/rtl/taxi_rgmii_phy_if.sv
taxi-bsl/src/eth/rtl/taxi_eth_phy_10g_tx_if.sv
taxi-bsl/src/eth/rtl/taxi_eth_mac_phy_10g.sv
taxi-bsl/src/eth/rtl/taxi_axis_xgmii_tx_32.sv
taxi-bsl/src/eth/rtl/taxi_mac_pause_ctrl_tx.sv
taxi-bsl/src/eth/rtl/taxi_eth_mac_mii.sv
taxi-bsl/src/eth/rtl/taxi_eth_mac_1g_gmii.sv
taxi-bsl/src/eth/rtl/taxi_mac_ctrl_tx.sv
taxi-bsl/src/eth/rtl/taxi_eth_mac_1g_rgmii.sv
taxi-bsl/src/eth/rtl/taxi_mac_pause_ctrl_rx.sv
taxi-bsl/src/eth/rtl/taxi_eth_mac_1g_rgmii_fifo.sv
taxi-bsl/src/eth/rtl/taxi_eth_mac_10g.sv
taxi-bsl/src/eth/rtl/taxi_eth_mac_1g.sv
taxi-bsl/src/eth/rtl/taxi_mii_phy_if.sv
taxi-bsl/src/eth/rtl/taxi_axis_gmii_tx.sv
taxi-bsl/src/eth/rtl/taxi_axis_baser_tx_64.sv
taxi-bsl/src/eth/rtl/taxi_gmii_phy_if.sv
taxi-bsl/src/eth/rtl/taxi_eth_mac_phy_10g_fifo.sv
taxi-bsl/src/lss/tb/taxi_i2c_master/test_taxi_i2c_master.sv
taxi-bsl/src/lss/tb/taxi_uart/test_taxi_uart.sv
taxi-bsl/src/lss/tb/taxi_i2c_slave_apb_master/test_taxi_i2c_slave_apb_master.sv
taxi-bsl/src/lss/tb/taxi_i2c_slave_axil_master/test_taxi_i2c_slave_axil_master.sv
taxi-bsl/src/lss/tb/taxi_i2c_single_reg/test_taxi_i2c_single_reg.sv
taxi-bsl/src/lss/tb/taxi_i2c_slave/test_taxi_i2c_slave.sv
taxi-bsl/src/lss/rtl/taxi_mdio_master.sv
taxi-bsl/src/lss/rtl/taxi_i2c_slave_axil_master.sv
taxi-bsl/src/lss/rtl/taxi_i2c_single_reg.sv
taxi-bsl/src/lss/rtl/taxi_i2c_master.sv
taxi-bsl/src/lss/rtl/taxi_i2c_slave.sv
taxi-bsl/src/lss/rtl/taxi_i2c_slave_apb_master.sv
taxi-bsl/src/lss/rtl/taxi_uart_brg.sv
taxi-bsl/src/lss/rtl/taxi_i2c_init.sv
taxi-bsl/src/lss/rtl/taxi_uart_rx.sv
taxi-bsl/src/lss/rtl/taxi_uart.sv
taxi-bsl/src/lss/rtl/taxi_uart_tx.sv
taxi-bsl/src/ptp/tb/taxi_ptp_td_rel2tod/test_taxi_ptp_td_rel2tod.sv
taxi-bsl/src/ptp/rtl/taxi_ptp_clock_cdc.sv
taxi-bsl/src/ptp/rtl/taxi_ptp_clock.sv
taxi-bsl/src/ptp/rtl/taxi_ptp_td_leaf.sv
taxi-bsl/src/ptp/rtl/taxi_ptp_td_phc.sv
taxi-bsl/src/ptp/rtl/taxi_ptp_td_rel2tod.sv
taxi-bsl/src/ptp/rtl/taxi_ptp_perout.sv
taxi-bsl/src/apb/tb/taxi_apb_adapter/test_taxi_apb_adapter.sv
taxi-bsl/src/apb/tb/taxi_apb_dp_ram/test_taxi_apb_dp_ram.sv
taxi-bsl/src/apb/tb/taxi_apb_ram/test_taxi_apb_ram.sv
taxi-bsl/src/apb/tb/taxi_apb_interconnect/test_taxi_apb_interconnect.sv
taxi-bsl/src/apb/rtl/taxi_apb_interconnect.sv
taxi-bsl/src/apb/rtl/taxi_apb_ram.sv
taxi-bsl/src/apb/rtl/taxi_apb_if.sv
taxi-bsl/src/apb/rtl/taxi_apb_adapter.sv
taxi-bsl/src/apb/rtl/taxi_apb_dp_ram.sv

17
src/sub/downstream_path/downstream_path.sv
View File

@@ -1,17 +0,0 @@
module downstream_path (
input clk,
input rst,
taxi_axis_if.snk s_axis_data,
taxi_axis_if.src m_axis_data,
taxi_axi_if.rd_mst m_axi_rd,
taxi_axi_if.wr_mst m_axi_wr,
taxi_apb_if.slv s_apb_cfg,
output logic o_irq_m2s,
output logic o_irq_s2m
);
endmodule

7
src/sub/upstream_path/sim/sources.list
View File

@@ -1,7 +0,0 @@
../../../../sim/verilator.vlt
upstream_ip_check_harness.sv
../src/sources.list
../../../common/taxi_sources.list

65
src/sub/upstream_path/sim/upstream_ip_check.py
View File

@@ -1,65 +0,0 @@
import cocotb
from scapy.layers.l2 import Ether
from scapy.layers.inet import IP, TCP
from cocotb.handle import Immediate
from cocotb.clock import Clock
from cocotb.triggers import Timer, RisingEdge
from cocotbext.axi import AxiStreamBus, AxiStreamSink, AxiStreamSource
import logging
CLK_PERIOD = 5
class TB:
def __init__(self, dut):
self.dut = dut
self.log = logging.getLogger("cocotb.tb")
self.log.setLevel(logging.INFO)
cocotb.start_soon(Clock(self.dut.clk, CLK_PERIOD, unit="ns").start())
self.s_axis_data = AxiStreamSource(AxiStreamBus.from_prefix(dut.s_axis_data, ""), dut.clk, dut.rst)
self.m_axis_dma = AxiStreamSink(AxiStreamBus.from_prefix(dut.m_axis_dma, ""), dut.clk, dut.rst)
self.m_axis_data = AxiStreamSink(AxiStreamBus.from_prefix(dut.m_axis_data, ""), dut.clk, dut.rst)
async def cycle_reset(self):
await self._cycle_reset(self.dut.rst, self.dut.clk)
async def _cycle_reset(self, rst, clk):
rst.value = Immediate(0)
await RisingEdge(clk)
await RisingEdge(clk)
rst.value = 1
await RisingEdge(clk)
await RisingEdge(clk)
rst.value = 0
await RisingEdge(clk)
await RisingEdge(clk)
@cocotb.test
async def test_sanity(dut):
tb = TB(dut)
await tb.cycle_reset()
tb.dut.i_dest_ip.value = 0xc0a85715
pkt_0 = Ether() / IP(src="127.0.0.1", dst="192.168.87.21") / TCP() / "Hello, world!"
await tb.s_axis_data.send(pkt_0.build())
pkt_1 = Ether() / IP(src="127.0.0.1", dst="192.168.87.22") / TCP() / "Different Data now!"
await tb.s_axis_data.send(pkt_1.build())
recv_pkt_0 = await tb.m_axis_data.recv()
recv_pkt_1 = await tb.m_axis_dma.recv()
assert recv_pkt_0.tdata == pkt_0.build()
assert recv_pkt_1.tdata == pkt_1.build()

21
src/sub/upstream_path/sim/upstream_ip_check_harness.sv
View File

@@ -1,21 +0,0 @@
module upstream_ip_check_harness();
taxi_axis_if #(.DATA_W(32)) s_axis_data();
taxi_axis_if #(.DATA_W(32)) m_axis_dma();
taxi_axis_if #(.DATA_W(32)) m_axis_data();
logic clk;
logic rst;
logic [31:0] i_dest_ip;
upstream_ip_check #(.DATA_W(32)) u_dut (
.clk (clk),
.rst (rst),
.s_axis_data (s_axis_data),
.m_axis_dma (m_axis_dma),
.m_axis_data (m_axis_data),
.i_dest_ip (i_dest_ip)
);
endmodule

7
src/sub/upstream_path/sim/upstream_path.yaml
View File

@@ -1,7 +0,0 @@
tests:
- name: "upstream_ip_check"
toplevel: "upstream_ip_check_harness"
modules:
- "upstream_ip_check"
sources: "sources.list"
waves: True

1
src/sub/upstream_path/src/sources.list
View File

@@ -1 +0,0 @@
upstream_ip_check.sv

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