2026-01-17 22:45:49 -08:00
2026-01-17 22:45:49 -08:00
2026-01-17 22:45:49 -08:00
2026-01-17 22:39:04 -08:00
2026-01-17 22:39:04 -08:00
Description
FPGA for wireguard
Readme GPL-3.0 3.9 MiB
Languages
C 60.1%
Verilog 32.4%
SystemVerilog 6.1%
VHDL 0.6%
Tcl 0.4%
Other 0.2%