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Added clarification of memory interface

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Arlet Ottens
2015-08-31 20:25:47 +02:00
parent dff3abaaac
commit ae653ab688
2 changed files with 6 additions and 2 deletions
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README
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A Verilog HDL version of the old MOS 6502 CPU.
Have fun.
Note: the 6502 core assumes a synchronous memory. This means that valid
data (DI) is expected on the cycle *after* valid address. This allows
direct connection to (Xilinx) block RAMs. When using asynchronous memory,
I suggest registering the address/control lines for glitchless output signals.
Have fun.