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Updated README

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Arlet Ottens
2020-10-21 12:12:56 +02:00
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README → README.md
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@@ -5,4 +5,6 @@ data (DI) is expected on the cycle *after* valid address. This allows
direct connection to (Xilinx) block RAMs. When using asynchronous memory, direct connection to (Xilinx) block RAMs. When using asynchronous memory,
I suggest registering the address/control lines for glitchless output signals. I suggest registering the address/control lines for glitchless output signals.
[Also check out my new 65C02 project](https://github.com/Arlet/verilog-65c02)
Have fun. Have fun.