- Feb 25, 2025
-
-
Byron Lathi authored
-
- Feb 23, 2025
-
-
Byron Lathi authored
This is a separate repo that needs to be included as a submodule now.
-
- Feb 09, 2025
-
-
Byron Lathi authored
-
- Jan 16, 2025
-
-
Byron Lathi authored
-
- Jan 02, 2025
-
-
Byron Lathi authored
-
- Dec 24, 2024
-
-
Byron Lathi authored
-
- Dec 22, 2024
-
-
Byron Lathi authored
-
- Dec 20, 2024
-
-
Byron Lathi authored
-
- Oct 15, 2024
-
-
Byron Lathi authored
-
- Oct 14, 2024
-
-
Byron Lathi authored
-
- Aug 20, 2024
-
-
Byron Lathi authored
-
- Jun 16, 2024
-
-
Byron Lathi authored
Resolve "Reset hdr_ready_seen" Closes #3 See merge request bslathi19/verilog-ethernet!3
-
Byron Lathi authored
-
Byron Lathi authored
Resolve "Ethernet Frame Duplicator" Closes #2 See merge request bslathi19/verilog-ethernet!2
-
- Jun 15, 2024
-
-
Byron Lathi authored
-
Byron Lathi authored
-
- Jun 09, 2024
-
-
Byron Lathi authored
-
- Jun 04, 2024
-
-
Byron Lathi authored
Resolve "Add 8 bit ICMP rx/tx" Closes #1 See merge request bslathi19/verilog-ethernet!1
-
Byron Lathi authored
-
- Jun 03, 2024
-
-
Byron Lathi authored
-
- Jun 02, 2024
-
-
Byron Lathi authored
-
Byron Lathi authored
-
Byron Lathi authored
-
- May 30, 2024
-
-
Byron Lathi authored
-
- Feb 13, 2024
-
-
Alex Forencich authored
Reorganize PTP timestamp capture logic; determine PTP clock step size from PTP time instead of parameters Signed-off-by:
Alex Forencich <alex@alexforencich.com>
-
- Feb 11, 2024
-
-
Alex Forencich authored
Signed-off-by:
Alex Forencich <alex@alexforencich.com>
-
Alex Forencich authored
Move alternate offset switch near the end of the current second to extend reconstruction range for timestamps in the past Signed-off-by:
Alex Forencich <alex@alexforencich.com>
-
Alex Forencich authored
Signed-off-by:
Alex Forencich <alex@alexforencich.com>
-
- Feb 09, 2024
-
-
Alex Forencich authored
Remove extraneous scaleb(-9) in set_ts_tod_ns in ptp_td so that the seconds field can be set correctly Signed-off-by:
Alex Forencich <alex@alexforencich.com>
-
- Feb 06, 2024
-
-
Alex Forencich authored
-
Alex Forencich authored
Signed-off-by:
Alex Forencich <alex@alexforencich.com>
-
- Jan 30, 2024
-
-
Alex Forencich authored
Rework MAC TX error handling to streamline logic; pad errored frames to avoid generating runt frames Signed-off-by:
Alex Forencich <alex@alexforencich.com>
-
Alex Forencich authored
Signed-off-by:
Alex Forencich <alex@alexforencich.com>
-
Alex Forencich authored
Signed-off-by:
Alex Forencich <alex@alexforencich.com>
-
- Jan 29, 2024
-
-
Alex Forencich authored
Signed-off-by:
Alex Forencich <alex@alexforencich.com>
-
Alex Forencich authored
Signed-off-by:
Alex Forencich <alex@alexforencich.com>
-
Alex Forencich authored
Signed-off-by:
Alex Forencich <alex@alexforencich.com>
-
- Jan 28, 2024
-
-
Alex Forencich authored
Signed-off-by:
Alex Forencich <alex@alexforencich.com>
-
Alex Forencich authored
Signed-off-by:
Alex Forencich <alex@alexforencich.com>
-
Alex Forencich authored
Signed-off-by:
Alex Forencich <alex@alexforencich.com>
-