Using Base/Mask addressing makes it impossible to have memory regions
which are not aligned to their size, which will not work for our
application. For example, we want to have zeropage and stack in SRAM but
the rest of the slaves in a sdram or ddr ram. With the old addressing
scheme, this is impossible since the first memory area is 512 bytes,
which means the proceding memory area can only be 512 bytes max.

The other solution to this is to have these smaller memory areas handled
in the address translater, but I would rather have the ability to have
arbitrarily sized and aligned memory areas in the crossbar. If this
impacts performance too much then I guess it can be re-evaluated

- Data width * max burst length > 4kB
    Max burst length is now internally adjusted so
      it checks for this bound and doesn't exceed it
    Register widths have been adjusted internally so
      that the design properly synthesizes again
- Sync on TLAST would never lose sync due to a
    circular dependency.  This has now been fixed.
- Documentation adjusted to reflect that writing
    to the r_busy bit starts the transfer.
- A race condition was preventing abort from ever
    releasing the IP, in the case where nothing
    was outstanding.  This has now been fixed.
- A skid buffer was added to the incoming packet
    stream.  This buffer's presence is parameterized,
    and may be removed if not desired.