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regblock -> busdecoder

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This commit is contained in:
Arnav Sacheti
2025-10-10 22:30:59 -07:00
parent 9bf5cd1e68
commit b4f9eaff71
78 changed files with 904 additions and 705 deletions
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14
docs/api.rst
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@@ -2,9 +2,9 @@ Exporter API
============
If you are not using the `PeakRDL command-line tool <https://peakrdl.readthedocs.io>`_,
you can still generate regblocks programmatically using the exporter API:
you can still generate busdecoders programmatically using the exporter API:
.. autoclass:: peakrdl_regblock.RegblockExporter
.. autoclass:: peakrdl_busdecoder.BusDecoderExporter
:members:
Example
@@ -16,9 +16,9 @@ implementation from SystemRDL source.
:emphasize-lines: 2-4, 29-33
from systemrdl import RDLCompiler, RDLCompileError
from peakrdl_regblock import RegblockExporter
from peakrdl_regblock.cpuif.axi4lite import AXI4Lite_Cpuif
from peakrdl_regblock.udps import ALL_UDPS
from peakrdl_busdecoder import BusDecoderExporter
from peakrdl_busdecoder.cpuif.axi4lite import AXI4Lite_Cpuif
from peakrdl_busdecoder.udps import ALL_UDPS
input_files = [
"PATH/TO/my_register_block.rdl"
@@ -27,7 +27,7 @@ implementation from SystemRDL source.
# Create an instance of the compiler
rdlc = RDLCompiler()
# Register all UDPs that 'regblock' requires
# Register all UDPs that 'busdecoder' requires
for udp in ALL_UDPS:
rdlc.register_udp(udp)
@@ -43,7 +43,7 @@ implementation from SystemRDL source.
sys.exit(1)
# Export a SystemVerilog implementation
exporter = RegblockExporter()
exporter = BusDecoderExporter()
exporter.export(
root, "path/to/output_dir",
cpuif_cls=AXI4Lite_Cpuif

19
docs/conf.py
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@@ -12,15 +12,16 @@
#
import os
import sys
sys.path.insert(0, os.path.abspath('../src/'))
sys.path.insert(0, os.path.abspath("../src/"))
import datetime
# -- Project information -----------------------------------------------------
project = 'PeakRDL-regblock'
copyright = '%d, Alex Mykyta' % datetime.datetime.now().year
author = 'Alex Mykyta'
project = "PeakRDL-busdecoder"
copyright = "%d, Alex Mykyta" % datetime.datetime.now().year
author = "Alex Mykyta"
# -- General configuration ---------------------------------------------------
@@ -29,19 +30,19 @@ author = 'Alex Mykyta'
# extensions coming with Sphinx (named 'sphinx.ext.*') or your custom
# ones.
extensions = [
'sphinx.ext.autodoc',
'sphinx.ext.napoleon',
"sphinx.ext.autodoc",
"sphinx.ext.napoleon",
"sphinxcontrib.wavedrom",
]
render_using_wavedrompy = True
# Add any paths that contain templates here, relative to this directory.
templates_path = ['_templates']
templates_path = ["_templates"]
# List of patterns, relative to source directory, that match files and
# directories to ignore when looking for source files.
# This pattern also affects html_static_path and html_extra_path.
exclude_patterns = ['_build', 'Thumbs.db', '.DS_Store']
exclude_patterns = ["_build", "Thumbs.db", ".DS_Store"]
# -- Options for HTML output -------------------------------------------------
@@ -52,7 +53,7 @@ exclude_patterns = ['_build', 'Thumbs.db', '.DS_Store']
html_theme = "sphinx_book_theme"
html_theme_options = {
"repository_url": "https://github.com/SystemRDL/PeakRDL-regblock",
"repository_url": "https://github.com/SystemRDL/PeakRDL-busdecoder",
"path_to_docs": "docs",
"use_download_button": False,
"use_source_button": True,

10
docs/configuring.rst
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@@ -1,13 +1,13 @@
.. _peakrdl_cfg:
Configuring PeakRDL-regblock
Configuring PeakRDL-busdecoder
============================
If using the `PeakRDL command line tool <https://peakrdl.readthedocs.io/>`_,
some aspects of the ``regblock`` command have additional configuration options
some aspects of the ``busdecoder`` command have additional configuration options
available via the PeakRDL TOML file.
All regblock-specific options are defined under the ``[regblock]`` TOML heading.
All busdecoder-specific options are defined under the ``[busdecoder]`` TOML heading.
.. data:: cpuifs
@@ -20,7 +20,7 @@ All regblock-specific options are defined under the ``[regblock]`` TOML heading.
.. code-block:: toml
[regblock]
[busdecoder]
cpuifs.my-cpuif-name = "my_cpuif_module:MyCPUInterfaceClass"
@@ -41,5 +41,5 @@ All regblock-specific options are defined under the ``[regblock]`` TOML heading.
.. code-block:: toml
[regblock]
[busdecoder]
default_reset = "arst"

8
docs/cpuif/apb.rst
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@@ -29,13 +29,13 @@ The APB3 CPU interface comes in two i/o port flavors:
SystemVerilog Interface
* Command line: ``--cpuif apb3``
* Interface Definition: :download:`apb3_intf.sv <../../hdl-src/apb3_intf.sv>`
* Class: :class:`peakrdl_regblock.cpuif.apb3.APB3_Cpuif`
* Class: :class:`peakrdl_busdecoder.cpuif.apb3.APB3_Cpuif`
Flattened inputs/outputs
Flattens the interface into discrete input and output ports.
* Command line: ``--cpuif apb3-flat``
* Class: :class:`peakrdl_regblock.cpuif.apb3.APB3_Cpuif_flattened`
* Class: :class:`peakrdl_busdecoder.cpuif.apb3.APB3_Cpuif_flattened`
APB4
@@ -50,10 +50,10 @@ The APB4 CPU interface comes in two i/o port flavors:
SystemVerilog Interface
* Command line: ``--cpuif apb4``
* Interface Definition: :download:`apb4_intf.sv <../../hdl-src/apb4_intf.sv>`
* Class: :class:`peakrdl_regblock.cpuif.apb4.APB4_Cpuif`
* Class: :class:`peakrdl_busdecoder.cpuif.apb4.APB4_Cpuif`
Flattened inputs/outputs
Flattens the interface into discrete input and output ports.
* Command line: ``--cpuif apb4-flat``
* Class: :class:`peakrdl_regblock.cpuif.apb4.APB4_Cpuif_flattened`
* Class: :class:`peakrdl_busdecoder.cpuif.apb4.APB4_Cpuif_flattened`

4
docs/cpuif/avalon.rst
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@@ -10,13 +10,13 @@ The Avalon interface comes in two i/o port flavors:
SystemVerilog Interface
* Command line: ``--cpuif avalon-mm``
* Interface Definition: :download:`avalon_mm_intf.sv <../../hdl-src/avalon_mm_intf.sv>`
* Class: :class:`peakrdl_regblock.cpuif.avalon.Avalon_Cpuif`
* Class: :class:`peakrdl_busdecoder.cpuif.avalon.Avalon_Cpuif`
Flattened inputs/outputs
Flattens the interface into discrete input and output ports.
* Command line: ``--cpuif avalon-mm-flat``
* Class: :class:`peakrdl_regblock.cpuif.avalon.Avalon_Cpuif_flattened`
* Class: :class:`peakrdl_busdecoder.cpuif.avalon.Avalon_Cpuif_flattened`
Implementation Details

4
docs/cpuif/axi4lite.rst
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@@ -12,13 +12,13 @@ The AXI4-Lite CPU interface comes in two i/o port flavors:
SystemVerilog Interface
* Command line: ``--cpuif axi4-lite``
* Interface Definition: :download:`axi4lite_intf.sv <../../hdl-src/axi4lite_intf.sv>`
* Class: :class:`peakrdl_regblock.cpuif.axi4lite.AXI4Lite_Cpuif`
* Class: :class:`peakrdl_busdecoder.cpuif.axi4lite.AXI4Lite_Cpuif`
Flattened inputs/outputs
Flattens the interface into discrete input and output ports.
* Command line: ``--cpuif axi4-lite-flat``
* Class: :class:`peakrdl_regblock.cpuif.axi4lite.AXI4Lite_Cpuif_flattened`
* Class: :class:`peakrdl_busdecoder.cpuif.axi4lite.AXI4Lite_Cpuif_flattened`
Pipelined Performance

12
docs/cpuif/customizing.rst
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@@ -29,7 +29,7 @@ Rather than rewriting a new CPU interface definition, you can extend and adjust
.. code-block:: python
from peakrdl_regblock.cpuif.axi4lite import AXI4Lite_Cpuif
from peakrdl_busdecoder.cpuif.axi4lite import AXI4Lite_Cpuif
class My_AXI4Lite(AXI4Lite_Cpuif):
@property
@@ -45,7 +45,7 @@ Then use your custom CPUIF during export:
.. code-block:: python
exporter = RegblockExporter()
exporter = BusDecoderExporter()
exporter.export(
root, "path/to/output_dir",
cpuif_cls=My_AXI4Lite
@@ -72,7 +72,7 @@ you can define your own.
2. Create a Python class that defines your CPUIF
Extend your class from :class:`peakrdl_regblock.cpuif.CpuifBase`.
Extend your class from :class:`peakrdl_busdecoder.cpuif.CpuifBase`.
Define the port declaration string, and provide a reference to your template file.
3. Use your new CPUIF definition when exporting.
@@ -94,17 +94,17 @@ Via a package's entry point definition
^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
If you are publishing a collection of PeakRDL plugins as an installable Python
package, you can advertise them to PeakRDL using an entry point.
This advertises your custom CPUIF class to the PeakRDL-regblock tool as a plugin
This advertises your custom CPUIF class to the PeakRDL-busdecoder tool as a plugin
that should be loaded, and made available as a command-line option in PeakRDL.
.. code-block:: toml
[project.entry-points."peakrdl_regblock.cpuif"]
[project.entry-points."peakrdl_busdecoder.cpuif"]
my-cpuif = "my_package.my_module:MyCPUIF"
* ``my_package``: The name of your installable Python module
* ``peakrdl-regblock.cpuif``: This is the namespace that PeakRDL-regblock will
* ``peakrdl-busdecoder.cpuif``: This is the namespace that PeakRDL-busdecoder will
search. Any cpuif plugins you create must be enclosed in this namespace in
order to be discovered.
* ``my_package.my_module:MyCPUIF``: This is the import path that

6
docs/cpuif/internal_protocol.rst
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@@ -3,9 +3,9 @@
Internal CPUIF Protocol
=======================
Internally, the regblock generator uses a common CPU interface handshake
Internally, the busdecoder generator uses a common CPU interface handshake
protocol. This strobe-based protocol is designed to add minimal overhead to the
regblock implementation, while also being flexible enough to support advanced
busdecoder implementation, while also being flexible enough to support advanced
features of a variety of bus interface standards.
@@ -205,7 +205,7 @@ request until the stall is cleared.
For non-pipelined CPU interfaces that only allow one outstanding transaction at a time,
these stall signals can be safely ignored.
In the following example, the regblock is configured such that:
In the following example, the busdecoder is configured such that:
* A read transaction takes 1 clock cycle to complete
* A write transaction takes 0 clock cycles to complete

4
docs/cpuif/introduction.rst
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@@ -17,9 +17,9 @@ encountered in the design.
Addressing
^^^^^^^^^^
The regblock exporter will always generate its address decoding logic using local
The busdecoder exporter will always generate its address decoding logic using local
address offsets. The absolute address offset of your device shall be
handled by your system interconnect, and present addresses to the regblock that
handled by your system interconnect, and present addresses to the busdecoder that
only include the local offset.
For example, consider a fictional AXI4-Lite device that:

2
docs/cpuif/passthrough.rst
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@@ -5,6 +5,6 @@ This CPUIF mode bypasses the protocol converter stage and directly exposes the
internal CPUIF handshake signals to the user.
* Command line: ``--cpuif passthrough``
* Class: :class:`peakrdl_regblock.cpuif.passthrough.PassthroughCpuif`
* Class: :class:`peakrdl_busdecoder.cpuif.passthrough.PassthroughCpuif`
For more details on the protocol itself, see: :ref:`cpuif_protocol`.

4
docs/dev_notes/template-layers/1.1.hardware-interface
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@@ -42,14 +42,14 @@ Naming Scheme
================================================================================
hwif_out
.my_regblock
.my_busdecoder
.my_reg[X][Y]
.my_field
.value
.anded
hwif_in
.my_regblock
.my_busdecoder
.my_reg[X][Y]
.my_field
.value

4
docs/faq.rst
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@@ -101,7 +101,7 @@ The generated output does not match our organization's coding style
SystemVerilog coding styles vary wildly, and unfortunately there is little
consensus on this topic within the digital design community.
The output generated by PeakRDL-regblock strives to be as human-readable as possible,
The output generated by PeakRDL-busdecoder strives to be as human-readable as possible,
and follow consistent indentation and styling. We do our best to use the most
widely accepted coding style, but since this is a very opinionated space, it is
impossible to satisfy everyone.
@@ -127,5 +127,5 @@ complexity to the tool.
If you encounter a lint violation, please carefully review and consider waiving
it if it does not pose an actual danger. If you still believe it is a problem,
please let us know by `submitting an issue <https://github.com/SystemRDL/PeakRDL-regblock/issues>`_
please let us know by `submitting an issue <https://github.com/SystemRDL/PeakRDL-busdecoder/issues>`_
that describes the problem.

20
docs/index.rst
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@@ -1,7 +1,7 @@
Introduction
============
PeakRDL-regblock is a free and open-source control & status register (CSR) compiler.
PeakRDL-busdecoder is a free and open-source control & status register (CSR) compiler.
This code generator translates your SystemRDL register description into
a synthesizable SystemVerilog RTL module that can be easily instantiated into
your hardware design.
@@ -14,31 +14,31 @@ your hardware design.
Quick Start
-----------
The easiest way to use PeakRDL-regblock is via the `PeakRDL command line tool <https://peakrdl.readthedocs.io/>`_:
The easiest way to use PeakRDL-busdecoder is via the `PeakRDL command line tool <https://peakrdl.readthedocs.io/>`_:
.. code-block:: bash
# Install PeakRDL-regblock along with the command-line tool
python3 -m pip install peakrdl-regblock[cli]
# Install PeakRDL-busdecoder along with the command-line tool
python3 -m pip install peakrdl-busdecoder[cli]
# Export!
peakrdl regblock atxmega_spi.rdl -o regblock/ --cpuif axi4-lite
peakrdl busdecoder atxmega_spi.rdl -o busdecoder/ --cpuif axi4-lite
Looking for VHDL?
-----------------
This project generates SystemVerilog RTL. If you prefer using VHDL, check out
the sister project which aims to be a feature-equivalent fork of
PeakRDL-regblock: `PeakRDL-regblock-VHDL <https://peakrdl-regblock-vhdl.readthedocs.io>`_
PeakRDL-busdecoder: `PeakRDL-busdecoder-VHDL <https://peakrdl-busdecoder-vhdl.readthedocs.io>`_
Links
-----
- `Source repository <https://github.com/SystemRDL/PeakRDL-regblock>`_
- `Release Notes <https://github.com/SystemRDL/PeakRDL-regblock/releases>`_
- `Issue tracker <https://github.com/SystemRDL/PeakRDL-regblock/issues>`_
- `PyPi <https://pypi.org/project/peakrdl-regblock>`_
- `Source repository <https://github.com/SystemRDL/PeakRDL-busdecoder>`_
- `Release Notes <https://github.com/SystemRDL/PeakRDL-busdecoder/releases>`_
- `Issue tracker <https://github.com/SystemRDL/PeakRDL-busdecoder/issues>`_
- `PyPi <https://pypi.org/project/peakrdl-busdecoder>`_
- `SystemRDL Specification <http://accellera.org/downloads/standards/systemrdl>`_

12
docs/licensing.rst
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@@ -1,9 +1,9 @@
Licensing
=========
Re-distribution of the PeakRDL-regblock code generator tool shall adhere to the
Re-distribution of the PeakRDL-busdecoder code generator tool shall adhere to the
terms outlined by the GNU LGPL v3 license. For a copy of the license, see:
https://github.com/SystemRDL/PeakRDL-regblock/blob/main/LICENSE
https://github.com/SystemRDL/PeakRDL-busdecoder/blob/main/LICENSE
Why LGPLv3?
@@ -23,19 +23,19 @@ explicitly mentioned in the exemptions below.
What is exempt from the LGPLv3 license?
---------------------------------------
Don't worry. Not everything that the PeakRDL-regblock project touches is
Don't worry. Not everything that the PeakRDL-busdecoder project touches is
considered LGPLv3 code.
The following are exempt and are free to use with no restrictions:
* Any code that is generated using PeakRDL-regblock is 100% yours. Since it
was derived from your regblock definition, it remains yours. You can
* Any code that is generated using PeakRDL-busdecoder is 100% yours. Since it
was derived from your busdecoder definition, it remains yours. You can
distribute it freely, use it in a proprietary ASIC, sell it as part of an
IP, whatever.
* Any code snippets in this documentation can be freely copy/pasted. These are
examples that are intended for this purpose.
* All reference files that are downloadable from this documentation, which are
also available in the `hdl-src folder in the repository <https://github.com/SystemRDL/PeakRDL-regblock/tree/main/hdl-src>`_
also available in the `hdl-src folder in the repository <https://github.com/SystemRDL/PeakRDL-busdecoder/tree/main/hdl-src>`_
Can I use this as part of my company's internally developed tools?

2
docs/limitations.rst
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@@ -15,7 +15,7 @@ Unaligned Registers
-------------------
All address offsets & strides shall be a multiple of the cpuif bus width used. Specifically:
* Bus width is inferred by the maximum accesswidth used in the regblock.
* Bus width is inferred by the maximum accesswidth used in the busdecoder.
* Each component's address and array stride shall be aligned to the bus width.

2
docs/props/addrmap.rst
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@@ -2,7 +2,7 @@ Addrmap/Regfile Properties
==========================
.. note:: Any properties not explicitly listed here are either implicitly
supported, or are not relevant to the regblock exporter and are ignored.
supported, or are not relevant to the busdecoder exporter and are ignored.
errextbus

2
docs/props/field.rst
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@@ -2,7 +2,7 @@ Field Properties
================
.. note:: Any properties not explicitly listed here are either implicitly
supported, or are not relevant to the regblock exporter and are ignored.
supported, or are not relevant to the busdecoder exporter and are ignored.
Software Access Properties
--------------------------

2
docs/props/reg.rst
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@@ -2,7 +2,7 @@ Register Properties
===================
.. note:: Any properties not explicitly listed here are either implicitly
supported, or are not relevant to the regblock exporter and are ignored.
supported, or are not relevant to the busdecoder exporter and are ignored.
accesswidth
-----------

4
docs/props/signal.rst
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@@ -2,7 +2,7 @@ Signal Properties
=================
.. note:: Any properties not explicitly listed here are either implicitly
supported, or are not relevant to the regblock exporter and are ignored.
supported, or are not relevant to the busdecoder exporter and are ignored.
activehigh/activelow
@@ -19,7 +19,7 @@ Ignored in all other contexts.
cpuif_reset
-----------
Specify that this signal shall be used as alternate reset signal for the CPU
interface for this regblock.
interface for this busdecoder.
field_reset

8
docs/rdl_features/external.rst
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@@ -1,9 +1,9 @@
External Components
===================
SystemRDL allows some component instances to be defined as "external" elements
of an address space definition. In the context of this regblock generator,
of an address space definition. In the context of this busdecoder generator,
the implementation of an external component is left up to the designer. When
generating the RTL for a regblock, the implementations of external components
generating the RTL for a busdecoder, the implementations of external components
are omitted and instead a user-interface is presented on the
``hwif_in``/``hwif_out`` i/o structs.
@@ -16,7 +16,7 @@ Things you should know
* By default external ``hwif_out`` signals are driven combinationally. An
optional output retiming stage can be enabled if needed.
* Due to the uncertain access latency of external components, the regblock will
* Due to the uncertain access latency of external components, the busdecoder will
only issue one outstanding transaction to an external component at a time.
This is enforced even if the CPUIF is capable of pipelined accesses such as
AXI4-Lite.
@@ -109,7 +109,7 @@ Broader external address regions can be represented by external block-like
components such as ``addrmap``, ``regfile`` or ``mem`` elements.
To ensure address decoding for external blocks is simple (only requires simple bit-pruning),
blocks that are external to an exported regblock shall be aligned to their size.
blocks that are external to an exported busdecoder shall be aligned to their size.
Request
^^^^^^^

4
docs/udps/extended_swacc.rst
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@@ -15,9 +15,9 @@ functionality.
Properties
----------
These UDP definitions, along with others supported by PeakRDL-regblock can be
These UDP definitions, along with others supported by PeakRDL-busdecoder can be
enabled by compiling the following file along with your design:
:download:`regblock_udps.rdl <../../hdl-src/regblock_udps.rdl>`.
:download:`busdecoder_udps.rdl <../../hdl-src/busdecoder_udps.rdl>`.
.. describe:: rd_swacc

8
docs/udps/fixedpoint.rst
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@@ -11,21 +11,21 @@ for each number, unlike for floating-point numbers.
For this SystemVerilog exporter, these properties only affect the signal type in
the the ``hwif`` structs. There is no special handling in the internals of
the regblock.
the busdecoder.
Properties
----------
Fields can be declared as fixed-point numbers using the following two properties:
.. literalinclude:: ../../hdl-src/regblock_udps.rdl
.. literalinclude:: ../../hdl-src/busdecoder_udps.rdl
:lines: 46-54
The :ref:`is_signed<signed>` property can be used in conjunction with these
properties to declare signed fixed-point fields.
These UDP definitions, along with others supported by PeakRDL-regblock, can be
These UDP definitions, along with others supported by PeakRDL-busdecoder, can be
enabled by compiling the following file along with your design:
:download:`regblock_udps.rdl <../../hdl-src/regblock_udps.rdl>`.
:download:`busdecoder_udps.rdl <../../hdl-src/busdecoder_udps.rdl>`.
.. describe:: intwidth

4
docs/udps/intro.rst
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@@ -5,11 +5,11 @@ Although the official SystemRDL spec defines numerous properties that allow you
to define complex register map structures, sometimes they are not enough to
accurately describe a necessary feature. Fortunately the SystemRDL spec allows
the language to be extended using "User Defined Properties" (UDPs). The
PeakRDL-regblock tool understands several UDPs that are described in this
PeakRDL-busdecoder tool understands several UDPs that are described in this
section.
To enable these UDPs, compile this RDL file prior to the rest of your design:
:download:`regblock_udps.rdl <../../hdl-src/regblock_udps.rdl>`.
:download:`busdecoder_udps.rdl <../../hdl-src/busdecoder_udps.rdl>`.
.. list-table:: Summary of UDPs
:header-rows: 1

6
docs/udps/read_buffering.rst
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@@ -24,12 +24,12 @@ Properties
The behavior of read-buffered registers is defined using the following two
properties:
.. literalinclude:: ../../hdl-src/regblock_udps.rdl
.. literalinclude:: ../../hdl-src/busdecoder_udps.rdl
:lines: 10-18
These UDP definitions, along with others supported by PeakRDL-regblock can be
These UDP definitions, along with others supported by PeakRDL-busdecoder can be
enabled by compiling the following file along with your design:
:download:`regblock_udps.rdl <../../hdl-src/regblock_udps.rdl>`.
:download:`busdecoder_udps.rdl <../../hdl-src/busdecoder_udps.rdl>`.
.. describe:: buffer_reads

8
docs/udps/signed.rst
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@@ -8,18 +8,18 @@ The ``is_signed`` user-defined property fills this need.
For this SystemVerilog exporter, marking a field as signed only affects the
signal type in the ``hwif`` structs. There is no special handling in the internals
of the regblock.
of the busdecoder.
Properties
----------
A field can be marked as signed using the following user-defined property:
.. literalinclude:: ../../hdl-src/regblock_udps.rdl
.. literalinclude:: ../../hdl-src/busdecoder_udps.rdl
:lines: 40-44
This UDP definition, along with others supported by PeakRDL-regblock, can be
This UDP definition, along with others supported by PeakRDL-busdecoder, can be
enabled by compiling the following file along with your design:
:download:`regblock_udps.rdl <../../hdl-src/regblock_udps.rdl>`.
:download:`busdecoder_udps.rdl <../../hdl-src/busdecoder_udps.rdl>`.
.. describe:: is_signed

10
docs/udps/write_buffering.rst
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@@ -4,8 +4,8 @@ Write-buffered Registers
========================
In order to support larger software write accesses that are atomic, the
regblock generator understands several UDPs that implement write-buffering to
specific registers. This causes the regblock to delay the effect of a software
busdecoder generator understands several UDPs that implement write-buffering to
specific registers. This causes the busdecoder to delay the effect of a software
write operation until a defined trigger event.
Some examples of when this is useful:
@@ -30,12 +30,12 @@ Properties
The behavior of write-buffered registers is defined using the following two
properties:
.. literalinclude:: ../../hdl-src/regblock_udps.rdl
.. literalinclude:: ../../hdl-src/busdecoder_udps.rdl
:lines: 20-28
These UDP definitions, along with others supported by PeakRDL-regblock can be
These UDP definitions, along with others supported by PeakRDL-busdecoder can be
enabled by compiling the following file along with your design:
:download:`regblock_udps.rdl <../../hdl-src/regblock_udps.rdl>`.
:download:`busdecoder_udps.rdl <../../hdl-src/busdecoder_udps.rdl>`.
.. describe:: buffer_writes