regblock -> busdecoder

docs/cpuif/apb.rst

@@ -29,13 +29,13 @@ The APB3 CPU interface comes in two i/o port flavors:
 SystemVerilog Interface
     * Command line: ``--cpuif apb3``
     * Interface Definition: :download:`apb3_intf.sv <../../hdl-src/apb3_intf.sv>`
-    * Class: :class:`peakrdl_regblock.cpuif.apb3.APB3_Cpuif`
+    * Class: :class:`peakrdl_busdecoder.cpuif.apb3.APB3_Cpuif`
 
 Flattened inputs/outputs
     Flattens the interface into discrete input and output ports.
 
     * Command line: ``--cpuif apb3-flat``
-    * Class: :class:`peakrdl_regblock.cpuif.apb3.APB3_Cpuif_flattened`
+    * Class: :class:`peakrdl_busdecoder.cpuif.apb3.APB3_Cpuif_flattened`
 
 
 APB4
@@ -50,10 +50,10 @@ The APB4 CPU interface comes in two i/o port flavors:
 SystemVerilog Interface
     * Command line: ``--cpuif apb4``
     * Interface Definition: :download:`apb4_intf.sv <../../hdl-src/apb4_intf.sv>`
-    * Class: :class:`peakrdl_regblock.cpuif.apb4.APB4_Cpuif`
+    * Class: :class:`peakrdl_busdecoder.cpuif.apb4.APB4_Cpuif`
 
 Flattened inputs/outputs
     Flattens the interface into discrete input and output ports.
 
     * Command line: ``--cpuif apb4-flat``
-    * Class: :class:`peakrdl_regblock.cpuif.apb4.APB4_Cpuif_flattened`
+    * Class: :class:`peakrdl_busdecoder.cpuif.apb4.APB4_Cpuif_flattened`

docs/cpuif/avalon.rst

@@ -10,13 +10,13 @@ The Avalon interface comes in two i/o port flavors:
 SystemVerilog Interface
     * Command line: ``--cpuif avalon-mm``
     * Interface Definition: :download:`avalon_mm_intf.sv <../../hdl-src/avalon_mm_intf.sv>`
-    * Class: :class:`peakrdl_regblock.cpuif.avalon.Avalon_Cpuif`
+    * Class: :class:`peakrdl_busdecoder.cpuif.avalon.Avalon_Cpuif`
 
 Flattened inputs/outputs
     Flattens the interface into discrete input and output ports.
 
     * Command line: ``--cpuif avalon-mm-flat``
-    * Class: :class:`peakrdl_regblock.cpuif.avalon.Avalon_Cpuif_flattened`
+    * Class: :class:`peakrdl_busdecoder.cpuif.avalon.Avalon_Cpuif_flattened`
 
 
 Implementation Details

docs/cpuif/axi4lite.rst

@@ -12,13 +12,13 @@ The AXI4-Lite CPU interface comes in two i/o port flavors:
 SystemVerilog Interface
     * Command line: ``--cpuif axi4-lite``
     * Interface Definition: :download:`axi4lite_intf.sv <../../hdl-src/axi4lite_intf.sv>`
-    * Class: :class:`peakrdl_regblock.cpuif.axi4lite.AXI4Lite_Cpuif`
+    * Class: :class:`peakrdl_busdecoder.cpuif.axi4lite.AXI4Lite_Cpuif`
 
 Flattened inputs/outputs
     Flattens the interface into discrete input and output ports.
 
     * Command line: ``--cpuif axi4-lite-flat``
-    * Class: :class:`peakrdl_regblock.cpuif.axi4lite.AXI4Lite_Cpuif_flattened`
+    * Class: :class:`peakrdl_busdecoder.cpuif.axi4lite.AXI4Lite_Cpuif_flattened`
 
 
 Pipelined Performance

docs/cpuif/customizing.rst

@@ -29,7 +29,7 @@ Rather than rewriting a new CPU interface definition, you can extend and adjust
 
 .. code-block:: python
 
-    from peakrdl_regblock.cpuif.axi4lite import AXI4Lite_Cpuif
+    from peakrdl_busdecoder.cpuif.axi4lite import AXI4Lite_Cpuif
 
     class My_AXI4Lite(AXI4Lite_Cpuif):
         @property
@@ -45,7 +45,7 @@ Then use your custom CPUIF during export:
 
 .. code-block:: python
 
-   exporter = RegblockExporter()
+   exporter = BusDecoderExporter()
    exporter.export(
       root, "path/to/output_dir",
       cpuif_cls=My_AXI4Lite
@@ -72,7 +72,7 @@ you can define your own.
 
 2. Create a Python class that defines your CPUIF
 
-    Extend your class from :class:`peakrdl_regblock.cpuif.CpuifBase`.
+    Extend your class from :class:`peakrdl_busdecoder.cpuif.CpuifBase`.
     Define the port declaration string, and provide a reference to your template file.
 
 3. Use your new CPUIF definition when exporting.
@@ -94,17 +94,17 @@ Via a package's entry point definition
 ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
 If you are publishing a collection of PeakRDL plugins as an installable Python
 package, you can advertise them to PeakRDL using an entry point.
-This advertises your custom CPUIF class to the PeakRDL-regblock tool as a plugin
+This advertises your custom CPUIF class to the PeakRDL-busdecoder tool as a plugin
 that should be loaded, and made available as a command-line option in PeakRDL.
 
 .. code-block:: toml
 
-    [project.entry-points."peakrdl_regblock.cpuif"]
+    [project.entry-points."peakrdl_busdecoder.cpuif"]
     my-cpuif = "my_package.my_module:MyCPUIF"
 
 
 *   ``my_package``: The name of your installable Python module
-*   ``peakrdl-regblock.cpuif``: This is the namespace that PeakRDL-regblock will
+*   ``peakrdl-busdecoder.cpuif``: This is the namespace that PeakRDL-busdecoder will
     search. Any cpuif plugins you create must be enclosed in this namespace in
     order to be discovered.
 *   ``my_package.my_module:MyCPUIF``: This is the import path that

docs/cpuif/internal_protocol.rst

@@ -3,9 +3,9 @@
 Internal CPUIF Protocol
 =======================
 
-Internally, the regblock generator uses a common CPU interface handshake
+Internally, the busdecoder generator uses a common CPU interface handshake
 protocol. This strobe-based protocol is designed to add minimal overhead to the
-regblock implementation, while also being flexible enough to support advanced
+busdecoder implementation, while also being flexible enough to support advanced
 features of a variety of bus interface standards.
 
 
@@ -205,7 +205,7 @@ request until the stall is cleared.
 For non-pipelined CPU interfaces that only allow one outstanding transaction at a time,
 these stall signals can be safely ignored.
 
-In the following example, the regblock is configured such that:
+In the following example, the busdecoder is configured such that:
 
 * A read transaction takes 1 clock cycle to complete
 * A write transaction takes 0 clock cycles to complete

docs/cpuif/introduction.rst

@@ -17,9 +17,9 @@ encountered in the design.
 Addressing
 ^^^^^^^^^^
 
-The regblock exporter will always generate its address decoding logic using local
+The busdecoder exporter will always generate its address decoding logic using local
 address offsets. The absolute address offset of your device shall be
-handled by your system interconnect, and present addresses to the regblock that
+handled by your system interconnect, and present addresses to the busdecoder that
 only include the local offset.
 
 For example, consider a fictional AXI4-Lite device that:

docs/cpuif/passthrough.rst

@@ -5,6 +5,6 @@ This CPUIF mode bypasses the protocol converter stage and directly exposes the
 internal CPUIF handshake signals to the user.
 
 * Command line: ``--cpuif passthrough``
-* Class: :class:`peakrdl_regblock.cpuif.passthrough.PassthroughCpuif`
+* Class: :class:`peakrdl_busdecoder.cpuif.passthrough.PassthroughCpuif`
 
 For more details on the protocol itself, see: :ref:`cpuif_protocol`.