Commit Graph

21 Commits

Author SHA1 Message Date
Sebastien Baillou
efbddccc54 fix: handle error response for overlapped registers with read-only and write-only attributes (#178) 2025-11-15 19:33:21 -08:00
Alex Mykyta
529c4df98c Move port list generation out of Jinja template. #125, #153 2025-10-25 20:19:15 -07:00
sbaillou
d69af23be5 Error response for unmapped address or forbidden read/write access (#168)
* feat: add ability to enable error output on the cpuif, when decoding errors occur (generate_cpuif_err in API).

* fix: move signal to new place (after automatic vers)

* feat: add info about new api (generate_cpuif_err)

* fix: repair readback with latency

* Adding generate_cpuif_err argument to peakrdl-regblock to generate cpuif error response, when the address is decoded incorrectly

* add sw rd or/and wr attribure error response related and add error respone for external mem

* add sw rd or/and wr error response test

* add sw rd or/and wr error response for external register test and fix generation of rtl logic for external register

* add sw rd or/and wr error response for external mem test

* add sw rd or/and wr error response for apb3 imterfaces driver

* add error response test for APB4, AXI4Lite and Avalon interfaces

* rename --generate_cpuif_err to --generate-cpuif-err

* style: minor typo fixes and test clean-up

* refactor: move expected error check inside write/read functions

* feat: add error response check to OBI testbench interface

* feat: split generate-cpuif-err option into err-if-bad-addr and err-if-bad-rw options

* feat: add err_if_bad_addr/rw to cfg_schema

* feat: extend cpuif_err_rsp test to cover all combinations of bad_addr/bad_rw

* style: lint fixes

* fix: removed redundant if node.external condition to help coverage

* Fix dangling hwif_in signals in testcase

---------

Co-authored-by: Denis Trifonov <d.trifonov@yadro.com>
Co-authored-by: Dominik Tanous <tanous@kandou.com>
Co-authored-by: Sebastien Baillou <baillou@kandou.com>
Co-authored-by: Alex Mykyta <amykyta3@users.noreply.github.com>
2025-10-25 18:22:15 -07:00
Alex Mykyta
588e1fee66 Add names to assertions. #151 2025-07-16 10:12:46 -07:00
Alex Mykyta
faa57c93b9 Add preprocessor ifndef around RTL assertions to allow exclusion. #104 2024-12-17 22:31:30 -08:00
Alex Mykyta
4dfd9b10d6 Add support for CPUIFs to have parameters #80 2024-03-29 22:39:45 -07:00
Alex Mykyta
555efdfcc0 Remove use of in-scope initial assignments to automatics to work around bug in Spyglass lint tool. #87 2024-03-20 19:57:50 -07:00
Alex Mykyta
0d39774d22 Fixup whitespace 2024-01-05 21:12:25 -08:00
Alex Mykyta
ad7b09a2f5 Remove implication operator to avoid xsim compatibility limitation. #57 2023-09-07 22:42:42 -07:00
Alex Mykyta
8a6f525ee2 Add assertion for rogue external ack strobes. Clarify recommended external ack tieoff. #57 2023-08-01 20:40:14 -07:00
Alex Mykyta
0d82154b9d Add support for field paritycheck. #35 2023-05-15 22:53:17 -07:00
Alex Mykyta
3e691cb5fb Fix bug where small designs with 3 or less sw readable addresses and readback retiming enabled generate incorrect output. 2023-05-14 22:46:23 -07:00
Alex Mykyta
b350da3e7c Add ability to control default reset style. #34 2023-05-13 17:15:31 -07:00
Alex Mykyta
5e76956618 Refactor exporter class to clean up the mess of random variables 2023-05-12 23:44:09 -07:00
Alex Mykyta
ca9185dac7 Add support for external components. (#4 & #36) 2023-05-11 21:52:26 -07:00
Alex Mykyta
9e76a712a7 Implement read buffering. (#22) 2022-11-06 23:28:07 -08:00
Alex Mykyta
279a3c5788 Implement write buffering (#22) 2022-10-29 22:02:04 -07:00
Alex Mykyta
808067fac9 Fix synthesizability of fields with msb0 ordering 2022-10-17 23:24:35 -07:00
Alex Mykyta
6e4246a2cc Add support for cpuif that have write strobes 2022-09-13 22:03:54 -07:00
Alex Mykyta
135b717486 Add identifier filter. closes #14 2022-07-20 23:35:17 -07:00
Alex Mykyta
8d13a9d7fe Switch to use regular non-namespaced package 2022-06-09 20:24:53 -07:00