bslathi19/PeakRDL-regblock
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bb2fead71a8a9e9e37cd355adff8886fbf52ec19
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104 Commits

Author SHA1 Message Date
Alex Mykyta
3ed2e1f891 Simplify stickybit implementation for single-bit fields to not create redundant expression. #127 2025-03-07 19:45:31 -08:00
Alex Mykyta
6430dd4914 Emit error if field that is asynchronously reset uses a dynamic reset value. #129 2025-03-07 19:20:44 -08:00
Alex Mykyta
d3cd51f500 Fix missing error message if multiple unconditional field assignments are inferred. #93 2025-03-06 22:12:26 -08:00
Alex Mykyta
f882e155d1 remove dead-code 2025-03-06 22:08:47 -08:00
Alex Mykyta
c53b11cf28 Add more specificity to stickybit conditional class 2025-03-06 21:24:49 -08:00
Alex Mykyta
40687abd6b Type hinting cleanup 2025-03-03 21:37:07 -08:00
Alex Mykyta
0258cac186 drop py3.6. Misc housekeeping 2025-03-03 21:37:07 -08:00
Aylon Chaim Porat
28ed82129f Add Addressmap block size to generated package (#134) 
* add map size as a localparam in rdl map package

* rename from _SIZE -> _BYTES_SIZE

* fix names on new test & localparam

* wrap map size in SVInt
 2025-03-03 21:16:25 -08:00
Alex Mykyta
aba2af17af Increment version 2024-12-19 21:53:12 -08:00
Alex Mykyta
8d82eb29d9 Add width cast to address decode loop iterators. #92 2024-12-19 21:49:23 -08:00
Alex Mykyta
e788e7cafd Remove excessive secondary counter saturation clamping logic. Counters will now be allowed to be set to values beyond their saturation point if loaded through non-increment/decrement mechanism. #114 2024-12-19 21:41:20 -08:00
Alex Mykyta
a15178c719 Use clog2 helper function to improve clarity. #116 2024-12-19 19:47:41 -08:00
Alex Mykyta
80a46a082b Fix incorrect address width calculation for external blocks. #116 2024-12-19 19:40:57 -08:00
Alex Mykyta
5f9d7308c2 Add next_q storage element to reset clause to avoid synthesis issues with async resets. #113 2024-12-19 19:30:30 -08:00
Alex Mykyta
1d7d47f49c More type hint workarounds 2024-12-18 22:20:35 -08:00
Alex Mykyta
5c1bc35799 Type hint workarounds 2024-12-18 22:13:51 -08:00
Alex Mykyta
e0295ae526 Fixup test bitswap. mypy 2024-12-18 22:04:12 -08:00
Alex Mykyta
11d9f65dff Fix incorrect bit-order in packed struct output of external registers. #111 2024-12-18 21:17:31 -08:00
Alex Mykyta
399f942201 Fix doc typos 2024-12-18 20:29:17 -08:00
Alex Mykyta
faa57c93b9 Add preprocessor ifndef around RTL assertions to allow exclusion. #104 2024-12-17 22:31:30 -08:00
Alex Mykyta
a076609dad version 2024-03-31 22:21:54 -07:00
Alex Mykyta
4dfd9b10d6 Add support for CPUIFs to have parameters #80 2024-03-29 22:39:45 -07:00
Alex Mykyta
f25ba60bfc Add packed struct overlay for external register bitfields. #84 2024-03-29 22:16:24 -07:00
Alex Mykyta
840b54c6e1 Use explicit logic type for user enum declarations. #91 2024-03-29 21:22:34 -07:00
Alex Mykyta
653d4efc73 version 2024-03-20 20:02:40 -07:00
Alex Mykyta
555efdfcc0 Remove use of in-scope initial assignments to automatics to work around bug in Spyglass lint tool. #87 2024-03-20 19:57:50 -07:00
Aylon Chaim Porat
cf2be63c20 read_buffering & write_buffering: get_trigger's accesswidth and regwidth should be taken from trigger when trigger is of RegNode type, not from node 2024-03-20 19:15:33 -07:00
motchy
be8d84bba0 fix: a typo in SV template 2024-03-10 11:46:28 -07:00
Alex Mykyta
0d39774d22 Fixup whitespace 2024-01-05 21:12:25 -08:00
Alex Mykyta
6a550abc69 Fix accidental blocking assignment in always_ff for read buffering storage elements 2024-01-05 19:57:47 -08:00
Alex Mykyta
2fedef64aa Add validation check for write buffered registers that trigger off of their own field. #39 2023-10-25 21:54:01 -07:00
Alex Mykyta
62518b318b Implement new SVInt object to defer literal expansion and allow bit-fiddling operations. Fix invalid bit-slicing of literals if field reset value is a constant. #71 2023-10-24 22:50:41 -07:00
Alex Mykyta
683fc4d0ac Update version 2023-10-11 22:04:34 -07:00
Alex Mykyta
0da6efe85c Fix hwif type name generation to properly handle parameterized component names. #70 2023-10-11 21:58:10 -07:00
Alex Mykyta
333853b925 Fix axi4-lite write strobe width. #68 2023-09-28 21:18:11 -07:00
Alex Mykyta
639cafc28b Fix always_ff generation for non-reset fields and async default reset. #63 2023-09-07 23:36:47 -07:00
Alex Mykyta
ad7b09a2f5 Remove implication operator to avoid xsim compatibility limitation. #57 2023-09-07 22:42:42 -07:00
Alex Mykyta
49db496ac1 Add parameters for data and addr width to package output 2023-08-24 20:44:16 -07:00
Alex Mykyta
280c3aad17 Discard LSbs of address for AXI4-Lite CPUIF to properly handle unaligned transfers. #60 2023-08-24 20:36:28 -07:00
Alex Mykyta
5c3dd6e6bb More test coverage 2023-08-03 22:18:55 -07:00
Alex Mykyta
f9e0d1babc Coverage improvements 2023-08-02 22:28:42 -07:00
Alex Mykyta
941871007b Omit unecessary hwif signals if an external register is read-only or write-only. #58 2023-08-02 21:38:06 -07:00
Alex Mykyta
8a6f525ee2 Add assertion for rogue external ack strobes. Clarify recommended external ack tieoff. #57 2023-08-01 20:40:14 -07:00
Alex Mykyta
f884b91852 version 2023-07-19 21:02:10 -07:00
Alex Mykyta
211224116e Clean up ugly unconditional 'if(1)' conditionals in field logic. #50 2023-07-19 20:49:38 -07:00
Alex Mykyta
da8ff4aaeb Make remaining interrupt conditional predicates single-bit. #54 2023-07-19 20:17:46 -07:00
Alex Mykyta
18f8f358b2 Make stickybit conditional predicate a single-bit result rather than a vector. #54 2023-07-18 21:50:51 -07:00
Alex Mykyta
60513b9730 version 2023-06-28 22:28:06 -07:00
Alex Mykyta
1f193e87eb Fix edge case if exporting a block that contains no internal registers. #53 2023-06-28 22:24:10 -07:00
Alex Mykyta
b056a443f1 Use sized integer literals in comparisons. #49 2023-06-14 21:58:41 -07:00