Trace FST

pyproject.toml

@@ -35,7 +35,7 @@ name = "fpga-sim"  # REQUIRED, is the only field that cannot be marked as dynami
 # https://packaging.python.org/guides/single-sourcing-package-version/
 
 # dynamic = ["version"]
-version = "0.3.2"  # REQUIRED, although can be dynamic
+version = "dev-0.4.0"  # REQUIRED, although can be dynamic
 
 # This is a one-line description or tagline of what your project does. This
 # corresponds to the "Summary" metadata field:

src/fpga_sim/fpga_sim.py

@@ -98,14 +98,20 @@ def fpga_sim_main():
         verilog_sources = list(filter(lambda s: (s.endswith(".v") or s.endswith(".sv") or s.endswith(".vlt")), sources))
 
 
+        build_args = ["--timing"]
+
+        # By default, verilator only uses vcd instead of fst, but fst is better.
+        if test["waves"]:
+            build_args.append("--trace-fst")
+
         runner.build(
             verilog_sources=verilog_sources,
             includes=incdirs,
             hdl_toplevel=test["toplevel"],
             build_dir=f"{test['base_path']}/sim_build",
-            waves=test["waves"],
+            #waves=test["waves"],
             defines=defines,
-            build_args=["--timing"]
+            build_args=build_args
         )
 
         result_xml = f"../sim_build/{test['name']}_results.xml".replace(" ", "_")