Experimental/incdirs
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@@ -35,7 +35,7 @@ name = "fpga-sim" # REQUIRED, is the only field that cannot be marked as dynami
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# https://packaging.python.org/guides/single-sourcing-package-version/
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# https://packaging.python.org/guides/single-sourcing-package-version/
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# dynamic = ["version"]
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# dynamic = ["version"]
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version = "0.2.2" # REQUIRED, although can be dynamic
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version = "0.3.0" # REQUIRED, although can be dynamic
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# This is a one-line description or tagline of what your project does. This
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# This is a one-line description or tagline of what your project does. This
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# corresponds to the "Summary" metadata field:
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# corresponds to the "Summary" metadata field:
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@@ -123,7 +123,7 @@ classifiers = [
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dependencies = [
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dependencies = [
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"pyyaml",
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"pyyaml",
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"cocotb",
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"cocotb",
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"rtl-manifest"
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"rtl-manifest>=0.3.1"
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]
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]
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# List additional groups of dependencies here (e.g. development
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# List additional groups of dependencies here (e.g. development
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@@ -1,4 +1,8 @@
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-i https://git.byronlathi.com/api/v4/projects/95/packages/pypi/simple
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setuptools
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setuptools
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wheel
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wheel
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build
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build
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twine
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twine
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cocotb
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rtl-manifest
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pyyaml
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@@ -1,5 +1,3 @@
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from ast import parse
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from email.mime import base
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import os
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import os
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import sys
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import sys
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@@ -95,10 +93,11 @@ def fpga_sim_main():
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# Turn this into a multiprocessing pool
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# Turn this into a multiprocessing pool
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for test in tests_to_run:
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for test in tests_to_run:
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sources = rtl_manifest.read_sources(f"{test['base_path']}/{test['sources']}")
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sources, incdirs = rtl_manifest.parse(f"{test['base_path']}/{test['sources']}")
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runner.build(
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runner.build(
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verilog_sources=sources,
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verilog_sources=sources,
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includes=incdirs,
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hdl_toplevel=test["toplevel"],
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hdl_toplevel=test["toplevel"],
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build_dir=f"{test['base_path']}/sim_build",
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build_dir=f"{test['base_path']}/sim_build",
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waves=test["waves"],
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waves=test["waves"],
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