bslathi19/fpga-sim
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Make more generic

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This commit is contained in:
Byron Lathi
2024-11-30 00:21:39 -08:00
parent 624acc3c76
commit 7f88c851ff
1 changed files with 12 additions and 16 deletions
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28
src/fpga_sim/fpga_sim.py
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@@ -1,6 +1,7 @@
from ast import parse
from email.mime import base
import os
import sys
import argparse
@@ -28,18 +29,7 @@ def fpga_sim_main():
with open(args.yaml) as cfg_file:
cfg = yaml.safe_load(cfg_file)
# print(cfg)
# 2: Get source files
repo_top = os.getenv("REPO_TOP")
sources = rtl_manifest.read_sources(f"{repo_top}/src/sources.list") # hack
sources.extend(rtl_manifest.read_sources(f"{repo_top}/sim/sources.list")) # hack
print(sources)
# 3: Figure out which tests to run
# 2: Figure out which tests to run
base_path = os.path.split(os.path.abspath(args.yaml))[0]
print(base_path)
@@ -53,11 +43,14 @@ def fpga_sim_main():
__cfg = yaml.safe_load(_cfg_file)
parse_cfg(__cfg, f"{base_path}/{os.path.split(test["yaml"])[0]}")
if test["type"] == "test":
waves = test["waves"] if "waves" in test else None
tests.append({
"base_path": base_path,
"name": test["name"],
"toplevel": test["toplevel"],
"modules": test["modules"],
"waves": test["waves"],
"waves": waves,
"sources": test["sources"]
})
parse_cfg(cfg, base_path)
@@ -75,15 +68,18 @@ def fpga_sim_main():
for test in tests:
sources = rtl_manifest.read_sources(f"{test["base_path"]}/{test["sources"]}")
runner.build(
verilog_sources=sources,
hdl_toplevel=test["toplevel"],
always=True,
clean=True,
build_dir=f"{test["base_path"]}/sim_build",
waves=test["waves"]
)
result_xml = f"../results/{test["name"]}_results.xml".replace(" ", "_")
result_xml = f"../sim_build/{test["name"]}_results.xml".replace(" ", "_")
sys.path.append(test["base_path"])
runner.test(hdl_toplevel=test["toplevel"], test_module=test["modules"], waves=test["waves"], results_xml=result_xml)