Rework what the yamls look like

pyproject.toml

@@ -35,7 +35,7 @@ name = "fpga-sim"  # REQUIRED, is the only field that cannot be marked as dynami
 # https://packaging.python.org/guides/single-sourcing-package-version/
 
 # dynamic = ["version"]
-version = "0.0.6"  # REQUIRED, although can be dynamic
+version = "0.1.0"  # REQUIRED, although can be dynamic
 
 # This is a one-line description or tagline of what your project does. This
 # corresponds to the "Summary" metadata field:

src/fpga_sim/fpga_sim.py

@@ -35,22 +35,39 @@ def fpga_sim_main():
 
     tests = []
 
+    defines = {}
+
     def parse_cfg(_cfg, _base_path=None):
-        for test in _cfg:
-            if test["type"] == "yaml":
-                with open(f"{_base_path}/{test["yaml"]}") as _cfg_file:
+        if "yaml" in _cfg:
+            for sub_yaml in _cfg["yaml"]:
+                print(sub_yaml)
+                with open(f"{_base_path}/{sub_yaml}") as _cfg_file:
                     __cfg = yaml.safe_load(_cfg_file)
-                    parse_cfg(__cfg, f"{_base_path}/{os.path.split(test["yaml"])[0]}")
-            if test["type"] == "test":
-                waves = test["waves"] if "waves" in test else None
+                    print(f"Base Path: {_base_path}/{os.path.split(sub_yaml)[0]}")
+                    parse_cfg(__cfg, f"{_base_path}/{os.path.split(sub_yaml)[0]}")
+
+        if "tests" in _cfg:
+            for test in _cfg["tests"]:
+                print(test)
+                if "waves" not in test:
+                    waves = False
+                else:
+                    waves = test["waves"]
+                
                 tests.append({
-                        "base_path": _base_path,
-                        "name": test["name"],
-                        "toplevel": test["toplevel"],
-                        "modules": test["modules"],
-                        "waves": waves,
-                        "sources": test["sources"]
-                    })
+                    "base_path": _base_path,
+                    "name": test["name"],
+                    "toplevel": test["toplevel"],
+                    "modules": test["modules"],
+                    "waves": waves,
+                    "sources": test["sources"]
+                })
+
+        if "defines" in _cfg:
+            cfg_defines = _cfg["defines"]
+            for define in cfg_defines:
+                print(f"{define}: {cfg_defines[define]}, {os.path.expandvars(cfg_defines[define])}")
+                defines[define] = os.path.expandvars(cfg_defines[define])
 
     parse_cfg(cfg, base_path)
 
@@ -60,6 +77,8 @@ def fpga_sim_main():
 
     os.environ["MAKEFLAGS"] = "-j"
 
+
+    # Turn this into a multiprocessing pool
     for test in tests:
 
         sources = rtl_manifest.read_sources(f"{test["base_path"]}/{test["sources"]}")
@@ -68,7 +87,8 @@ def fpga_sim_main():
             verilog_sources=sources,
             hdl_toplevel=test["toplevel"],
             build_dir=f"{test["base_path"]}/sim_build",
-            waves=test["waves"]
+            waves=test["waves"],
+            defines=defines
         )
 
         result_xml = f"../sim_build/{test["name"]}_results.xml".replace(" ", "_")