bslathi19/fpga-sim
1
0
Fork 0
Code Issues Pull Requests Actions Packages Projects Releases Wiki Activity

Rework what the yamls look like

Browse Source
This commit is contained in:
Byron Lathi
2024-12-01 11:23:35 -08:00
parent dbbf458ee9
commit d03e7a127b
2 changed files with 35 additions and 15 deletions
Download Patch File Download Diff File Expand all files Collapse all files

2
pyproject.toml
View File

@@ -35,7 +35,7 @@ name = "fpga-sim" # REQUIRED, is the only field that cannot be marked as dynami
# https://packaging.python.org/guides/single-sourcing-package-version/ # https://packaging.python.org/guides/single-sourcing-package-version/
# dynamic = ["version"] # dynamic = ["version"]
version = "0.0.6" # REQUIRED, although can be dynamic version = "0.1.0" # REQUIRED, although can be dynamic
# This is a one-line description or tagline of what your project does. This # This is a one-line description or tagline of what your project does. This
# corresponds to the "Summary" metadata field: # corresponds to the "Summary" metadata field:

48
src/fpga_sim/fpga_sim.py
View File

@@ -35,22 +35,39 @@ def fpga_sim_main():
tests = [] tests = []
defines = {}
def parse_cfg(_cfg, _base_path=None): def parse_cfg(_cfg, _base_path=None):
for test in _cfg: if "yaml" in _cfg:
if test["type"] == "yaml": for sub_yaml in _cfg["yaml"]:
with open(f"{_base_path}/{test["yaml"]}") as _cfg_file: print(sub_yaml)
with open(f"{_base_path}/{sub_yaml}") as _cfg_file:
__cfg = yaml.safe_load(_cfg_file) __cfg = yaml.safe_load(_cfg_file)
parse_cfg(__cfg, f"{_base_path}/{os.path.split(test["yaml"])[0]}") print(f"Base Path: {_base_path}/{os.path.split(sub_yaml)[0]}")
if test["type"] == "test": parse_cfg(__cfg, f"{_base_path}/{os.path.split(sub_yaml)[0]}")
waves = test["waves"] if "waves" in test else None
if "tests" in _cfg:
for test in _cfg["tests"]:
print(test)
if "waves" not in test:
waves = False
else:
waves = test["waves"]
tests.append({ tests.append({
"base_path": _base_path, "base_path": _base_path,
"name": test["name"], "name": test["name"],
"toplevel": test["toplevel"], "toplevel": test["toplevel"],
"modules": test["modules"], "modules": test["modules"],
"waves": waves, "waves": waves,
"sources": test["sources"] "sources": test["sources"]
}) })
if "defines" in _cfg:
cfg_defines = _cfg["defines"]
for define in cfg_defines:
print(f"{define}: {cfg_defines[define]}, {os.path.expandvars(cfg_defines[define])}")
defines[define] = os.path.expandvars(cfg_defines[define])
parse_cfg(cfg, base_path) parse_cfg(cfg, base_path)
@@ -60,6 +77,8 @@ def fpga_sim_main():
os.environ["MAKEFLAGS"] = "-j" os.environ["MAKEFLAGS"] = "-j"
# Turn this into a multiprocessing pool
for test in tests: for test in tests:
sources = rtl_manifest.read_sources(f"{test["base_path"]}/{test["sources"]}") sources = rtl_manifest.read_sources(f"{test["base_path"]}/{test["sources"]}")
@@ -68,7 +87,8 @@ def fpga_sim_main():
verilog_sources=sources, verilog_sources=sources,
hdl_toplevel=test["toplevel"], hdl_toplevel=test["toplevel"],
build_dir=f"{test["base_path"]}/sim_build", build_dir=f"{test["base_path"]}/sim_build",
waves=test["waves"] waves=test["waves"],
defines=defines
) )
result_xml = f"../sim_build/{test["name"]}_results.xml".replace(" ", "_") result_xml = f"../sim_build/{test["name"]}_results.xml".replace(" ", "_")