Fix verilator control files

src/fpga_sim/fpga_sim.py

@@ -3,7 +3,7 @@ import sys
 
 import argparse
 
-from cocotb_tools.runner import get_runner
+from cocotb_tools.runner import get_runner, VerilatorControlFile
 
 from rtl_manifest import rtl_manifest
 
@@ -95,8 +95,12 @@ def fpga_sim_main():
 
         sources, incdirs = rtl_manifest.parse(f"{test['base_path']}/{test['sources']}")
 
-        verilog_sources = list(filter(lambda s: (s.endswith(".v") or s.endswith(".sv") or s.endswith(".vlt")), sources))
+        verilog_sources = list(filter(lambda s: (s.endswith(".v") or s.endswith(".sv")), sources))
+        verilator_sources = [VerilatorControlFile(s) for s in list(filter(lambda s: (s.endswith(".vlt")), sources))]
 
+        sources = []
+        sources.extend(verilog_sources)
+        sources.extend(verilator_sources)
 
         build_args = ["--timing"]
 
@@ -105,7 +109,7 @@ def fpga_sim_main():
             build_args.append("--trace-fst")
 
         runner.build(
-            sources=verilog_sources,
+            sources=sources,
             includes=incdirs,
             hdl_toplevel=test["toplevel"],
             build_dir=f"{test['base_path']}/sim_build",