Filter out only verilog sources (and verilator lint files)

.gitea/workflows/publish.yaml

@@ -1,37 +0,0 @@
-name: Publish Package
-on: [push]
-
-jobs:
-  build:
-    name: Build Package
-    runs-on: ubuntu-latest
-
-    steps:
-      - uses: actions/checkout@v4
-      - uses: actions/setup-python@v5
-        with:
-          python-version: "3.x"
-      - run: python3 -m pip install build --user
-      - run: python -m build
-      - uses: actions/upload-artifact@v3
-        with:
-          name: python-package-distributions
-          path: dist/
-
-  deploy:
-    name: Deploy Package
-    needs:
-      - build
-    runs-on: ubuntu-latest
-    
-    steps:
-      - uses: actions/checkout@v4
-      - uses: actions/setup-python@v5
-        with:
-          python-version: "3.x"
-      - run: python3 -m pip install twine --user
-      - uses: actions/download-artifact@v3
-        name: python-package-distributions
-        path: dist/ # Does this even do anything?
-      - run: ls -laR python-package-distributions
-      - run: TWINE_PASSWORD=${{ secrets.PYPI_PAT }} TWINE_USERNAME=bslathi19 python -m twine upload --repository-url ${{ vars.CI_API_URL }} python-package-distributions/*

pyproject.toml

@@ -35,7 +35,7 @@ name = "fpga-sim"  # REQUIRED, is the only field that cannot be marked as dynami
 # https://packaging.python.org/guides/single-sourcing-package-version/
 
 # dynamic = ["version"]
-version = "0.5.2"  # REQUIRED, although can be dynamic
+version = "0.3.1"  # REQUIRED, although can be dynamic
 
 # This is a one-line description or tagline of what your project does. This
 # corresponds to the "Summary" metadata field:
@@ -122,7 +122,7 @@ classifiers = [
 # https://packaging.python.org/discussions/install-requires-vs-requirements/
 dependencies = [
   "pyyaml",
-  "cocotb>=2",
+  "cocotb",
   "rtl-manifest>=0.3.1"
 ]
 

src/fpga_sim/fpga_sim.py

@@ -3,9 +3,7 @@ import sys
 
 import argparse
 
-import subprocess
+from cocotb.runner import get_runner
-
-from cocotb_tools.runner import get_runner, VerilatorControlFile
 
 from rtl_manifest import rtl_manifest
 
@@ -97,36 +95,21 @@ def fpga_sim_main():
 
         sources, incdirs = rtl_manifest.parse(f"{test['base_path']}/{test['sources']}")
 
-        verilog_sources = list(filter(lambda s: (s.endswith(".v") or s.endswith(".sv")), sources))
+        verilog_sources = list(filter(lambda s: (s.endswith(".v") or s.endswith(".sv") or s.endswith(".vlt")), sources))
-        verilator_sources = [VerilatorControlFile(s) for s in list(filter(lambda s: (s.endswith(".vlt")), sources))]
 
-        sources = []
-        sources.extend(verilog_sources)
-        sources.extend(verilator_sources)
 
-        build_args = ["--timing"]
+        runner.build(
-
+            verilog_sources=verilog_sources,
-        # By default, verilator only uses vcd instead of fst, but fst is better.
+            includes=incdirs,
-        if test["waves"]:
+            hdl_toplevel=test["toplevel"],
-            build_args.append("--trace-fst")
+            build_dir=f"{test['base_path']}/sim_build",
-
+            waves=test["waves"],
-        try:
+            defines=defines
-            runner.build(
+        )
-                sources=sources,
-                includes=incdirs,
-                hdl_toplevel=test["toplevel"],
-                build_dir=f"{test['base_path']}/sim_build",
-                waves=test["waves"],
-                defines=defines,
-                build_args=build_args
-            )
-        except subprocess.CalledProcessError:
-            print("Failed to compile")
-            return
 
         result_xml = f"../sim_build/{test['name']}_results.xml".replace(" ", "_")
 
         sys.path.append(test["base_path"])
 
-        runner.test(hdl_toplevel_lang="verilog", hdl_toplevel=test["toplevel"], test_module=test["modules"], waves=test["waves"], results_xml=result_xml)
+        runner.test(hdl_toplevel=test["toplevel"], test_module=test["modules"], waves=test["waves"], results_xml=result_xml)