Filter out only verilog sources (and verilator lint files)

pyproject.toml

@@ -35,7 +35,7 @@ name = "fpga-sim"  # REQUIRED, is the only field that cannot be marked as dynami
 # https://packaging.python.org/guides/single-sourcing-package-version/
 
 # dynamic = ["version"]
-version = "0.3.2"  # REQUIRED, although can be dynamic
+version = "0.3.1"  # REQUIRED, although can be dynamic
 
 # This is a one-line description or tagline of what your project does. This
 # corresponds to the "Summary" metadata field:

src/fpga_sim/fpga_sim.py

@@ -104,8 +104,7 @@ def fpga_sim_main():
             hdl_toplevel=test["toplevel"],
             build_dir=f"{test['base_path']}/sim_build",
             waves=test["waves"],
-            defines=defines,
-            build_args=["--timing"]
+            defines=defines
         )
 
         result_xml = f"../sim_build/{test['name']}_results.xml".replace(" ", "_")