Add VERILATOR define by default

src/fpga_sim/fpga_sim.py

@@ -71,6 +71,8 @@ def fpga_sim_main():
                 print(f"{define}: {cfg_defines[define]}, {os.path.expandvars(cfg_defines[define])}")
                 defines[define] = os.path.expandvars(cfg_defines[define])
 
+            cfg_defines["VERILATOR"] = None
+
     parse_cfg(cfg, base_path)
 
     # 4: Run those tests
@@ -104,8 +106,7 @@ def fpga_sim_main():
             hdl_toplevel=test["toplevel"],
             build_dir=f"{test['base_path']}/sim_build",
             waves=test["waves"],
-            defines=defines,
-            build_args=["--timing"]
+            defines=defines
         )
 
         result_xml = f"../sim_build/{test['name']}_results.xml".replace(" ", "_")