Add VERILATOR define by default

.gitea/workflows/publish.yaml

@@ -1,37 +0,0 @@
-name: Publish Package
-on: [push]
-
-jobs:
-  build:
-    name: Build Package
-    runs-on: ubuntu-latest
-
-    steps:
-      - uses: actions/checkout@v4
-      - uses: actions/setup-python@v5
-        with:
-          python-version: "3.x"
-      - run: python3 -m pip install build --user
-      - run: python -m build
-      - uses: actions/upload-artifact@v3
-        with:
-          name: python-package-distributions
-          path: dist/
-
-  deploy:
-    name: Deploy Package
-    needs:
-      - build
-    runs-on: ubuntu-latest
-    
-    steps:
-      - uses: actions/checkout@v4
-      - uses: actions/setup-python@v5
-        with:
-          python-version: "3.x"
-      - run: python3 -m pip install twine --user
-      - uses: actions/download-artifact@v3
-        name: python-package-distributions
-        path: dist/ # Does this even do anything?
-      - run: ls -laR python-package-distributions
-      - run: TWINE_PASSWORD=${{ secrets.PYPI_PAT }} TWINE_USERNAME=bslathi19 python -m twine upload --repository-url ${{ vars.CI_API_URL }} python-package-distributions/*

pyproject.toml

@@ -35,7 +35,7 @@ name = "fpga-sim"  # REQUIRED, is the only field that cannot be marked as dynami
 # https://packaging.python.org/guides/single-sourcing-package-version/
 
 # dynamic = ["version"]
-version = "0.4.0a1"  # REQUIRED, although can be dynamic
+version = "0.3.2"  # REQUIRED, although can be dynamic
 
 # This is a one-line description or tagline of what your project does. This
 # corresponds to the "Summary" metadata field:

src/fpga_sim/fpga_sim.py

@@ -71,6 +71,8 @@ def fpga_sim_main():
                 print(f"{define}: {cfg_defines[define]}, {os.path.expandvars(cfg_defines[define])}")
                 defines[define] = os.path.expandvars(cfg_defines[define])
 
+            cfg_defines["VERILATOR"] = None
+
     parse_cfg(cfg, base_path)
 
     # 4: Run those tests
@@ -98,20 +100,13 @@ def fpga_sim_main():
         verilog_sources = list(filter(lambda s: (s.endswith(".v") or s.endswith(".sv") or s.endswith(".vlt")), sources))
 
 
-        build_args = ["--timing"]
-
-        # By default, verilator only uses vcd instead of fst, but fst is better.
-        if test["waves"]:
-            build_args.append("--trace-fst")
-
         runner.build(
             verilog_sources=verilog_sources,
             includes=incdirs,
             hdl_toplevel=test["toplevel"],
             build_dir=f"{test['base_path']}/sim_build",
             waves=test["waves"],
-            defines=defines,
-            build_args=build_args
+            defines=defines
         )
 
         result_xml = f"../sim_build/{test['name']}_results.xml".replace(" ", "_")