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exp/filter_verilog
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Byron Lathi 59b77618b0 Add VERILATOR define by default
2025-03-29 19:37:11 -07:00
src/fpga_sim
Add VERILATOR define by default
2025-03-29 19:37:11 -07:00
.gitignore
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2024-11-29 22:31:03 -08:00
.gitlab-ci.yml
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2024-11-29 22:31:03 -08:00
init_env.sh
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2024-11-29 22:31:03 -08:00
LICENSE.txt
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2024-11-29 22:31:03 -08:00
pyproject.toml
Add VERILATOR define by default
2025-03-29 19:37:11 -07:00
README.md
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2024-11-29 22:31:03 -08:00
requirements.txt
Add extra index url
2025-03-20 22:44:10 -07:00

README.md

FPGA Sim

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Description
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Readme 116 KiB
Languages
Python 98%
Shell 2%