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Kinda working

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This commit is contained in:
Byron Lathi
2026-04-18 16:18:57 -07:00
parent 50f8791588
commit 756b96d9e2
9 changed files with 143 additions and 17 deletions
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4
sim/verilog6502_wrapper_tb.sv
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@@ -11,6 +11,7 @@ logic rst;
logic o_irq_ext;
logic i_irq_ext;
logic i_nmi_ext;
verilog6502_wrapper u_dut(
@@ -22,7 +23,8 @@ verilog6502_wrapper u_dut(
.s_axi_rd(s_axi),
.s_axi_wr(s_axi),
.o_irq_ext(o_irq_ext),
.i_irq_ext(i_irq_ext)
.i_irq_ext(i_irq_ext),
.i_nmi_ext(i_nmi_ext)
);
endmodule

10
sim/verilog6502_wrapper_test.py
View File

@@ -29,12 +29,16 @@ async def test_sanity(dut):
for _ in range(10):
await RisingEdge(dut.clk)
await s_axi.write(0x0, [0x4c, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00])
await s_axi.write(0x200, [0x58, 0xa9, 0x00, 0x1a, 0xcb, 0x4c, 0x02, 0x03])
cocotb.start_soon(s_axi.read(0x0, 8))
cocotb.start_soon(s_axi.read(0x200, 8))
await Timer(10, "us")
await s_apb.write_dword(0x0, 0)
await Timer(10, "us")
await Timer(1, "us")
dut.i_nmi_ext.value = Immediate(1)
await Timer(1, "us")