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Byron Lathi 756b96d9e2 Kinda working
2026-04-18 16:18:57 -07:00
fpga
initial commit
2026-04-14 21:34:37 -07:00
sim
Kinda working
2026-04-18 16:18:57 -07:00
src
Kinda working
2026-04-18 16:18:57 -07:00
sub
Kinda working
2026-04-18 16:18:57 -07:00
.gitignore
initial commit
2026-04-14 21:34:37 -07:00
.gitmodules
initial commit
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init_env.sh
initial commit
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requirements.txt
initial commit
2026-04-14 21:34:37 -07:00
Description
No description provided
2.4 MiB
Languages
Verilog 79.7%
Tcl 14.5%
SystemVerilog 5.7%