Kinda working

2026-04-18 16:18:57 -07:00
parent 50f8791588
commit 756b96d9e2
9 changed files with 143 additions and 17 deletions
--- a/sim/verilog6502_wrapper_tb.sv
+++ b/sim/verilog6502_wrapper_tb.sv
@@ -11,6 +11,7 @@ logic rst;

 logic o_irq_ext;
 logic i_irq_ext;
+logic i_nmi_ext;


 verilog6502_wrapper u_dut(
@@ -22,7 +23,8 @@ verilog6502_wrapper u_dut(
    .s_axi_rd(s_axi),
    .s_axi_wr(s_axi),
    .o_irq_ext(o_irq_ext),
-    .i_irq_ext(i_irq_ext)
+    .i_irq_ext(i_irq_ext),
+    .i_nmi_ext(i_nmi_ext)
 );

 endmodule